| Project Settings |
|---|
| Project Name | CAN_SB_syn | Implementation Name | synthesis |
| Top Module | CAN_SB | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| Compile Input | Complete |
31 |
64 |
0 |
- |
0m:00s |
- |
1/7/2015
2:16:08 PM |
| Pre-mapping | Complete |
27 |
3 |
0 |
0m:00s |
0m:01s |
134MB |
1/7/2015
2:16:12 PM |
| Map & Optimize | Complete |
35 |
47 |
0 |
0m:01s |
0m:02s |
135MB |
1/7/2015
2:16:15 PM |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 1/7/2015
2:16:10 PM |
| Area Summary |
|---|
| |
| Sequential Cells | 0 |
DSP Blocks (MACC)
(dsp_used) | 0 |
| I/O Cells | 5 |
Global Clock Buffers | 1 |
| LUTs
(total_luts) | 0 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| CAN_SB_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | NA | NA |
| CAN_SB_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKINT_inferred_clock | 100.0 MHz | NA | NA |
| System | 100.0 MHz | 890.5 MHz | 8.877 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|