@W: BN132 :"e:\microsemi_prj\can_smartfusion2_tutorial\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance CAN_SB_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance CAN_SB_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"e:\microsemi_prj\can_smartfusion2_tutorial\component\work\can_sb_sb_mss\can_sb_sb_mss.v":241:0:241:13|Found inferred clock CAN_SB_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 54 sequential elements including CAN_SB_sb_0.CAN_SB_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\microsemi_prj\can_smartfusion2_tutorial\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Found inferred clock CAN_SB_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKINT_inferred_clock which controls 15 sequential elements including CAN_SB_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. 
