# Synopsys Constraint Checker(syntax only), version mapact, Build 1659R, built Dec 10 2015
# Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

# Written on Fri Mar 04 14:32:35 2016


##### DESIGN INFO #######################################################

Top View:                "SPI_Flash"
Constraint File(s):      "D:\Libero_11_7_publish\tu0548_spi_keil\designer\SPI_Flash\synthesis.fdc"

#Run constraint checker to find more issues with constraints.
#########################################################################



No issues found in constraint syntax.



Clock Summary
*************

Start                                               Requested     Requested     Clock                                                                Clock           
Clock                                               Frequency     Period        Type                                                                 Group           
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
SPI_Flash_sb_0/CCC_0/GL0                            100.0 MHz     10.000        generated (from SPI_Flash_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup
SPI_Flash_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     50.0 MHz      20.000        declared                                                             default_clkgroup
=====================================================================================================================================================================
