Project Settings
Project Name | SPI_Flash_syn | Implementation Name | synthesis
Top Module | SPI_Flash | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 34 | 64 | 0 | - | 0m:01s | - | 3/11/2016 6:58:43 PM
(premap) | Complete | 27 | 2 | 0 | 0m:00s | 0m:00s | 135MB | 3/11/2016 6:58:45 PM
(fpga_mapper) | Complete | 77 | 17 | 0 | 0m:01s | 0m:01s | 135MB | 3/11/2016 6:58:47 PM
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 3/11/2016 6:58:44 PM

Area Summary
Sequential Cells | 0 | DSP Blocks (MACC) (dsp_used) | 0
I/O Cells | 6 | Global Clock Buffers | 1
LUTs (total_luts) | 0 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
SPI_Flash_sb_0/CCC_0/GL0 | 100.0 MHz | NA | NA
SPI_Flash_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | NA | NA

Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |