Project Settings
Project Name | Sysservices_syn | Implementation Name | synthesis
Top Module | Sysservices | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 33 | 64 | 0 | - | 0m:00s | - | 14-03-2016 12:43:59
(premap) | Complete | 27 | 3 | 0 | 0m:00s | 0m:00s | 135MB | 14-03-2016 12:44:01
(fpga_mapper) | Complete | 37 | 32 | 0 | 0m:01s | 0m:01s | 134MB | 14-03-2016 12:44:02
Multi-srs Generator | Complete |  |  |  | 0m:01s |  |  | 14-03-2016 12:44:00

Area Summary
Sequential Cells | 0 | DSP Blocks (MACC) (dsp_used) | 0
I/O Cells | 2 | Global Clock Buffers | 1
LUTs (total_luts) | 0 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
Sysservices_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | NA | NA
Sysservices_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA

Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |