#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Thu Apr 22 10:32:20 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\CCC_0\mddr_ddr3_sb_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\FABOSC_0\mddr_ddr3_sb_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb_MSS\mddr_ddr3_sb_MSS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb_MSS\mddr_ddr3_sb_MSS.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\mddr_ddr3_sb.v" (library work) @I::"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module top @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... @N:CG364 : mddr_ddr3_sb_CCC_0_FCCC.v(5) | Synthesizing module mddr_ddr3_sb_CCC_0_FCCC in library work. Running optimization stage 1 on mddr_ddr3_sb_CCC_0_FCCC ....... @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 Running optimization stage 1 on CoreConfigP_Z1 ....... @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 Running optimization stage 1 on CoreResetP_Z2 ....... @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : mddr_ddr3_sb_FABOSC_0_OSC.v(5) | Synthesizing module mddr_ddr3_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on mddr_ddr3_sb_FABOSC_0_OSC ....... @W:CL318 : mddr_ddr3_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : mddr_ddr3_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : mddr_ddr3_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : mddr_ddr3_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : mddr_ddr3_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. Running optimization stage 1 on OUTBUF ....... @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work. Running optimization stage 1 on OUTBUF_DIFF ....... @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF in library work. Running optimization stage 1 on BIBUF_DIFF ....... @N:CG364 : mddr_ddr3_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... @N:CG364 : mddr_ddr3_sb_MSS.v(9) | Synthesizing module mddr_ddr3_sb_MSS in library work. Running optimization stage 1 on mddr_ddr3_sb_MSS ....... @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : mddr_ddr3_sb.v(9) | Synthesizing module mddr_ddr3_sb in library work. Running optimization stage 1 on mddr_ddr3_sb ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on mddr_ddr3_sb ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on mddr_ddr3_sb_MSS ....... Running optimization stage 2 on MSS_075 ....... Running optimization stage 2 on BIBUF_DIFF ....... Running optimization stage 2 on BIBUF ....... Running optimization stage 2 on OUTBUF_DIFF ....... Running optimization stage 2 on OUTBUF ....... Running optimization stage 2 on mddr_ddr3_sb_FABOSC_0_OSC ....... @N:CL159 : mddr_ddr3_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on CoreResetP_Z2 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. Running optimization stage 2 on CoreConfigP_Z1 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. Running optimization stage 2 on mddr_ddr3_sb_CCC_0_FCCC ....... Running optimization stage 2 on INBUF ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 97MB peak: 107MB) Process took 0h:00m:05s realtime, 0h:00m:04s cputime Process completed successfully. # Thu Apr 22 10:32:25 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\igloo2_task_feb_2021\SF2\TU0372_SF2_DDR3\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 22 10:32:26 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 23MB peak: 24MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime Process completed successfully. # Thu Apr 22 10:32:26 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File C:\igloo2_task_feb_2021\SF2\TU0372_SF2_DDR3\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 22 10:32:28 2021 ###########################################################] Premap Report # Thu Apr 22 10:32:28 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Reading constraint file: C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(10) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 132MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance MDDR_system_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MDDR_system_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance MDDR_system_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance MDDR_system_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_system_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance MDDR_system_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) @W:MT688 : synthesis.fdc(10) | No path from master pin (-source) to source of clock MDDR_system_sb_0/CCC_0/GL0 due to black box MDDR_system_sb_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------------------------------------- 0 - MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 109 0 - CLK0_PAD 100.0 MHz 10.000 declared default_clkgroup 0 1 . MDDR_system_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from CLK0_PAD) default_clkgroup 38 0 - MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 31 ===================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB 109 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075) MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST.CLK_MDDR_APB - MDDR_system_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) CLK0_PAD 0 CLK0_PAD(port) - - MDDR_system_sb_0.CCC_0.CLK0_PAD_INST.I(IBUF) MDDR_system_sb_0/CCC_0/GL0 38 MDDR_system_sb_0.CCC_0.CCC_INST.GL0(CCC) MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - MDDR_system_sb_0.CCC_0.GL0_INST.I(BUFG) MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 31 MDDR_system_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) MDDR_system_sb_0.CORERESETP_0.count_ddr_enable_q1.C - MDDR_system_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) ========================================================================================================================================================================================================================================================================================================== @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 168MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 170MB peak: 170MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 170MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Apr 22 10:32:30 2021 ###########################################################] Map & Optimize Report # Thu Apr 22 10:32:31 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 163MB peak: 163MB) @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : mddr_ddr3_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.mddr_ddr3_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[16] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[17] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[18] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[19] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[20] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[21] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[22] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[23] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[24] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[25] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[26] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[27] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[28] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[29] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[30] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[31] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[11] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[31] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[30] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[29] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[28] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[27] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[26] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[25] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[24] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[23] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[22] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[21] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.mddr_ddr3_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[14] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:BN132 : coreconfigp.v(546) | Removing instance MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_ddr[13:0] Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance MDDR_system_sb_0.CORERESETP_0.DDR_READY_int (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 170MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 170MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 170MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 170MB peak: 170MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s 7.49ns 113 / 141 @N:FP130 : | Promoting Net MDDR_system_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT I_49 @N:FP130 : | Promoting Net MDDR_system_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT I_50 @N:FP130 : | Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_51 @N:FP130 : | Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_52 @N:FP130 : | Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_53 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 171MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 171MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 37 clock pin(s) of sequential element(s) 0 instances converted, 37 sequential instances remain driven by gated/generated clocks ====================================================================== Non-Gated/Non-Generated Clocks ======================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 75 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST ClockId0003 MDDR_system_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 31 MDDR_system_sb_0.CORERESETP_0.count_ddr[13] ============================================================================================================================================================================= ========================================================================================= Gated/Generated Clocks ========================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 MDDR_system_sb_0.CCC_0.CCC_INST CCC 37 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ========================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 142MB peak: 171MB) Writing Analyst data base C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 170MB peak: 171MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 171MB peak: 171MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 170MB peak: 172MB) @W:MT246 : mddr_ddr3_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock CLK0_PAD with period 10.00ns @N:MT615 : | Found clock MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock MDDR_system_sb_0/CCC_0/GL0 with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Thu Apr 22 10:32:35 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 8.086 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CLK0_PAD 100.0 MHz NA 10.000 NA NA declared default_clkgroup MDDR_system_sb_0/CCC_0/GL0 100.0 MHz 522.4 MHz 10.000 1.914 8.086 generated (from CLK0_PAD) default_clkgroup MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 20.000 1.989 18.011 declared default_clkgroup MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 127.4 MHz 40.000 7.849 16.076 declared default_clkgroup ======================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 18.011 | No paths - | No paths - | No paths - MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT MDDR_system_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | 40.000 33.986 | No paths - | 20.000 18.118 | 20.000 16.076 MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB MDDR_system_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - MDDR_system_sb_0/CCC_0/GL0 MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - MDDR_system_sb_0/CCC_0/GL0 MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - MDDR_system_sb_0/CCC_0/GL0 MDDR_system_sb_0/CCC_0/GL0 | 10.000 8.086 | No paths - | No paths - | No paths - ================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MDDR_system_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.sm0_state[3] MDDR_system_sb_0/CCC_0/GL0 SLE Q sm0_state[3] 0.076 8.086 MDDR_system_sb_0.CORERESETP_0.release_sdif3_core_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q release_sdif3_core_clk_base 0.094 8.149 MDDR_system_sb_0.CORERESETP_0.sdif3_spll_lock_q2 MDDR_system_sb_0/CCC_0/GL0 SLE Q sdif3_spll_lock_q2 0.076 8.162 MDDR_system_sb_0.CORERESETP_0.release_sdif2_core_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q release_sdif2_core_clk_base 0.094 8.216 MDDR_system_sb_0.CORERESETP_0.ddr_settled_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q ddr_settled_clk_base 0.094 8.224 MDDR_system_sb_0.CORERESETP_0.release_sdif1_core_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q release_sdif1_core_clk_base 0.094 8.548 MDDR_system_sb_0.CORERESETP_0.sm0_state[4] MDDR_system_sb_0/CCC_0/GL0 SLE Q sm0_state[4] 0.094 8.561 MDDR_system_sb_0.CORERESETP_0.release_sdif0_core_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q release_sdif0_core_clk_base 0.094 8.615 MDDR_system_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base MDDR_system_sb_0/CCC_0/GL0 SLE Q CONFIG2_DONE_clk_base 0.094 8.760 MDDR_system_sb_0.CORERESETP_0.sm0_state[5] MDDR_system_sb_0/CCC_0/GL0 SLE Q sm0_state[5] 0.094 8.816 =============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.sm0_state[4] MDDR_system_sb_0/CCC_0/GL0 SLE D sm0_state_ns[4] 9.778 8.086 MDDR_system_sb_0.CORERESETP_0.sm0_state[5] MDDR_system_sb_0/CCC_0/GL0 SLE D sm0_state_ns[5] 9.778 8.159 MDDR_system_sb_0.CORERESETP_0.count_ddr_enable MDDR_system_sb_0/CCC_0/GL0 SLE D next_count_ddr_enable_0_sqmuxa 9.778 8.479 MDDR_system_sb_0.CORERESETP_0.count_ddr_enable MDDR_system_sb_0/CCC_0/GL0 SLE EN un1_next_ddr_ready_0_sqmuxa 9.707 8.493 MDDR_system_sb_0.CORERESETP_0.sm0_state[3] MDDR_system_sb_0/CCC_0/GL0 SLE D sm0_state_ns[3] 9.778 8.544 MDDR_system_sb_0.CORERESETP_0.sm0_state[6] MDDR_system_sb_0/CCC_0/GL0 SLE EN sm0_state_ns_a3[6] 9.707 8.816 MDDR_system_sb_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_system_sb_0/CCC_0/GL0 SLE D MSS_HPMS_READY_int_4 9.778 8.877 MDDR_system_sb_0.CORERESETP_0.mss_ready_select MDDR_system_sb_0/CCC_0/GL0 SLE EN mss_ready_select4 9.707 8.883 MDDR_system_sb_0.CORERESETP_0.sm0_state[2] MDDR_system_sb_0/CCC_0/GL0 SLE D sm0_state_ns[2] 9.778 8.906 MDDR_system_sb_0.CORERESETP_0.INIT_DONE_int MDDR_system_sb_0/CCC_0/GL0 SLE EN sm0_state[6] 9.707 9.391 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 1.692 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 8.086 Number of logic level(s): 2 Starting point: MDDR_system_sb_0.CORERESETP_0.sm0_state[3] / Q Ending point: MDDR_system_sb_0.CORERESETP_0.sm0_state[4] / D The start point is clocked by MDDR_system_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by MDDR_system_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.sm0_state[3] SLE Q Out 0.076 0.076 r - sm0_state[3] Net - - 0.648 - 3 MDDR_system_sb_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 B In - 0.724 r - MDDR_system_sb_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 Y Out 0.143 0.867 r - next_count_ddr_enable_0_sqmuxa Net - - 0.432 - 2 MDDR_system_sb_0.CORERESETP_0.sm0_state_ns[4] CFG3 C In - 1.299 r - MDDR_system_sb_0.CORERESETP_0.sm0_state_ns[4] CFG3 Y Out 0.177 1.476 r - sm0_state_ns[4] Net - - 0.216 - 1 MDDR_system_sb_0.CORERESETP_0.sm0_state[4] SLE D In - 1.692 r - ================================================================================================================================ Total path delay (propagation time + setup) of 1.914 is 0.618(32.3%) logic and 1.296(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.count_ddr[0] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[0] 0.076 18.011 MDDR_system_sb_0.CORERESETP_0.count_ddr[1] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[1] 0.076 18.295 MDDR_system_sb_0.CORERESETP_0.count_ddr[3] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[3] 0.076 18.314 MDDR_system_sb_0.CORERESETP_0.count_ddr[4] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[4] 0.094 18.350 MDDR_system_sb_0.CORERESETP_0.count_ddr[2] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[2] 0.076 18.382 MDDR_system_sb_0.CORERESETP_0.count_ddr[5] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[5] 0.076 18.386 MDDR_system_sb_0.CORERESETP_0.count_ddr[8] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[8] 0.094 18.418 MDDR_system_sb_0.CORERESETP_0.count_ddr[6] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[6] 0.076 18.423 MDDR_system_sb_0.CORERESETP_0.count_ddr[7] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[7] 0.076 18.454 MDDR_system_sb_0.CORERESETP_0.count_ddr[9] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[9] 0.094 18.457 ========================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.ddr_settled MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN ddr_settled4 19.706 18.011 MDDR_system_sb_0.CORERESETP_0.count_ddr[13] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[13] 19.778 18.411 MDDR_system_sb_0.CORERESETP_0.count_ddr[12] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[12] 19.778 18.425 MDDR_system_sb_0.CORERESETP_0.count_ddr[11] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[11] 19.778 18.440 MDDR_system_sb_0.CORERESETP_0.count_ddr[10] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[10] 19.778 18.454 MDDR_system_sb_0.CORERESETP_0.count_ddr[9] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[9] 19.778 18.468 MDDR_system_sb_0.CORERESETP_0.count_ddr[8] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[8] 19.778 18.482 MDDR_system_sb_0.CORERESETP_0.count_ddr[7] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[7] 19.778 18.497 MDDR_system_sb_0.CORERESETP_0.count_ddr[6] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[6] 19.778 18.511 MDDR_system_sb_0.CORERESETP_0.count_ddr[5] MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[5] 19.778 18.525 ============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 1.696 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 18.011 Number of logic level(s): 2 Starting point: MDDR_system_sb_0.CORERESETP_0.count_ddr[0] / Q Ending point: MDDR_system_sb_0.CORERESETP_0.ddr_settled / EN The start point is clocked by MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.076 0.076 r - count_ddr[0] Net - - 0.648 - 3 MDDR_system_sb_0.CORERESETP_0.ddr_settled4_9 CFG4 D In - 0.724 r - MDDR_system_sb_0.CORERESETP_0.ddr_settled4_9 CFG4 Y Out 0.284 1.008 f - ddr_settled4_9 Net - - 0.216 - 1 MDDR_system_sb_0.CORERESETP_0.ddr_settled4 CFG4 D In - 1.224 f - MDDR_system_sb_0.CORERESETP_0.ddr_settled4 CFG4 Y Out 0.250 1.474 f - ddr_settled4 Net - - 0.221 - 1 MDDR_system_sb_0.CORERESETP_0.ddr_settled SLE EN In - 1.696 f - =========================================================================================================== Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORECONFIGP_0.psel MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.076 16.076 MDDR_system_sb_0.CORECONFIGP_0.paddr[13] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[13] 0.094 18.118 MDDR_system_sb_0.CORECONFIGP_0.paddr[12] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[12] 0.094 18.267 MDDR_system_sb_0.CORECONFIGP_0.state[1] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 18.326 MDDR_system_sb_0.CORECONFIGP_0.paddr[15] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[15] 0.094 18.672 MDDR_system_sb_0.CORECONFIGP_0.state[0] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.695 MDDR_system_sb_0.CORECONFIGP_0.MDDR_PENABLE MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE Q CORECONFIGP_0_MDDR_APBmslave_PENABLE 0.094 18.934 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PRDATA[1] CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] 4.666 33.986 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PREADY CORECONFIGP_0_MDDR_APBmslave_PREADY 4.525 34.026 MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PRDATA[15] CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] 4.956 34.154 =================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE EN un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 19.706 16.076 MDDR_system_sb_0.CORECONFIGP_0.state[1] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D state_ns[1] 19.778 16.166 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 19.778 16.188 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.296 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 19.778 16.296 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 19.778 16.579 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 19.778 16.579 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 19.778 16.579 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 19.778 16.579 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[7] 19.778 16.579 ================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 3.631 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 16.076 Number of logic level(s): 4 Starting point: MDDR_system_sb_0.CORECONFIGP_0.psel / Q Ending point: MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY / EN The start point is clocked by MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=20.000 period=40.000) on pin CLK The end point is clocked by MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=20.000 period=40.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------- MDDR_system_sb_0.CORECONFIGP_0.psel SLE Q Out 0.076 0.076 r - psel Net - - 0.744 - 5 MDDR_system_sb_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa_0_0 CFG2 A In - 0.820 r - MDDR_system_sb_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa_0_0 CFG2 Y Out 0.087 0.907 f - un1_int_sel_0_sqmuxa_i Net - - 0.744 - 5 MDDR_system_sb_0.CORECONFIGP_0.prdata_e1_0_a2 CFG3 A In - 1.651 f - MDDR_system_sb_0.CORECONFIGP_0.prdata_e1_0_a2 CFG3 Y Out 0.087 1.738 r - prdata_e1 Net - - 1.010 - 18 MDDR_system_sb_0.CORECONFIGP_0.prdata_e1_0_a2_RNINCN2 CFG2 A In - 2.747 r - MDDR_system_sb_0.CORECONFIGP_0.prdata_e1_0_a2_RNINCN2 CFG2 Y Out 0.087 2.835 f - pready Net - - 0.432 - 2 MDDR_system_sb_0.CORECONFIGP_0.un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 CFG4 B In - 3.267 f - MDDR_system_sb_0.CORECONFIGP_0.un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 CFG4 Y Out 0.143 3.409 f - un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 Net - - 0.221 - 1 MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY SLE EN In - 3.631 f - ====================================================================================================================================== Total path delay (propagation time + setup) of 3.924 is 0.774(19.7%) logic and 3.150(80.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(13) | Timing constraint (from [get_cells { MDDR_system_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_rcosc MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (from [get_cells { MDDR_system_sb_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_system_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { MDDR_system_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(16) | Timing constraint (through [get_pins { MDDR_system_sb_0.mddr_ddr3_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(17) | Timing constraint (through [get_pins { MDDR_system_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(18) | Timing constraint (through [get_nets { MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { MDDR_system_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* MDDR_system_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 171MB peak: 172MB) Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 171MB peak: 172MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 7 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use CFG1 4 uses CFG2 19 uses CFG3 10 uses CFG4 32 uses Carry cells: ARI1 14 uses - used for arithmetic functions Sequential Cells: SLE 141 uses DSP Blocks: 0 of 84 (0%) I/O ports: 54 I/O primitives: 50 BIBUF 18 uses BIBUF_DIFF 2 uses INBUF 2 uses OUTBUF 27 uses OUTBUF_DIFF 1 use Global Clock Buffers: 7 Total LUTs: 79 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 141 + 0 + 0 + 0 = 141; Total number of LUTs after P&R: 79 + 0 + 0 + 0 = 79; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 64MB peak: 172MB) Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Thu Apr 22 10:32:36 2021 ###########################################################]