| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip SmartFusion2 : M2S090TS |
| Implementation Name | synthesis | Top Module | top |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
51 |
37 |
0 |
- |
00m:06s |
- |
4/22/2021
10:32:26 AM |
| (premap) | Complete |
38 |
19 |
0 |
0m:02s |
0m:02s |
170MB |
4/22/2021
10:32:30 AM |
| (fpga_mapper) | Complete |
41 |
21 |
0 |
0m:04s |
0m:05s |
172MB |
4/22/2021
10:32:36 AM |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 4/22/2021
10:32:28 AM |
| Area Summary |
|---|
| |
| Carry Cells | 14 |
Sequential Cells | 141 |
| DSP Blocks
(dsp_used) | 0 |
I/O Cells | 50 |
| Global Clock Buffers | 7 |
LUTs
(total_luts) | 79 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| CLK0_PAD | 100.0 MHz | NA | NA |
| MDDR_system_sb_0/CCC_0/GL0 | 100.0 MHz | 522.4 MHz | 8.086 |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 502.7 MHz | 18.011 |
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | 25.0 MHz | 127.4 MHz | 16.076 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 1 |
| |
|