@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\work\mddr_ddr3_sb\fabosc_0\mddr_ddr3_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\work\mddr_ddr3_sb\fabosc_0\mddr_ddr3_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\work\mddr_ddr3_sb\fabosc_0\mddr_ddr3_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\work\mddr_ddr3_sb\fabosc_0\mddr_ddr3_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\work\mddr_ddr3_sb\fabosc_0\mddr_ddr3_sb_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.mddr_ddr3_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[16] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[17] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[18] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[19] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[20] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[21] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[22] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[23] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[24] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[25] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[26] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[27] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[28] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[29] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[30] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.pwdata[31] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.paddr[11] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance CORECONFIGP_0.paddr[14] (in view: work.mddr_ddr3_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: MO231 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found counter in view:work.CoreResetP_Z2(verilog) instance count_ddr[13:0] 
@N: BN362 :"c:\igloo2_task_feb_2021\publish_final\sf2\new\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance MDDR_system_sb_0.CORERESETP_0.DDR_READY_int (in view: work.top(verilog)) because it does not drive other instances.
@N: FP130 |Promoting Net MDDR_system_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT  I_49 
@N: FP130 |Promoting Net MDDR_system_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_50 
@N: FP130 |Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_51 
@N: FP130 |Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_52 
@N: FP130 |Promoting Net MDDR_system_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT  I_53 
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock CLK0_PAD with period 10.00ns 
@N: MT615 |Found clock MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns 
@N: MT615 |Found clock MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns 
@N: MT615 |Found clock MDDR_system_sb_0/CCC_0/GL0 with period 10.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
