@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":729:7:729:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\CCC_0\mddr_ddr3_sb_CCC_0_FCCC.v":5:7:5:29|Synthesizing module mddr_ddr3_sb_CCC_0_FCCC in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\FABOSC_0\mddr_ddr3_sb_FABOSC_0_OSC.v":5:7:5:31|Synthesizing module mddr_ddr3_sb_FABOSC_0_OSC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":338:7:338:16|Synthesizing module BIBUF_DIFF in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb_MSS\mddr_ddr3_sb_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075 in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb_MSS\mddr_ddr3_sb_MSS.v":9:7:9:22|Synthesizing module mddr_ddr3_sb_MSS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v":720:7:720:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\mddr_ddr3_sb.v":9:7:9:18|Synthesizing module mddr_ddr3_sb in library work.
@N: CG364 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\work\mddr_ddr3_sb\FABOSC_0\mddr_ddr3_sb_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused.
@N: CL201 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":71:24:71:35|Input SDIF1_PREADY is unused.
@N: CL159 :"C:\igloo2_task_feb_2021\Publish_final\SF2\new\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":72:24:72:36|Input SDIF1_PSLVERR is unused.
@N|Running in 64-bit mode

