Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Thu Apr 8 13:24:55 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 405.502 100.0%
Static Power 236.000 58.2%
Dynamic Power 169.503 41.8%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 161.482 1.200 134.569
Rail VDDI 1.5 212.293 1.500 141.529
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038
Rail VDDI 2.5 4.402 2.500 1.761
Rail CCC_NE1_PLL_VDDA 9.000 3.300 2.727

Breakdown by Clock

Power (mW) Percentage
MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 131.533 94.4%
MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.083 0.1%
MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.139 0.1%
MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
CLK0_PAD (clocks) 3.885 2.8%
CLK0_PAD (register outputs) 0.001 0.0%
CLK0_PAD (primary inputs) 0.000 0.0%
CLK0_PAD (combinational outputs) 0.000 0.0%
CLK0_PAD (set/reset nets) 0.000 0.0%
MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.358 0.3%
MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.041 0.0%
MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.040 0.0%
MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (clocks) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (register outputs) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (primary inputs) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (clocks) 0.489 0.4%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (register outputs) 0.122 0.1%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (combinational outputs) 2.644 1.9%
MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
Input to Output 0.000 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 0.992 0.2%
Type Gate 11.035 2.7%
Type I/O 222.454 54.9%
Type Core Static 18.535 4.6%
Type Banks Static 0.613 0.2%
Type VPP Static 0.825 0.2%
Type Built-in Blocks 151.048 37.2%