SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Thu Apr 22 10:38:32 2021
| Design | top |
| Family | SmartFusion2 |
| Die | M2S090TS |
| Package | 484 FBGA |
| Temperature Range | 0 - 85 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST |
| Scenario for Timing Analysis | timing_analysis |
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| CLK0_PAD | 10.000 | 100.000 | ||
| MDDR_system_sb_0/CCC_0/GL0 | 10.000 | 100.000 | 5.422 | WORST |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 | 9.018 | WORST |
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | 40.000 | 25.000 | 1.675 | BEST |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin MDDR_system_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:D | 1.890 | 7.857 | 7.197 | 15.054 | 0.254 | 2.143 | WORST |
| Path 2 | MDDR_system_sb_0/CORERESETP_0/release_sdif3_core_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:D | 1.810 | 7.937 | 7.117 | 15.054 | 0.254 | 2.063 | WORST |
| Path 3 | MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[5]:D | 1.797 | 7.950 | 7.104 | 15.054 | 0.254 | 2.050 | WORST |
| Path 4 | MDDR_system_sb_0/CORERESETP_0/release_sdif3_core_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[5]:D | 1.707 | 8.040 | 7.014 | 15.054 | 0.254 | 1.960 | WORST |
| Path 5 | MDDR_system_sb_0/CORERESETP_0/sm0_state[5]:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[6]:EN | 1.340 | 8.320 | 6.664 | 14.984 | 0.308 | 1.680 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:D | ||||||||
| data required time | 15.054 | |||||||
| data arrival time | - | 7.197 | ||||||
| slack | 7.857 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.237 | 3.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 3.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 3.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.621 | 4.490 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.317 | 4.807 | 6 | r | |
| MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.500 | 5.307 | r | ||
| MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base:Q | cell | ADLIB:SLE | + | 0.108 | 5.415 | 1 | f | |
| MDDR_system_sb_0/CORERESETP_0/next_sm0_state25_1:A | net | MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_clk_base_Z | + | 0.321 | 5.736 | f | ||
| MDDR_system_sb_0/CORERESETP_0/next_sm0_state25_1:Y | cell | ADLIB:CFG2 | + | 0.164 | 5.900 | 1 | f | |
| MDDR_system_sb_0/CORERESETP_0/next_sm0_state25:C | net | MDDR_system_sb_0/CORERESETP_0/next_sm0_state25_1_Z | + | 0.761 | 6.661 | f | ||
| MDDR_system_sb_0/CORERESETP_0/next_sm0_state25:Y | cell | ADLIB:CFG4 | + | 0.087 | 6.748 | 2 | f | |
| MDDR_system_sb_0/CORERESETP_0/sm0_state_ns[4]:B | net | MDDR_system_sb_0/CORERESETP_0/next_sm0_state25_Z | + | 0.227 | 6.975 | f | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_state_ns[4]:Y | cell | ADLIB:CFG3 | + | 0.147 | 7.122 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:D | net | MDDR_system_sb_0/CORERESETP_0/sm0_state_ns_Z[4] | + | 0.075 | 7.197 | r | ||
| data arrival time | 7.197 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.237 | 13.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 13.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 13.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.617 | 14.486 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 14.803 | 11 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 | + | 0.505 | 15.308 | r | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:D | Library setup time | ADLIB:SLE | - | 0.254 | 15.054 | |||
| data required time | 15.054 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn | 4.240 | 5.422 | 9.534 | 14.956 | 0.353 | 4.578 | -0.015 | WORST |
| Path 2 | MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn | 4.240 | 5.422 | 9.534 | 14.956 | 0.353 | 4.578 | -0.015 | WORST |
| Path 3 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/sm0_state[4]:ALn | 2.813 | 6.818 | 8.137 | 14.955 | 0.353 | 3.182 | 0.016 | WORST |
| Path 4 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/release_sdif1_core_q1:ALn | 2.813 | 6.818 | 8.137 | 14.955 | 0.353 | 3.182 | 0.016 | WORST |
| Path 5 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled_clk_base:ALn | 2.813 | 6.818 | 8.137 | 14.955 | 0.353 | 3.182 | 0.016 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn | ||||||||
| data required time | 14.956 | |||||||
| data arrival time | - | 9.534 | ||||||
| slack | 5.422 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.237 | 3.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 3.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 3.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.621 | 4.490 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL | cell | ADLIB:RGB | + | 0.317 | 4.807 | 7 | r | |
| MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 | + | 0.487 | 5.294 | r | ||
| MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q | cell | ADLIB:SLE | + | 0.087 | 5.381 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n:B | net | MDDR_system_sb_0/CORERESETP_0/MSS_HPMS_READY_int_Z | + | 0.352 | 5.733 | r | ||
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n:Y | cell | ADLIB:CFG2 | + | 0.074 | 5.807 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9:An | net | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n | + | 1.905 | 7.712 | f | ||
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9:YEn | cell | ADLIB:GBM | + | 0.374 | 8.086 | 2 | f | |
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9/U0_RGB1_RGB0:An | net | MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9/U0_YWn_GEast | + | 0.612 | 8.698 | f | ||
| MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 9.015 | 2 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn | net | MDDR_system_sb_0/CORERESETP_0/sdif0_areset_n_RNIR2K9/U0_RGB1_RGB0_rgbl_net_1 | + | 0.519 | 9.534 | r | ||
| data arrival time | 9.534 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.237 | 13.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 13.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 13.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.635 | 14.504 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL | cell | ADLIB:RGB | + | 0.317 | 14.821 | 2 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_q1:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 | + | 0.488 | 15.309 | r | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn | Library recovery time | ADLIB:SLE | - | 0.353 | 14.956 | |||
| data required time | 14.956 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/release_sdif0_core:CLK | MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_q1:D | 0.772 | 6.946 | 8.121 | 15.067 | 0.254 | WORST |
| Path 2 | MDDR_system_sb_0/CORERESETP_0/release_sdif1_core:CLK | MDDR_system_sb_0/CORERESETP_0/release_sdif1_core_q1:D | 0.788 | 6.965 | 8.089 | 15.054 | 0.254 | WORST |
| Path 3 | MDDR_system_sb_0/CORERESETP_0/release_sdif2_core:CLK | MDDR_system_sb_0/CORERESETP_0/release_sdif2_core_q1:D | 0.613 | 7.126 | 7.921 | 15.047 | 0.254 | WORST |
| Path 4 | MDDR_system_sb_0/CORERESETP_0/ddr_settled:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled_q1:D | 0.601 | 7.144 | 7.923 | 15.067 | 0.254 | WORST |
| Path 5 | MDDR_system_sb_0/CORERESETP_0/release_sdif3_core:CLK | MDDR_system_sb_0/CORERESETP_0/release_sdif3_core_q1:D | 0.471 | 7.279 | 7.768 | 15.047 | 0.254 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/release_sdif0_core:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_q1:D | ||||||||
| data required time | 15.067 | |||||||
| data arrival time | - | 8.121 | ||||||
| slack | 6.946 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 1.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 1.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 5.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 5.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 6.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 6.815 | 14 | r | |
| MDDR_system_sb_0/CORERESETP_0/release_sdif0_core:CLK | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.534 | 7.349 | r | ||
| MDDR_system_sb_0/CORERESETP_0/release_sdif0_core:Q | cell | ADLIB:SLE | + | 0.087 | 7.436 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_q1:D | net | MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_Z | + | 0.685 | 8.121 | r | ||
| data arrival time | 8.121 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.237 | 13.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 13.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 13.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.617 | 14.486 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 14.803 | 11 | r | |
| MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_q1:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 | + | 0.518 | 15.321 | r | ||
| MDDR_system_sb_0/CORERESETP_0/release_sdif0_core_q1:D | Library setup time | ADLIB:SLE | - | 0.254 | 15.067 | |||
| data required time | 15.067 | |||||||
| Operating Conditions | WORST |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | 2.058 | 17.598 | 9.401 | 26.999 | 0.308 | 2.402 | WORST |
| Path 2 | MDDR_system_sb_0/CORERESETP_0/count_ddr[13]:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | 2.033 | 17.655 | 9.344 | 26.999 | 0.308 | 2.345 | WORST |
| Path 3 | MDDR_system_sb_0/CORERESETP_0/count_ddr[1]:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | 1.980 | 17.676 | 9.323 | 26.999 | 0.308 | 2.324 | WORST |
| Path 4 | MDDR_system_sb_0/CORERESETP_0/count_ddr[10]:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | 1.896 | 17.748 | 9.251 | 26.999 | 0.308 | 2.252 | WORST |
| Path 5 | MDDR_system_sb_0/CORERESETP_0/count_ddr[4]:CLK | MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | 1.884 | 17.760 | 9.239 | 26.999 | 0.308 | 2.240 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | ||||||||
| data required time | 26.999 | |||||||
| data arrival time | - | 9.401 | ||||||
| slack | 17.598 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 1.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 1.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 5.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 5.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 6.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 6.815 | 17 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:CLK | net | MDDR_system_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F | + | 0.528 | 7.343 | r | ||
| MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:Q | cell | ADLIB:SLE | + | 0.087 | 7.430 | 2 | r | |
| MDDR_system_sb_0/CORERESETP_0/ddr_settled4_8:B | net | MDDR_system_sb_0/CORERESETP_0/count_ddr_Z[7] | + | 0.618 | 8.048 | r | ||
| MDDR_system_sb_0/CORERESETP_0/ddr_settled4_8:Y | cell | ADLIB:CFG4 | + | 0.225 | 8.273 | 1 | f | |
| MDDR_system_sb_0/CORERESETP_0/ddr_settled4:C | net | MDDR_system_sb_0/CORERESETP_0/ddr_settled4_8_Z | + | 0.302 | 8.575 | f | ||
| MDDR_system_sb_0/CORERESETP_0/ddr_settled4:Y | cell | ADLIB:CFG4 | + | 0.287 | 8.862 | 1 | f | |
| MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | net | MDDR_system_sb_0/CORERESETP_0/ddr_settled4_Z | + | 0.539 | 9.401 | f | ||
| data arrival time | 9.401 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 21.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 21.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 25.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 25.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 26.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 26.815 | 17 | r | |
| MDDR_system_sb_0/CORERESETP_0/ddr_settled:CLK | net | MDDR_system_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F | + | 0.492 | 27.307 | r | ||
| MDDR_system_sb_0/CORERESETP_0/ddr_settled:EN | Library setup time | ADLIB:SLE | - | 0.308 | 26.999 | |||
| data required time | 26.999 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:ALn | 3.846 | 15.779 | 11.195 | 26.974 | 0.353 | 4.221 | 0.022 | WORST |
| Path 2 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr[5]:ALn | 3.846 | 15.779 | 11.195 | 26.974 | 0.353 | 4.221 | 0.022 | WORST |
| Path 3 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr[3]:ALn | 3.846 | 15.779 | 11.195 | 26.974 | 0.353 | 4.221 | 0.022 | WORST |
| Path 4 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr[1]:ALn | 3.846 | 15.779 | 11.195 | 26.974 | 0.353 | 4.221 | 0.022 | WORST |
| Path 5 | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr[11]:ALn | 3.846 | 15.779 | 11.195 | 26.974 | 0.353 | 4.221 | 0.022 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:ALn | ||||||||
| data required time | 26.974 | |||||||
| data arrival time | - | 11.195 | ||||||
| slack | 15.779 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 1.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 1.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 5.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 5.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 6.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 6.815 | 14 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.534 | 7.349 | r | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc:Q | cell | ADLIB:SLE | + | 0.087 | 7.436 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIEE25:An | net | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_0 | + | 1.905 | 9.341 | f | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIEE25:YEn | cell | ADLIB:GBM | + | 0.374 | 9.715 | 1 | f | |
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIEE25/U0_RGB1:An | net | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIEE25/U0_YWn_GEast | + | 0.594 | 10.309 | f | ||
| MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIEE25/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 10.626 | 17 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:ALn | net | MDDR_system_sb_0/CORERESETP_0/sm0_areset_n_rcosc_Z | + | 0.569 | 11.195 | r | ||
| data arrival time | 11.195 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 21.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 21.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 25.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 25.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 26.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 26.815 | 17 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:CLK | net | MDDR_system_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F | + | 0.512 | 27.327 | r | ||
| MDDR_system_sb_0/CORERESETP_0/count_ddr[7]:ALn | Library recovery time | ADLIB:SLE | - | 0.353 | 26.974 | |||
| data required time | 26.974 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/CORERESETP_0/count_ddr_enable:CLK | MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1:D | 2.699 | 9.018 | 8.035 | 17.053 | 0.254 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/CORERESETP_0/count_ddr_enable:CLK | ||||||||
| To: MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1:D | ||||||||
| data required time | 17.053 | |||||||
| data arrival time | - | 8.035 | ||||||
| slack | 9.018 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.237 | 3.237 | |||||
| MDDR_system_sb_0/CCC_0/GL0_INST:An | net | MDDR_system_sb_0/CCC_0/GL0_net | + | 0.454 | 3.691 | r | ||
| MDDR_system_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.178 | 3.869 | 6 | f | |
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.617 | 4.486 | f | ||
| MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 4.803 | 11 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr_enable:CLK | net | MDDR_system_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbl_net_1 | + | 0.533 | 5.336 | r | ||
| MDDR_system_sb_0/CORERESETP_0/count_ddr_enable:Q | cell | ADLIB:SLE | + | 0.087 | 5.423 | 1 | r | |
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST:A | net | MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_Z | + | 0.612 | 6.035 | r | ||
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST:Y | cell | ADLIB:CFG1A_TEST | + | 0.074 | 6.109 | 1 | r | |
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:A | net | mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST_net | + | 0.192 | 6.301 | r | ||
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:Y | cell | ADLIB:CFG1D_TEST | + | 0.345 | 6.646 | 1 | r | |
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:A | net | mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net0 | + | 0.308 | 6.954 | r | ||
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:Y | cell | ADLIB:CFG1D_TEST | + | 0.345 | 7.299 | 1 | r | |
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:A | net | mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net | + | 0.231 | 7.530 | r | ||
| mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:Y | cell | ADLIB:CFG1C_TEST | + | 0.202 | 7.732 | 1 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1:D | net | mdr_MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net | + | 0.303 | 8.035 | r | ||
| data arrival time | 8.035 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 10.000 | 10.000 | |||||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 10.000 | r | |||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 1.797 | 11.797 | r | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 11.949 | 1 | r | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_system_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.578 | 15.527 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.374 | 15.901 | 2 | f | |
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.597 | 16.498 | f | ||
| MDDR_system_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 16.815 | 17 | r | |
| MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1:CLK | net | MDDR_system_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F | + | 0.492 | 17.307 | r | ||
| MDDR_system_sb_0/CORERESETP_0/count_ddr_enable_q1:D | Library setup time | ADLIB:SLE | - | 0.254 | 17.053 | |||
| data required time | 17.053 | |||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 1.779 | 1.675 | 1.779 | 3.454 | 0.245 | -1.675 | BEST |
| Path 2 | MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | MDDR_system_sb_0/CORECONFIGP_0/state[0]:D | 1.387 | 2.098 | 1.387 | 3.485 | 0.201 | -2.098 | BEST |
| Path 3 | MDDR_system_sb_0/CORECONFIGP_0/psel:CLK | MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 3.479 | 15.953 | 9.097 | 25.050 | 0.308 | 8.094 | WORST |
| Path 4 | MDDR_system_sb_0/CORECONFIGP_0/psel:CLK | MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:D | 3.133 | 16.353 | 8.751 | 25.104 | 0.254 | 7.294 | WORST |
| Path 5 | MDDR_system_sb_0/CORECONFIGP_0/psel:CLK | MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[1]:D | 2.951 | 16.523 | 8.569 | 25.092 | 0.254 | 6.954 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | ||||||||
| To: MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | ||||||||
| data required time | 3.454 | |||||||
| data arrival time | - | 1.779 | ||||||
| slack | 1.675 | |||||||
| Data arrival time calculation | ||||||||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | 0.000 | 0.000 | ||||||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PSEL | cell | ADLIB:MSS_075_IP | + | 0.584 | 0.584 | 1 | f | |
| MDDR_system_sb_0/CORECONFIGP_0/next_state4:B | net | MDDR_system_sb_0/mddr_ddr3_sb_MSS_TMP_0_FIC_2_APB_MASTER_PSELx | + | 0.473 | 1.057 | f | ||
| MDDR_system_sb_0/CORECONFIGP_0/next_state4:Y | cell | ADLIB:CFG2 | + | 0.112 | 1.169 | 2 | f | |
| MDDR_system_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:C | net | MDDR_system_sb_0/CORECONFIGP_0/next_state4_Z | + | 0.068 | 1.237 | f | ||
| MDDR_system_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:Y | cell | ADLIB:CFG4 | + | 0.060 | 1.297 | 1 | f | |
| MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | net | MDDR_system_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0_Z | + | 0.482 | 1.779 | f | ||
| data arrival time | 1.779 | |||||||
| Data required time calculation | ||||||||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | Max Delay Constraint | 0.000 | 0.000 | |||||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN:An | net | MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/CLK_CONFIG_APB | + | 2.450 | 2.450 | f | ||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN:YEn | cell | ADLIB:GBM | + | 0.257 | 2.707 | 8 | f | |
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN/U0_RGB1_RGB5:An | net | MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN/U0_YWn_GEast | + | 0.414 | 3.121 | f | ||
| MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN/U0_RGB1_RGB5:YR | cell | ADLIB:RGB | + | 0.218 | 3.339 | 10 | r | |
| MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK | net | MDDR_system_sb_0/mddr_ddr3_sb_MSS_0/MSS_ADLIB_INST_RNITKN/U0_RGB1_RGB5_rgbr_net_1 | + | 0.360 | 3.699 | r | ||
| MDDR_system_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | Library setup time | ADLIB:SLE | - | 0.245 | 3.454 | |||
| data required time | 3.454 | |||||||
| Operating Conditions | BEST |
No Path
No Path
No Path
No Path
No Path
No Path
No Path