Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date      :  Wed Apr 14 10:34:46 2021
Project   :  C:\igloo2_task_feb_2021\Publish_final\SF2\TU_372\DDR3_SmartFusion2_Tutorial\Solution\Libero_Project
Component :  mddr_ddr3_sb
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/mddr_ddr3_sb.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/mddr_ddr3_sb.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/CCC_0/mddr_ddr3_sb_CCC_0_FCCC.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/FABOSC_0/mddr_ddr3_sb_FABOSC_0_OSC.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/mddr_ddr3_sb.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/mddr_ddr3_sb_MSS.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/mddr_ddr3_sb_MSS_syn.v

HDL source files for Mentor Precision Synthesis tool:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps_pre.v
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/mddr_ddr3_sb_MSS_pre.v

Stimulus files for all Simulation tools:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/subsystem.bfm
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/subsystem.bfm
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb/subsystem.bfm
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/CM3_compile_bfm.tcl
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/user.bfm
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/test.bfm
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm

Firmware files for all Software IDE tools:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/sys_config_mss_clocks.h
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/sys_config_mddr_define.h

Configuration files to be used for all Simulation tools:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/MDDR_init.bfm

Configuration files to be used for Power Analysis:
    C:/igloo2_task_feb_2021/Publish_final/SF2/TU_372/DDR3_SmartFusion2_Tutorial/Solution/Libero_Project/component/work/mddr_ddr3_sb_MSS/MDDR_init.reg

