*******************************************
       Libero SoC  and IP VERSIONS
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This tutorial is tested with following versions:

Libero SoC     --  Version: 12.6
System builder --  Version: 1.0

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     DESIGN FILE DIRECTORY STRUCTURE
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m2s_tu0372_df
    |
    |             
    |---Source_files
    |       |
    |       |----DDR3
    |       |      |
    |       |      |---- ddr3.v and ddr_parameters.v (ddr3 verilog models files)
    |       |      |---- DDR3_PHY_16_NO_ECC_BL8_INTER.txt (Configuration file)
    |       |
    |       |
    |       |---- wave.do
    |       |
    |       |---- user.bfm
    |
    |---Solution
    |      |
    |      |--Libero_Project (Verilog)
    |
    |---Readme.txt

Source_files
================================================
This folder consists of a set of pre-created files and a folder that can be used in this tutorial.

- wave.do :Predefined set of signals that can be used to check the results of the simulation.
- user.bfm	   :Automatically generated file by Libero SoC. Use this file to add your BFM read/write commands.					
	
- DDR3 folder:
	- ddr3.v                           : Micron DDR3 simulation models
	- ddr3_parameters.v	           :This file defines different timing parameters depending on the Speed Grade  of different DDR3 versions specified in the ddr3.v file
	- DDR3_PHY_16_NO_ECC_BL8_INTER.txt :This is a file in which you specify the different settings and configurations that  define the DDR controller behavior (Configuration file). 

Solution
===============================================
For reference, the final Libero SoC Verilog project of this tutorial is provided under this folder.




