@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3276:2:3276:7|Removing sequential instance myCIC_I.DownsampleCounterclkDrate64[5:0],  because it is equivalent to instance myCIC_Q.DownsampleCounterclkDrate64[5:0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un7_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un7_enDs[0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un6_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un6_enDs[0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un10_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un10_enDs[0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un9_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un9_enDs[0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3279:4:3279:5|Removing user instance myCIC_I.dcntProc1_64_proc.DownsampleCounterclkDrate64_4[5:0],  because it is equivalent to instance myCIC_Q.dcntProc1_64_proc.DownsampleCounterclkDrate64_4[5:0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un8_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un8_enDs[0]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":3312:19:3312:51|Removing user instance myCIC_I.Rate_block.un11_enDs[0],  because it is equivalent to instance myCIC_Q.Rate_block.un11_enDs[0]
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.myPhaseGenerator.shrp1_block.myshrp1.Delay0_block.GenBlock.genblk1.theDelay.outreg[32] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay3_block.GenBlock.genblk1.theDelay.outreg[0] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[4] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[7] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[10] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[11] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[13] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[14] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[15] reduced to a combinational gate by constant propagation
@W: MO129 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Sequential instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay1_block.GenBlock.genblk1.theDelay.outreg[16] reduced to a combinational gate by constant propagation
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Removing instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[16],  because it is equivalent to instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[4]
@W: BN132 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\synlib.v":607:6:607:11|Removing instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[15],  because it is equivalent to instance myDDS.mySinCos.myCORDIC_SinCos.myCORDIC2_stage.myCORDIC_onequadrant1.myCORDIC_stg1.Delay2_block.GenBlock.genblk1.theDelay.outreg[4]
@W: FX665 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":272:2:272:7|Removing instance CFIR_I_PolyphaseFIR_1_blockmyCFIR_I_PolyphaseFIR_1.inner_floopmem_22_[7] because it is equivalent to instance CFIR_I_PolyphaseFIR_1_blockmyCFIR_I_PolyphaseFIR_1.inner_floopmem_22_[6]
@W: FX665 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":110:2:110:7|Removing instance CFIR_I_PolyphaseFIR_0_blockmyCFIR_I_PolyphaseFIR_0.inner_floopmem_23_[7] because it is equivalent to instance CFIR_I_PolyphaseFIR_0_blockmyCFIR_I_PolyphaseFIR_0.inner_floopmem_23_[6]
@W: FX665 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":272:2:272:7|Removing instance CFIR_Q_PolyphaseFIR_1_blockmyCFIR_Q_PolyphaseFIR_1.inner_floopmem_22_[7] because it is equivalent to instance CFIR_Q_PolyphaseFIR_1_blockmyCFIR_Q_PolyphaseFIR_1.inner_floopmem_22_[6]
@W: FX665 :"e:\libero_11p7_updates\ll_11p6\m2s_tu0312_liberov11p6_df\solutions\verilog\ddc_top\hdl\ddc.v":110:2:110:7|Removing instance CFIR_Q_PolyphaseFIR_0_blockmyCFIR_Q_PolyphaseFIR_0.inner_floopmem_23_[7] because it is equivalent to instance CFIR_Q_PolyphaseFIR_0_blockmyCFIR_Q_PolyphaseFIR_0.inner_floopmem_23_[6]
