@W: CG107 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":161:23:161:25|Extending unsized constant with leading x/z beyond 32 bits
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_0_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_1_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_2_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_3_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_4_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":643:21:643:33|No assignment to delayLineClip_5_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":644:21:644:25|No assignment to regsL_0_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":644:21:644:25|No assignment to regsL_1_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":645:21:645:25|No assignment to regsR_0_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":645:21:645:25|No assignment to regsR_1_
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":646:21:646:23|No assignment to cnt
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":647:6:647:17|No assignment to resetExpired
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":648:6:648:12|No assignment to cntDone
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":352:12:352:23|No assignment to wire N_x_in_0_515
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":353:12:353:23|No assignment to wire N_y_in_0_516
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":354:12:354:23|No assignment to wire N_z_in_0_517
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":355:12:355:24|No assignment to wire N_x_out_1_518
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":356:12:356:24|No assignment to wire N_y_out_1_519
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":357:12:357:24|No assignment to wire N_z_out_1_520
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":521:12:521:23|No assignment to wire N_x_in_0_521
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":522:12:522:23|No assignment to wire N_y_in_0_522
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":523:12:523:23|No assignment to wire N_z_in_0_523
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":524:12:524:24|No assignment to wire N_x_out_1_524
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":525:12:525:24|No assignment to wire N_y_out_1_525
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":526:12:526:24|No assignment to wire N_z_out_1_526
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":690:12:690:23|No assignment to wire N_x_in_0_527
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":691:12:691:23|No assignment to wire N_y_in_0_528
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":692:12:692:23|No assignment to wire N_z_in_0_529
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":693:12:693:24|No assignment to wire N_x_out_1_530
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":694:12:694:24|No assignment to wire N_y_out_1_531
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":695:12:695:24|No assignment to wire N_z_out_1_532
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":859:12:859:23|No assignment to wire N_x_in_0_533
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":860:12:860:23|No assignment to wire N_y_in_0_534
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":861:12:861:23|No assignment to wire N_z_in_0_535
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":862:12:862:24|No assignment to wire N_x_out_1_536
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":863:12:863:24|No assignment to wire N_y_out_1_537
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":864:12:864:24|No assignment to wire N_z_out_1_538
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1028:12:1028:23|No assignment to wire N_x_in_0_539
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1029:12:1029:23|No assignment to wire N_y_in_0_540
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1030:12:1030:23|No assignment to wire N_z_in_0_541
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1031:12:1031:24|No assignment to wire N_x_out_1_542
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1032:12:1032:24|No assignment to wire N_y_out_1_543
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1033:12:1033:24|No assignment to wire N_z_out_1_544
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1197:12:1197:23|No assignment to wire N_x_in_0_545
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1198:12:1198:23|No assignment to wire N_y_in_0_546
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1199:12:1199:23|No assignment to wire N_z_in_0_547
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1200:12:1200:24|No assignment to wire N_x_out_1_548
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1201:12:1201:24|No assignment to wire N_y_out_1_549
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1202:12:1202:24|No assignment to wire N_z_out_1_550
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1366:12:1366:23|No assignment to wire N_x_in_0_551
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1367:12:1367:23|No assignment to wire N_y_in_0_552
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1368:12:1368:23|No assignment to wire N_z_in_0_553
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1369:12:1369:24|No assignment to wire N_x_out_1_554
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1370:12:1370:24|No assignment to wire N_y_out_1_555
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1371:12:1371:24|No assignment to wire N_z_out_1_556
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1535:12:1535:23|No assignment to wire N_x_in_0_557
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1536:12:1536:23|No assignment to wire N_y_in_0_558
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1537:12:1537:23|No assignment to wire N_z_in_0_559
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1538:12:1538:24|No assignment to wire N_x_out_1_560
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1539:12:1539:24|No assignment to wire N_y_out_1_561
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1540:12:1540:24|No assignment to wire N_z_out_1_562
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1704:12:1704:23|No assignment to wire N_x_in_0_563
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1705:12:1705:23|No assignment to wire N_y_in_0_564
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1706:12:1706:23|No assignment to wire N_z_in_0_565
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1707:12:1707:24|No assignment to wire N_x_out_1_566
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1708:12:1708:24|No assignment to wire N_y_out_1_567
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1709:12:1709:24|No assignment to wire N_z_out_1_568
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1873:12:1873:23|No assignment to wire N_x_in_0_569
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1874:12:1874:23|No assignment to wire N_y_in_0_570
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1875:12:1875:23|No assignment to wire N_z_in_0_571
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1876:12:1876:24|No assignment to wire N_x_out_1_572
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1877:12:1877:24|No assignment to wire N_y_out_1_573
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1878:12:1878:24|No assignment to wire N_z_out_1_574
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2042:12:2042:23|No assignment to wire N_x_in_0_575
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2043:12:2043:23|No assignment to wire N_y_in_0_576
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2044:12:2044:23|No assignment to wire N_z_in_0_577
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2045:12:2045:24|No assignment to wire N_x_out_1_578
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2046:12:2046:24|No assignment to wire N_y_out_1_579
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2047:12:2047:24|No assignment to wire N_z_out_1_580
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2203:12:2203:23|No assignment to wire N_z_in_0_581
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2204:12:2204:24|No assignment to wire N_x_out_1_582
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2205:12:2205:24|No assignment to wire N_y_out_1_583
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2206:12:2206:24|No assignment to wire N_z_out_1_584
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2270:12:2270:23|No assignment to wire N_x_in_0_585
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2271:12:2271:23|No assignment to wire N_y_in_0_586
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2272:12:2272:23|No assignment to wire N_z_in_0_587
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2273:12:2273:24|No assignment to wire N_x_out_1_588
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2274:12:2274:24|No assignment to wire N_y_out_1_589
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2434:12:2434:23|No assignment to wire N_z_in_0_590
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2435:12:2435:24|No assignment to wire N_x_out_1_591
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2436:12:2436:24|No assignment to wire N_y_out_1_592
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2601:11:2601:31|No assignment to wire N_GlobalEnable1_0_593
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2602:12:2602:23|No assignment to wire N_z_in_0_594
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2603:12:2603:24|No assignment to wire N_x_out_1_595
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2604:12:2604:24|No assignment to wire N_y_out_1_596
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2779:11:2779:31|No assignment to wire N_GlobalEnable1_0_597
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2780:12:2780:24|No assignment to wire N_theta_0_598
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2781:12:2781:22|No assignment to wire N_sin_1_599
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2782:12:2782:22|No assignment to wire N_cos_1_600
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2836:11:2836:31|No assignment to wire N_GlobalEnable1_0_601
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2837:12:2837:26|No assignment to wire N_phasein_0_602
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2838:12:2838:22|No assignment to wire N_sin_1_603
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2839:12:2839:22|No assignment to wire N_cos_1_604
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":1437:29:1437:32|No assignment to accU
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2947:12:2947:23|No assignment to wire N_freq_0_605
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2948:12:2948:23|No assignment to wire N_pout_1_606
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3212:11:3212:31|No assignment to wire N_GlobalEnable1_0_607
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3213:12:3213:23|No assignment to wire N_freq_0_608
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3214:12:3214:22|No assignment to wire N_sin_1_609
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3215:12:3215:22|No assignment to wire N_cos_1_610
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3086:12:3086:20|No assignment to wire N_x_0_641
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3087:12:3087:20|No assignment to wire N_y_1_642
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3155:12:3155:20|No assignment to wire N_x_0_651
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3156:12:3156:20|No assignment to wire N_y_1_652
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3272:12:3272:20|No assignment to wire N_x_0_653
@W: CG360 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3273:12:3273:20|No assignment to wire N_y_1_654
@W: CG133 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":2513:24:2513:29|No assignment to outreg
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 8 of inner_floop.mem_23_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 9 of inner_floop.mem_22_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 10 of inner_floop.mem_21_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 11 of inner_floop.mem_20_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 12 of inner_floop.mem_19_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 12 of inner_floop.mem_18_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bits 14 to 13 of inner_floop.mem_17_[14:0] 
@W: CL260 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":110:2:110:7|Pruning register bit 14 of inner_floop.mem_16_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bits 14 to 8 of inner_floop.mem_22_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bits 14 to 10 of inner_floop.mem_21_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bits 14 to 11 of inner_floop.mem_20_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bits 14 to 12 of inner_floop.mem_19_[14:0] 
@W: CL279 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bits 14 to 13 of inner_floop.mem_18_[14:0] 
@W: CL260 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":272:2:272:7|Pruning register bit 14 of inner_floop.mem_17_[14:0] 
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bit 14 of inp[14:0] is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":334:24:334:26|Input port bit 44 of inp[44:0] is unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bits 43 to 42 of inp[43:0] are unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bits 27 to 0 of inp[43:0] are unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bits 33 to 32 of inp[33:0] are unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2252:15:2252:18|Input port bits 13 to 0 of z_in[14:0] are unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2247:8:2247:10|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2248:8:2248:20|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2249:8:2249:18|Input GlobalReset is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1844:8:1844:10|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1845:8:1845:20|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1846:8:1846:18|Input GlobalReset is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1675:8:1675:10|Input clk is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1676:8:1676:20|Input GlobalEnable1 is unused
@W: CL159 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1677:8:1677:18|Input GlobalReset is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":334:24:334:26|Input port bit 15 of inp[15:0] is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":334:24:334:26|Input port bit 17 of inp[17:0] is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bit 17 of inp[17:0] is unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bit 13 of inp[13:0] is unused
@W: CL246 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":129:25:129:27|Input port bits 19 to 0 of inp[31:0] are unused
@W: CL247 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":334:24:334:26|Input port bit 15 of inp[16:0] is unused

