@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":621:7:621:31|Synthesizing module synDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":322:7:322:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":491:7:491:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":660:7:660:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":829:7:829:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":998:7:998:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1167:7:1167:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1336:7:1336:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1505:7:1505:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1674:7:1674:77|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":1843:7:1843:77|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2012:7:2012:77|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2181:7:2181:76|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2246:7:2246:77|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2387:7:2387:64|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2573:7:2573:44|Synthesizing module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":1920:7:1920:15|Synthesizing module synNegate
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2765:7:2765:30|Synthesizing module DDS_SinCos_CORDIC_SinCos
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2818:7:2818:16|Synthesizing module DDS_SinCos
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2931:7:2931:24|Synthesizing module DDS_PhaseGenerator
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":1428:7:1428:20|Synthesizing module synAccumulator
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2915:7:2915:33|Synthesizing module synDDS_PhaseGenerator_shrp1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":2899:7:2899:33|Synthesizing module synDDS_PhaseGenerator_shrp2
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3198:7:3198:9|Synthesizing module DDS
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3076:7:3076:14|Synthesizing module CIC_I_I1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":326:7:326:18|Synthesizing module synBusSatRnd
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":906:7:906:24|Synthesizing module synDelayWithEnable
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":600:7:600:34|Synthesizing module singleDelayWithEnableGeneric
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3060:7:3060:23|Synthesizing module synCIC_I_I1_Delay
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3145:7:3145:14|Synthesizing module CIC_I_C1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3129:7:3129:23|Synthesizing module synCIC_I_C1_Delay
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3248:7:3248:11|Synthesizing module CIC_I
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":117:7:117:19|Synthesizing module synBusAdapter
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":2508:7:2508:25|Synthesizing module synDownsampleSimple
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":3383:7:3383:9|Synthesizing module ddc
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":178:7:178:27|Synthesizing module CFIR_I_PolyphaseFIR_1
@N: CG364 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v":15:7:15:27|Synthesizing module CFIR_I_PolyphaseFIR_0
@N: CL135 :"E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v":762:6:762:11|Found seqShift GenBlock.asynch_implementation.RegisterStyle.delayline, depth=10, width=1
@N|Running in 64-bit mode

