

*******************************************
       Libero SoC  VERSIONS
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	This tutorial was tested with the following: 

	Libero SoC Version	: v11.7 
	Synphony Model compiler ME J-2015.03M  (used with matlab simulink software)
			Modelsim: v10.4c


  ==> Please note that VHDL Source Files ,Verilog Source Files are shared to User, incase user doesnot have the Matlab,synphony model compiler ME tools	



a) Smartfusion2/IGLOO2_DSP_ Flow_Tutorial.pdf 
   ===================================		

	This is the user's guide for this tutorial which includes step by step instructions 

				1) For converting the design created in Matlab simulink model file to verilog / VHDL RTL file. 
				2) Creating and simulating the design using Libero SoC design software.

    
b)  Source Files 
   ==============	

	

	Has 4 Folders DDC,VHDL source files,Verilog Source Files and ddc-impl_1 folder.
 	
        
	i)  The DDC Folder has 5 following files.
			
			Filename 		File type		Description 
			-======-                -=========		-==========

		1)	ddc.mdl     		Simulink Model file 	Design file
		2)	Inport_ddc_ADC 		DAT file		Input file provides ADC Signal values
		3)	Inport_ddc_Freq		DAT file		Input file provides Frequency Values	
		4)	Outport_ddc_I_out	DAT file		Output file in-phase 
		5)	Outport_ddc_Q_out	DAT file		Output file quadrature phase 


 
	ii)	VHDL_Source_Files  has following files
		---------------------------------------------------------------
			
		Filename 		File type		Description 
		-======-               -=========		-==========

		a) SynLib_asynch.vhd	 VHDL			Source file to Libero project
		b) ddc.vhd		 VHDL			Source file to Libero project

		c) ddc_Test.vhd	 	 vHDL			Test bench Source file to Modelsim 



	iii)	verilog_Source_Files has following files
		------------------------------------------------
			
		Filename 		File type		Description 
		-======-               -=========		-==========

		a) SynLib.v	 	Verilog			Source file to Libero project
		b) ddc.v		Verilog			Source file to Libero project
		c) define.h		Header file		Source file to Libero project

		d) ddc_Test.v	 	verilog			Test bench Source file to Modelsim  


	
		

c) Solution -- (Libero SOC Project) - 
   ===============================

	For reference, the final Libero SoC VHDL and Verilog projects of this tutorial are given under this folder.

	a) Verilog project
	b) VHDL project

	
d) Readme.txt
   ==========
	
	Explains the structure of Smartfusion2/Igloo2_DSP_FLOW_Tutorial folder

