KEY LIBERO "11.7"
KEY CAPTURE "11.7.0.119"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2"
KEY ProjectID "0"
KEY HDLTechnology "VERILOG"
KEY UseConstraintFlowTechnology "TRUE"
KEY VendorTechnology_Family "SmartFusion2"
KEY VendorTechnology_Die "PA4M5000"
KEY VendorTechnology_Package "fg896"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
KEY VendorTechnology_TARGETDEVICESFORMIGRATION "PA4M5000"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.2_VOLTR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "ddc::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\constraint\ddc.sdc,sdc"
STATE="utd"
TIME="1456992985"
SIZE="260"
ENDFILE
VALUE "<project>\designer\impl1\ddc.ide_des,ide_des"
STATE="utd"
TIME="1456992963"
SIZE="237"
ENDFILE
VALUE "<project>\hdl\ddc.v,hdl"
STATE="utd"
TIME="1456992320"
SIZE="112070"
ENDFILE
VALUE "<project>\hdl\define.h,hdl"
STATE="utd"
TIME="1456992320"
SIZE="474"
ENDFILE
VALUE "<project>\hdl\SynLib.v,hdl"
STATE="utd"
TIME="1456992320"
SIZE="75135"
ENDFILE
VALUE "<project>\simulation\Inport_ddc_ADC.dat,sim"
STATE="utd"
TIME="1456992407"
SIZE="960012"
ENDFILE
VALUE "<project>\simulation\Inport_ddc_Freq.dat,sim"
STATE="utd"
TIME="1456992407"
SIZE="2720034"
ENDFILE
VALUE "<project>\simulation\Outport_ddc_I_out.dat,sim"
STATE="utd"
TIME="1456992407"
SIZE="10016"
ENDFILE
VALUE "<project>\simulation\Outport_ddc_Q_out.dat,sim"
STATE="utd"
TIME="1456992407"
SIZE="10016"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1456992452"
SIZE="816"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1456992642"
SIZE="233"
ENDFILE
VALUE "<project>\simulation\test_ddc_presynth_simulation.log,log"
STATE="utd"
TIME="1456992456"
SIZE="5980"
ENDFILE
VALUE "<project>\stimulus\ddc_Test.v,tb_hdl"
STATE="utd"
TIME="1456992334"
SIZE="10954"
ENDFILE
VALUE "<project>\synthesis\ddc.edn,syn_edn"
STATE="utd"
TIME="1456993069"
SIZE="7413714"
ENDFILE
VALUE "<project>\synthesis\ddc.so,so"
STATE="utd"
TIME="1456993069"
SIZE="258"
ENDFILE
VALUE "<project>\synthesis\ddc.v,syn_hdl"
STATE="utd"
TIME="1456993094"
SIZE="2021744"
ENDFILE
VALUE "<project>\synthesis\ddc_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1456993069"
SIZE="1082"
ENDFILE
VALUE "<project>\synthesis\ddc_syn.prj,prj"
STATE="utd"
TIME="1456992996"
SIZE="1235"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "ddc::work"
FILE "<project>\hdl\ddc.v,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\ddc_Test.v,tb_hdl"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\constraint\ddc.sdc,sdc"
ENDLIST
LIST TimingConstraints
VALUE "<project>\constraint\ddc.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\ddc.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST ddc
VALUE "<project>\stimulus\ddc_Test.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=-all
Resolution=1fs
VsimOpt=
EntityName=test_ddc
TopInstanceName=i_ddc
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Microsemi\Libero_SoC_v11.7\SoftConsole\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_SoC_v11.7\Synplify\bin\synplify_pro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_SoC_v11.7\Model\win32acoem\modelsim.exe"
PARAM=" -l test_ddc_presynth_simulation.log "
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_SoC_v11.7\Designer\bin\flashpro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_SoC_v11.7\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "ddc::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSTIMULUS=StateSuccess
ideSYNTHESIS(<project>\synthesis\ddc.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Verify Timing:ddc_max_timing_slow_1.14V_85C.xml
StartPage;StartPage;0
Constraint Manager;Constraint Manager;0
HDL;constraint\ddc.sdc;0
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
LIST "CFIR_I_PolyphaseFIR_0::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "CFIR_I_PolyphaseFIR_1::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "CIC_I::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "CIC_I_C1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "CIC_I_I1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "CIC_I_C1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synCIC_I_C1_Delay::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "CIC_I_I1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synCIC_I_I1_Delay::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "ddc::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "CFIR_I_PolyphaseFIR_0::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "CFIR_I_PolyphaseFIR_1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "CIC_I::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDownsampleSimple::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_PhaseGenerator::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_PhaseGenerator::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synAccumulator::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDDS_PhaseGenerator_shrp1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synDDS_PhaseGenerator_shrp2::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synNegate::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "singleDelayWithEnableGeneric::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAbs::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAccumulator::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAccumulatorMC::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAccumulatorMCOvf::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAccumulatorOvf::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synAddSub::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synBinLogic::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synBusAdapter::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synBusAdapter_sat::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synBusSatRnd_sat::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synBusSatRnd::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synBusSatRnd_sat::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCIC_I_C1_Delay::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCIC_I_I1_Delay::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synComparator::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCounter::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCounterFR::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCounterFRMC::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCounterMC::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCounterSync::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synCSAUnit::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synDDS_PhaseGenerator_shrp1::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synDDS_PhaseGenerator_shrp2::work","hdl\ddc.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "singleDelayWithEnableGeneric::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnableGeneric::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synDelayWithEnableGeneric::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synDownsampleSimple::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synFIFO::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synFIFO_MC::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synFIFO::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synGain::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synInverter::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synMult::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synMultiRateFIFO::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synMux::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synNegate::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synPipelinedAdd::work","hdl\SynLib.v","FALSE","FALSE"
SUBBLOCK "synDelayWithEnable::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synRegister::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synRegister_MC::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synRobustLatch::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synShifter::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synShifterR::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synSRL::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "synStepFunction::work","hdl\SynLib.v","FALSE","FALSE"
ENDLIST
LIST "clock_div::work","stimulus\ddc_Test.v","FALSE","TRUE"
ENDLIST
LIST "clock_gen::work","stimulus\ddc_Test.v","FALSE","TRUE"
ENDLIST
LIST "clocks::work","stimulus\ddc_Test.v","FALSE","TRUE"
SUBBLOCK "clock_gen::work","stimulus\ddc_Test.v","FALSE","TRUE"
ENDLIST
LIST "test_ddc::work","stimulus\ddc_Test.v","FALSE","TRUE"
SUBBLOCK "clocks::work","stimulus\ddc_Test.v","FALSE","TRUE"
SUBBLOCK "ddc::work","hdl\ddc.v","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
VALUE "constraint\ddc.sdc"
ENDLIST
LIST FDCTabList
ENDLIST
