-------------------------------------
 External Hold Repair Report 
-------------------------------------
 Iteration 1  
 Total I/O input ports improved: 0       
-------------------------------------



-------------------------
 Min-delay Repair Report 
-------------------------
 Iteration 1  
 Total paths found:    8       
 Total paths improved: 8       
-------------------------

Path 1
------------------------
From: myCIC_I/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[14]:CLK
  To: myCIC_I/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[14]:D
------------------------
Path min-delay slack:       -36 ps
------------------------
  On sink pin: myCIC_I/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[14]:D
-------------------------------------
  Pin max-delay slack:    24707 ps
  Min-delay inserted:       405 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_I/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[14]_CFG1A_TEST


Path 2
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[31]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[31]:D
------------------------
Path min-delay slack:       -18 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[31]:D
-------------------------------------
  Pin max-delay slack:    24676 ps
  Min-delay inserted:       599 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[31]_CFG1A_TEST


Path 3
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[19]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[19]:D
------------------------
Path min-delay slack:       -16 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[19]:D
-------------------------------------
  Pin max-delay slack:    24673 ps
  Min-delay inserted:       423 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[19]_CFG1A_TEST


Path 4
------------------------
From: myCIC_I/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[10]:CLK
  To: myCIC_I/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[10]:D
------------------------
Path min-delay slack:       -15 ps
------------------------
  On sink pin: myCIC_I/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[10]:D
-------------------------------------
  Pin max-delay slack:    24668 ps
  Min-delay inserted:       501 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_I/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[10]_CFG1A_TEST


Path 5
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[37]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[37]:D
------------------------
Path min-delay slack:       -13 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[37]:D
-------------------------------------
  Pin max-delay slack:    24669 ps
  Min-delay inserted:       359 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[37]_CFG1D_TEST


Path 6
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[15]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[15]:D
------------------------
Path min-delay slack:        -9 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[15]:D
-------------------------------------
  Pin max-delay slack:    24659 ps
  Min-delay inserted:       402 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[15]_CFG1A_TEST


Path 7
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[6]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[6]:D
------------------------
Path min-delay slack:        -4 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[6]:D
-------------------------------------
  Pin max-delay slack:    24650 ps
  Min-delay inserted:       322 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[6]_CFG1C_TEST


Path 8
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[41]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[41]:D
------------------------
Path min-delay slack:        -1 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[41]:D
-------------------------------------
  Pin max-delay slack:    24646 ps
  Min-delay inserted:       309 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[41]_CFG1C_TEST




-------------------------------------
 External Hold Repair Report 
-------------------------------------
 Iteration 2  
 Total I/O input ports improved: 0       
-------------------------------------



-------------------------
 Min-delay Repair Report 
-------------------------
 Iteration 2  
 Total paths found:    1       
 Total paths improved: 1       
-------------------------

Path 1
------------------------
From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[17]:CLK
  To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[17]:D
------------------------
Path min-delay slack:       -11 ps
------------------------
  On sink pin: myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[17]:D
-------------------------------------
  Pin max-delay slack:    24661 ps
  Min-delay inserted:       422 ps ( Estimated )
  ----------------------------
  Delay buffers inserted before the sink:
      mdr_myCIC_Q/myC1/Delay_syn_block_myDelay_syn/Delay0_block/GenBlock_genblk1_theDelay/outreg[17]_CFG1A_TEST




-------------------------------------
 External Hold Repair Report 
-------------------------------------
 Iteration 3  
 Total I/O input ports improved: 0       
-------------------------------------



-------------------------
 Min-delay Repair Report 
-------------------------
 Iteration 3  
 Total paths found:    0       
 Total paths improved: 0       
-------------------------


Note:
    [1]: A net cannot be modified for repair if:
         - it is hardwired, preserved, or global;
         - the sink pin is a clock pin;
         - the sink pin has negative max-delay slack allowance;
         - the sink and driving pins are placed in the same cluster.

    [2]: A location is not feasible for inserting a delay buffer if the estimated minimum delay to be inserted might exceed the max-delay slack allowance of the sink pin.



