<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.7.0.119</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Thu Mar 03 13:59:05 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>ddc</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S050T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>896 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>STD</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>clk</cell>
 <cell>17.130</cell>
 <cell>58.377</cell>
 <cell>25.000</cell>
 <cell>40.000</cell>
 <cell>15.252</cell>
 <cell>0.414</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>9.147</cell>
 <cell>109.325</cell>
 <cell>3200.000</cell>
 <cell>0.313</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>4.014</cell>
 <cell>9.387</cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>10.964</cell>
 <cell>91.208</cell>
 <cell>1600.000</cell>
 <cell>0.625</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain clk</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>myDDS/myPhaseGenerator/shrp2_block.myshrp2/Delay0_block/GenBlock.genblk1.theDelay/outreg[23]:CLK</cell>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:D</cell>
 <cell>0.285</cell>
 <cell>0.242</cell>
 <cell>2.407</cell>
 <cell>2.165</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/Delay1_block/GenBlock.genblk1.theDelay/GenBlock.asynch_implementation.RegisterStyle.delayline_0__0_[0]:CLK</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/Delay1_block/GenBlock.genblk1.theDelay/GenBlock.asynch_implementation.RegisterStyle.delayline_1__0_[0]:D</cell>
 <cell>0.293</cell>
 <cell>0.250</cell>
 <cell>2.414</cell>
 <cell>2.164</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Freq_block.med[24]:CLK</cell>
 <cell>myDDS/myPhaseGenerator/shrp1_block.myshrp1/Delay0_block/GenBlock.genblk1.theDelay/outreg[24]:D</cell>
 <cell>0.293</cell>
 <cell>0.251</cell>
 <cell>2.417</cell>
 <cell>2.166</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[2]:CLK</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg1/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:D</cell>
 <cell>0.296</cell>
 <cell>0.252</cell>
 <cell>2.426</cell>
 <cell>2.174</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Freq_block.med[23]:CLK</cell>
 <cell>myDDS/myPhaseGenerator/shrp1_block.myshrp1/Delay0_block/GenBlock.genblk1.theDelay/outreg[23]:D</cell>
 <cell>0.298</cell>
 <cell>0.253</cell>
 <cell>2.428</cell>
 <cell>2.175</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: myDDS/myPhaseGenerator/shrp2_block.myshrp2/Delay0_block/GenBlock.genblk1.theDelay/outreg[23]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.407</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.165</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.242</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clk</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.104</cell>
 <cell>1.104</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>1.270</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.325</cell>
 <cell>15</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.285</cell>
 <cell>1.610</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>1.807</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/myPhaseGenerator/shrp2_block.myshrp2/Delay0_block/GenBlock.genblk1.theDelay/outreg[23]:CLK</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.315</cell>
 <cell>2.122</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/myPhaseGenerator/shrp2_block.myshrp2/Delay0_block/GenBlock.genblk1.theDelay/outreg[23]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>2.179</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:D</cell>
 <cell>net</cell>
 <cell>myDDS/N_3[23]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.228</cell>
 <cell>2.407</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.407</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clk</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.104</cell>
 <cell>1.104</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>1.270</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.325</cell>
 <cell>15</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.285</cell>
 <cell>1.610</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>1.807</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:CLK</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>2.165</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.165</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.165</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Freq[12]</cell>
 <cell>Freq_block.med[12]:D</cell>
 <cell>1.959</cell>
 <cell></cell>
 <cell>1.959</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.414</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Freq[2]</cell>
 <cell>Freq_block.med[2]:D</cell>
 <cell>1.967</cell>
 <cell></cell>
 <cell>1.967</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.398</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Freq[10]</cell>
 <cell>Freq_block.med[10]:D</cell>
 <cell>2.065</cell>
 <cell></cell>
 <cell>2.065</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.309</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Freq[0]</cell>
 <cell>Freq_block.med[0]:D</cell>
 <cell>2.066</cell>
 <cell></cell>
 <cell>2.066</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.305</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Freq[29]</cell>
 <cell>Freq_block.med[29]:D</cell>
 <cell>2.075</cell>
 <cell></cell>
 <cell>2.075</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.289</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Freq[12]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Freq_block.med[12]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.959</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Freq[12]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_ibuf[12]/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>Freq[12]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_ibuf[12]/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.104</cell>
 <cell>1.104</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_ibuf[12]/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>Freq_ibuf[12]/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.104</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_ibuf[12]/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.051</cell>
 <cell>1.155</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_block.med[12]:D</cell>
 <cell>net</cell>
 <cell>Freq_c[12]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.804</cell>
 <cell>1.959</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.959</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clk</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.227</cell>
 <cell>N/C</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.061</cell>
 <cell>N/C</cell>
 <cell>15</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB24:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.313</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB24:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>N/C</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_block.med[12]:CLK</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB24_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Freq_block.med[12]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>External Removal (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>GlobalReset</cell>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:ALn</cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.132</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>GlobalReset</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg1/Delay3_block/GenBlock.genblk1.theDelay/outreg[4]:ALn</cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.132</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>GlobalReset</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg7/Delay3_block/GenBlock.genblk1.theDelay/outreg[0]:ALn</cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.132</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>GlobalReset</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg8/Delay3_block/GenBlock.genblk1.theDelay/outreg[0]:ALn</cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.132</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>GlobalReset</cell>
 <cell>myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg5/Delay1_block/GenBlock.genblk1.theDelay/outreg[1]:ALn</cell>
 <cell>2.238</cell>
 <cell></cell>
 <cell>2.238</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.128</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.140</cell>
 <cell>1.140</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.185</cell>
 <cell>1.325</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.127</cell>
 <cell>1.452</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB20:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>1.731</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB20:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.885</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:ALn</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB20_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.233</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clk</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.227</cell>
 <cell>N/C</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.184</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.061</cell>
 <cell>N/C</cell>
 <cell>15</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:CLK</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_RGB9_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myDDS/mySinCos/Delay3_block/GenBlock.genblk1.theDelay/outreg[3]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain clkDiv128</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_15_[13]:CLK</cell>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_14_[13]:D</cell>
 <cell>0.289</cell>
 <cell>0.254</cell>
 <cell>2.431</cell>
 <cell>2.177</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CFIR_I_PolyphaseFIR_0_block.myCFIR_I_PolyphaseFIR_0/inner_floop.mem_5_[13]:CLK</cell>
 <cell>CFIR_I_PolyphaseFIR_0_block.myCFIR_I_PolyphaseFIR_0/inner_floop.mem_4_[13]:D</cell>
 <cell>0.289</cell>
 <cell>0.255</cell>
 <cell>2.426</cell>
 <cell>2.171</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>CFIR_Q_PolyphaseFIR_0_block.myCFIR_Q_PolyphaseFIR_0/inner_floop.mem_5_[13]:CLK</cell>
 <cell>CFIR_Q_PolyphaseFIR_0_block.myCFIR_Q_PolyphaseFIR_0/inner_floop.mem_4_[13]:D</cell>
 <cell>0.289</cell>
 <cell>0.255</cell>
 <cell>2.401</cell>
 <cell>2.146</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_15_[12]:CLK</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_14_[12]:D</cell>
 <cell>0.296</cell>
 <cell>0.256</cell>
 <cell>2.431</cell>
 <cell>2.175</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_8_[0]:CLK</cell>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_7_[0]:D</cell>
 <cell>0.297</cell>
 <cell>0.261</cell>
 <cell>2.456</cell>
 <cell>2.195</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_15_[13]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_14_[13]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.431</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.177</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.109</cell>
 <cell>1.109</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.176</cell>
 <cell>1.285</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.340</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>1.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>1.826</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_15_[13]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>2.142</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_15_[13]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>2.196</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_14_[13]:D</cell>
 <cell>net</cell>
 <cell>CFIR_I_PolyphaseFIR_1_block_myCFIR_I_PolyphaseFIR_1/mem_15_[13]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.235</cell>
 <cell>2.431</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.431</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.109</cell>
 <cell>1.109</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.176</cell>
 <cell>1.285</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.340</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>1.630</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>1.826</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_14_[13]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>2.177</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_I_PolyphaseFIR_1_block.myCFIR_I_PolyphaseFIR_1/inner_floop.mem_14_[13]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.177</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.177</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>I_out_block.med[2]:CLK</cell>
 <cell>I_out[2]</cell>
 <cell>1.860</cell>
 <cell></cell>
 <cell>4.014</cell>
 <cell></cell>
 <cell>4.014</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>I_out_block.med[3]:CLK</cell>
 <cell>I_out[3]</cell>
 <cell>1.917</cell>
 <cell></cell>
 <cell>4.079</cell>
 <cell></cell>
 <cell>4.079</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>I_out_block.med[12]:CLK</cell>
 <cell>I_out[12]</cell>
 <cell>1.951</cell>
 <cell></cell>
 <cell>4.080</cell>
 <cell></cell>
 <cell>4.080</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>I_out_block.med[0]:CLK</cell>
 <cell>I_out[0]</cell>
 <cell>1.926</cell>
 <cell></cell>
 <cell>4.080</cell>
 <cell></cell>
 <cell>4.080</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>I_out_block.med[10]:CLK</cell>
 <cell>I_out[10]</cell>
 <cell>1.940</cell>
 <cell></cell>
 <cell>4.094</cell>
 <cell></cell>
 <cell>4.094</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: I_out_block.med[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: I_out[2]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.014</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.109</cell>
 <cell>1.109</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.176</cell>
 <cell>1.285</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.340</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB20:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.291</cell>
 <cell>1.631</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB20:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>1.828</cell>
 <cell>89</cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_block.med[2]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB20_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>2.154</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_block.med[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>2.208</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_obuf[2]/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>I_out_c[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.478</cell>
 <cell>2.686</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_obuf[2]/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.220</cell>
 <cell>2.906</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_obuf[2]/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>I_out_obuf[2]/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.906</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out_obuf[2]/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.108</cell>
 <cell>4.014</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out[2]</cell>
 <cell>net</cell>
 <cell>I_out[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.014</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.014</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>I_out[2]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>External Removal (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>GlobalReset</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[3]:ALn</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.154</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>GlobalReset</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[1]:ALn</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.154</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>GlobalReset</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[5]:ALn</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.154</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>GlobalReset</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[7]:ALn</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.154</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>GlobalReset</cell>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[11]:ALn</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.154</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[3]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.140</cell>
 <cell>1.140</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.185</cell>
 <cell>1.325</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.127</cell>
 <cell>1.452</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB16:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.281</cell>
 <cell>1.733</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB16:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.154</cell>
 <cell>1.887</cell>
 <cell>43</cell>
 <cell>f</cell>
</row>
<row>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[3]:ALn</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB16_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.359</cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.246</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.232</cell>
 <cell>N/C</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.061</cell>
 <cell>N/C</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB12:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.327</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB12:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>N/C</cell>
 <cell>43</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[3]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB12_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CFIR_Q_PolyphaseFIR_1_block.myCFIR_Q_PolyphaseFIR_1/inner_floop.mem_6_[3]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET clkDiv64 to clkDiv128</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[3]:CLK</cell>
 <cell>Downsample_RG3/outp_ds[3]:D</cell>
 <cell>0.303</cell>
 <cell>0.612</cell>
 <cell>2.775</cell>
 <cell>2.163</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[5]:CLK</cell>
 <cell>Downsample_RG3/outp_ds[5]:D</cell>
 <cell>0.517</cell>
 <cell>0.835</cell>
 <cell>3.013</cell>
 <cell>2.178</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[2]:CLK</cell>
 <cell>Downsample_RG3/outp_ds[2]:D</cell>
 <cell>0.516</cell>
 <cell>0.836</cell>
 <cell>3.018</cell>
 <cell>2.182</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[12]:CLK</cell>
 <cell>Downsample_RG3/outp_ds[12]:D</cell>
 <cell>0.488</cell>
 <cell>0.838</cell>
 <cell>2.991</cell>
 <cell>2.153</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[9]:CLK</cell>
 <cell>Downsample_RG3/outp_ds[9]:D</cell>
 <cell>0.522</cell>
 <cell>0.844</cell>
 <cell>3.018</cell>
 <cell>2.174</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[3]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Downsample_RG3/outp_ds[3]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.775</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.163</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.612</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.458</cell>
 <cell>1.458</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>1.640</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.695</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.280</cell>
 <cell>1.975</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.171</cell>
 <cell>46</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[3]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.301</cell>
 <cell>2.472</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[3]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>2.526</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Downsample_RG3/outp_ds[3]:D</cell>
 <cell>net</cell>
 <cell>N_16[3]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.249</cell>
 <cell>2.775</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.775</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv128</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv128</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.109</cell>
 <cell>1.109</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.176</cell>
 <cell>1.285</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.340</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB21:An</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.291</cell>
 <cell>1.631</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB21:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>1.827</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Downsample_RG3/outp_ds[3]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv128_ibuf_RNITBS9/U0_RGB1_RGB21_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.336</cell>
 <cell>2.163</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Downsample_RG3/outp_ds[3]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.163</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.163</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain clkDiv64</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>myCIC_I/myC3/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>0.366</cell>
 <cell>0.329</cell>
 <cell>2.866</cell>
 <cell>2.537</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>myCIC_Q/myC3/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>myCIC_Q/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>0.366</cell>
 <cell>0.330</cell>
 <cell>2.847</cell>
 <cell>2.517</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>DownsampleCounterclkDiv64Drate2[0]:CLK</cell>
 <cell>Downsample_RG2_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[13]:EN</cell>
 <cell>0.367</cell>
 <cell>0.347</cell>
 <cell>2.846</cell>
 <cell>2.499</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>myCIC_Q/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>myCIC_Q/myC5/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>0.390</cell>
 <cell>0.362</cell>
 <cell>2.871</cell>
 <cell>2.509</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>myCIC_I/myC5/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>0.429</cell>
 <cell>0.400</cell>
 <cell>2.929</cell>
 <cell>2.529</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: myCIC_I/myC3/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.329</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.458</cell>
 <cell>1.458</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>1.640</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.695</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.280</cell>
 <cell>1.975</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.171</cell>
 <cell>50</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC3/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.329</cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC3/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>2.554</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC3/tmpOutPre_axb_0_i_0:B</cell>
 <cell>net</cell>
 <cell>myCIC_I/outBuf0_1[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>2.770</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC3/tmpOutPre_axb_0_i_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.047</cell>
 <cell>2.817</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>net</cell>
 <cell>myCIC_I/tmpOutPre_3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.049</cell>
 <cell>2.866</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.866</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.458</cell>
 <cell>1.458</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>1.640</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.695</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.280</cell>
 <cell>1.975</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.171</cell>
 <cell>50</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB11_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[0]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>External Removal (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>GlobalReset</cell>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[40]:ALn</cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.538</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>GlobalReset</cell>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[37]:ALn</cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.538</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>GlobalReset</cell>
 <cell>myCIC_Q/myC5/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[10]:ALn</cell>
 <cell>2.224</cell>
 <cell></cell>
 <cell>2.224</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.537</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>GlobalReset</cell>
 <cell>myCIC_Q/Delay_RG1_block/GenBlock.genblk1.theDelay/outreg[4]:ALn</cell>
 <cell>2.225</cell>
 <cell></cell>
 <cell>2.225</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.537</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>GlobalReset</cell>
 <cell>myCIC_I/myC5/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[22]:ALn</cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.537</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[40]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>GlobalReset</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.140</cell>
 <cell>1.140</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.185</cell>
 <cell>1.325</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.127</cell>
 <cell>1.452</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB37:An</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>1.731</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB37:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.153</cell>
 <cell>1.884</cell>
 <cell>59</cell>
 <cell>f</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[40]:ALn</cell>
 <cell>net</cell>
 <cell>GlobalReset_ibuf_RNIP2EB/U0_RGB1_RGB37_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.361</cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.620</cell>
 <cell>N/C</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.203</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.061</cell>
 <cell>N/C</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.311</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.218</cell>
 <cell>N/C</cell>
 <cell>46</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[40]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB10_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_I/myC4/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[40]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET clk to clkDiv64</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[7]:CLK</cell>
 <cell>myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[7]:D</cell>
 <cell>0.401</cell>
 <cell>0.013</cell>
 <cell>2.513</cell>
 <cell>2.500</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>myCIC_I/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[15]:CLK</cell>
 <cell>myCIC_I/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[15]:D</cell>
 <cell>0.489</cell>
 <cell>0.067</cell>
 <cell>2.600</cell>
 <cell>2.533</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>myCIC_I/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[19]:CLK</cell>
 <cell>myCIC_I/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[19]:D</cell>
 <cell>0.490</cell>
 <cell>0.068</cell>
 <cell>2.601</cell>
 <cell>2.533</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[36]:CLK</cell>
 <cell>myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[36]:D</cell>
 <cell>0.490</cell>
 <cell>0.069</cell>
 <cell>2.579</cell>
 <cell>2.510</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>myCIC_I/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[25]:CLK</cell>
 <cell>myCIC_I/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[25]:D</cell>
 <cell>0.494</cell>
 <cell>0.072</cell>
 <cell>2.605</cell>
 <cell>2.533</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[7]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[7]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.513</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.013</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clk</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clk</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.104</cell>
 <cell>1.104</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>1.270</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.325</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.261</cell>
 <cell>1.586</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>1.782</cell>
 <cell>57</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[7]:CLK</cell>
 <cell>net</cell>
 <cell>clk_ibuf_RNIVTI2/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.330</cell>
 <cell>2.112</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_Q/Rate_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[7]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>2.166</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[7]:D</cell>
 <cell>net</cell>
 <cell>myCIC_Q/N_8[7]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.347</cell>
 <cell>2.513</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.513</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>clkDiv64</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>clkDiv64</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.458</cell>
 <cell>1.458</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>1.640</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>1.695</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.261</cell>
 <cell>1.956</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.152</cell>
 <cell>41</cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[7]:CLK</cell>
 <cell>net</cell>
 <cell>clkDiv64_ibuf_RNICQH8/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>myCIC_Q/myC1/Delay_syn_block.myDelay_syn/Delay0_block/GenBlock.genblk1.theDelay/outreg[7]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
