# Microsemi Corp.
# Date: 2016-Mar-03 13:54:45
# This file was generated based on the following SDC source files:
#   E:/Libero_11p7_updates/LL_11p6/m2s_tu0312_liberov11p6_df/Solutions/Verilog/DDC_top/constraint/ddc.sdc
#

create_clock -name {clk} -period 25 -waveform {0 12.5 } [ get_ports { clk } ]
create_clock -name {clkDiv64} -period 1600 -waveform {0 800 } [ get_ports { clkDiv64 } ]
create_clock -name {clkDiv128} -period 3200 -waveform {0 1600 } [ get_ports { clkDiv128 } ]
