// ********************************************************************
//
// Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

// This code is for use only with Microsemi devices and is prohibited
// for use with all other devices and technologies.

// VERILOG created by Synphony Model Compiler J-2015.03M, Build 005R, Mar 30 2015
// Date written:             Wed Oct 28 11:33:51 2015

// ********************************************************************

// Generated from C:\demo\ddc.mdl Version 1.3028 Last modified date Mon Oct 19 15:12:29 2015
`include "define.h"
module CFIR_I_PolyphaseFIR_0( clk, gReset, gEnable, inp, outp);
parameter inpBitWidth = 14;
parameter inpFrac = 13;
parameter coefBitWidth = 9;
parameter coefFrac = 8;
parameter dpBitWidth = 15;
parameter dpFrac = 13;
parameter outBitWidth = 15;
parameter tapLen = 25;
parameter extraLatency = 0;
input  clk;
input gReset;
input gEnable;
input [inpBitWidth-1:0] inp;
output [outBitWidth-1:0] outp;


wire signed  [coefBitWidth-1:0] CoefArr [0:9] ;
generate
begin: CoefArrGen
  assign CoefArr[0] = 9'b111111111;
  assign CoefArr[1] = 9'b000000001;
  assign CoefArr[2] = 9'b000000100;
  assign CoefArr[3] = 9'b111111110;
  assign CoefArr[4] = 9'b000000101;
  assign CoefArr[5] = 9'b111110111;
  assign CoefArr[6] = 9'b000001100;
  assign CoefArr[7] = 9'b111110001;
  assign CoefArr[8] = 9'b000010001;
  assign CoefArr[9] = 9'b001101110;
end
endgenerate
parameter uniTap = 10;
wire [31:0] CoefIndTable [0:tapLen-1];
generate
begin:CoefIndTableGen
  assign CoefIndTable[0] = 0;
  assign CoefIndTable[1] = 1;
  assign CoefIndTable[2] = 2;
  assign CoefIndTable[3] = 3;
  assign CoefIndTable[4] = 2;
  assign CoefIndTable[5] = 10;
  assign CoefIndTable[6] = 3;
  assign CoefIndTable[7] = 4;
  assign CoefIndTable[8] = 5;
  assign CoefIndTable[9] = 6;
  assign CoefIndTable[10] = 7;
  assign CoefIndTable[11] = 8;
  assign CoefIndTable[12] = 9;
  assign CoefIndTable[13] = 8;
  assign CoefIndTable[14] = 7;
  assign CoefIndTable[15] = 6;
  assign CoefIndTable[16] = 5;
  assign CoefIndTable[17] = 4;
  assign CoefIndTable[18] = 3;
  assign CoefIndTable[19] = 10;
  assign CoefIndTable[20] = 2;
  assign CoefIndTable[21] = 3;
  assign CoefIndTable[22] = 2;
  assign CoefIndTable[23] = 1;
  assign CoefIndTable[24] = 0;
end
endgenerate
wire signed [inpBitWidth-1:0] multInp;
wire signed [dpBitWidth-1:0] multOuts [0:uniTap+1-1];
wire signed [dpBitWidth-1:0] multBufs1 [0:uniTap-1];
wire signed [coefBitWidth + inpBitWidth-1:0] multBufs1pre [0:uniTap-1];
wire  rstBuf;
wire  enBuf;
reg signed [dpBitWidth-1:0] mem [0:1*(tapLen-1)-1];

    assign multInp = inp;
generate
  genvar i1;
for(i1=0; i1<=uniTap-1; i1=i1+1)
begin: multOuts_gen
    assign multOuts[i1] = multBufs1[i1];
end
endgenerate
  assign multOuts[uniTap] = 0;
  assign rstBuf = 0;
  assign enBuf = 1;
    assign outp = multOuts[0] + mem[0];
  generate
      genvar i2;
    for(i2=0; i2<=uniTap-1; i2=i2+1)
    begin: floop
      assign multBufs1pre[i2] = multInp * CoefArr[i2];
        assign multBufs1[i2] = multBufs1pre[i2] >>> (coefFrac+inpFrac-dpFrac) ;
    end
  endgenerate

  generate
      integer i3, j;
  begin: inner_floop
  always @(posedge clk or posedge gReset)
  begin: FIR_proc
    integer i;
    if(gReset==1) 
    begin
         for(i3 = 0; i3 <= 1*(tapLen-1)-1; i3=i3+1) 
           begin
             mem[i3] <= 0;
           end

       end // reset
       else if(gEnable==1) begin
        if( rstBuf==1 ) begin
          for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
            begin
              mem[(i3+1)*1-1] <= 0;
            end

        end // reset
        else if( enBuf==1 ) begin
            mem[0] <= mem[1] + ((multOuts[CoefIndTable[1]]));
            mem[1] <= mem[2] + ((multOuts[CoefIndTable[2]]));
            mem[2] <= mem[3] + ((multOuts[CoefIndTable[3]]));
            mem[3] <= mem[4] + ((multOuts[CoefIndTable[4]]) >>> 1);
            mem[4] <= mem[5] + ((multOuts[CoefIndTable[5]]));
            mem[5] <= mem[6] + ((multOuts[CoefIndTable[6]]));
            mem[6] <= mem[7] + ((multOuts[CoefIndTable[7]]));
            mem[7] <= mem[8] + ((multOuts[CoefIndTable[8]]));
            mem[8] <= mem[9] + ((multOuts[CoefIndTable[9]]));
            mem[9] <= mem[10] + ((multOuts[CoefIndTable[10]]));
            mem[10] <= mem[11] + ((multOuts[CoefIndTable[11]]));
            mem[11] <= mem[12] + ((multOuts[CoefIndTable[12]]));
            mem[12] <= mem[13] + ((multOuts[CoefIndTable[13]]));
            mem[13] <= mem[14] + ((multOuts[CoefIndTable[14]]));
            mem[14] <= mem[15] + ((multOuts[CoefIndTable[15]]));
            mem[15] <= mem[16] + ((multOuts[CoefIndTable[16]]));
            mem[16] <= mem[17] + ((multOuts[CoefIndTable[17]]));
            mem[17] <= mem[18] + ((multOuts[CoefIndTable[18]]));
            mem[18] <= mem[19] + ((multOuts[CoefIndTable[19]]));
            mem[19] <= mem[20] + ((multOuts[CoefIndTable[20]]) >>> 1);
            mem[20] <= mem[21] + ((multOuts[CoefIndTable[21]]));
            mem[21] <= mem[22] + ((multOuts[CoefIndTable[22]]));
            mem[22] <= mem[23] + ((multOuts[CoefIndTable[23]]));
            mem[23] <=  ((multOuts[CoefIndTable[24]]));
        end
        else begin
          for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
            begin
              mem[(i3+1)*1-1] <= mem[i3*1];
            end

        end
        for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
        begin
          for(j = 0; j <= 1-2; j=j+1) 
          begin
            mem[i3*1+j] <= mem[i3*1+j+1];
          end
        end

       end // gEnable
     end // always
   end // inner_floop
   endgenerate
endmodule

//-----------------------------------------

module CFIR_I_PolyphaseFIR_1( clk, gReset, gEnable, inp, outp);
parameter inpBitWidth = 14;
parameter inpFrac = 13;
parameter coefBitWidth = 9;
parameter coefFrac = 8;
parameter dpBitWidth = 15;
parameter dpFrac = 13;
parameter outBitWidth = 15;
parameter tapLen = 24;
parameter extraLatency = 0;
input  clk;
input gReset;
input gEnable;
input [inpBitWidth-1:0] inp;
output [outBitWidth-1:0] outp;


wire signed  [coefBitWidth-1:0] CoefArr [0:9] ;
generate
begin: CoefArrGen
  assign CoefArr[0] = 9'b111111111;
  assign CoefArr[1] = 9'b000000011;
  assign CoefArr[2] = 9'b000000010;
  assign CoefArr[3] = 9'b111111110;
  assign CoefArr[4] = 9'b000000100;
  assign CoefArr[5] = 9'b111111100;
  assign CoefArr[6] = 9'b111111101;
  assign CoefArr[7] = 9'b000000111;
  assign CoefArr[8] = 9'b111101011;
  assign CoefArr[9] = 9'b001001111;
end
endgenerate
parameter uniTap = 10;
wire [31:0] CoefIndTable [0:tapLen-1];
generate
begin:CoefIndTableGen
  assign CoefIndTable[0] = 0;
  assign CoefIndTable[1] = 1;
  assign CoefIndTable[2] = 2;
  assign CoefIndTable[3] = 3;
  assign CoefIndTable[4] = 4;
  assign CoefIndTable[5] = 5;
  assign CoefIndTable[6] = 4;
  assign CoefIndTable[7] = 6;
  assign CoefIndTable[8] = 10;
  assign CoefIndTable[9] = 7;
  assign CoefIndTable[10] = 8;
  assign CoefIndTable[11] = 9;
  assign CoefIndTable[12] = 9;
  assign CoefIndTable[13] = 8;
  assign CoefIndTable[14] = 7;
  assign CoefIndTable[15] = 10;
  assign CoefIndTable[16] = 6;
  assign CoefIndTable[17] = 4;
  assign CoefIndTable[18] = 5;
  assign CoefIndTable[19] = 4;
  assign CoefIndTable[20] = 3;
  assign CoefIndTable[21] = 2;
  assign CoefIndTable[22] = 1;
  assign CoefIndTable[23] = 0;
end
endgenerate
wire signed [inpBitWidth-1:0] multInp;
wire signed [dpBitWidth-1:0] multOuts [0:uniTap+1-1];
wire signed [dpBitWidth-1:0] multBufs1 [0:uniTap-1];
wire signed [coefBitWidth + inpBitWidth-1:0] multBufs1pre [0:uniTap-1];
wire  rstBuf;
wire  enBuf;
reg signed [dpBitWidth-1:0] mem [0:1*(tapLen-1)-1];

    assign multInp = inp;
generate
  genvar i1;
for(i1=0; i1<=uniTap-1; i1=i1+1)
begin: multOuts_gen
    assign multOuts[i1] = multBufs1[i1];
end
endgenerate
  assign multOuts[uniTap] = 0;
  assign rstBuf = 0;
  assign enBuf = 1;
    assign outp = multOuts[0] + mem[0];
  generate
      genvar i2;
    for(i2=0; i2<=uniTap-1; i2=i2+1)
    begin: floop
      assign multBufs1pre[i2] = multInp * CoefArr[i2];
        assign multBufs1[i2] = multBufs1pre[i2] >>> (coefFrac+inpFrac-dpFrac) ;
    end
  endgenerate

  generate
      integer i3, j;
  begin: inner_floop
  always @(posedge clk or posedge gReset)
  begin: FIR_proc
    integer i;
    if(gReset==1) 
    begin
         for(i3 = 0; i3 <= 1*(tapLen-1)-1; i3=i3+1) 
           begin
             mem[i3] <= 0;
           end

       end // reset
       else if(gEnable==1) begin
        if( rstBuf==1 ) begin
          for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
            begin
              mem[(i3+1)*1-1] <= 0;
            end

        end // reset
        else if( enBuf==1 ) begin
          for(i3 = 0; i3 <= tapLen-3; i3=i3+1) 
            begin
            mem[(i3+1)*1-1] <= mem[1*(i3+1)] + multOuts[CoefIndTable[i3+1]];
            end

          mem[1*(tapLen-1)-1] <= multOuts[CoefIndTable[tapLen-1]];
        end
        else begin
          for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
            begin
              mem[(i3+1)*1-1] <= mem[i3*1];
            end

        end
        for(i3 = 0; i3 <= tapLen-2; i3=i3+1) 
        begin
          for(j = 0; j <= 1-2; j=j+1) 
          begin
            mem[i3*1+j] <= mem[i3*1+j+1];
          end
        end

       end // gEnable
     end // always
   end // inner_floop
   endgenerate
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_515 ;
wire [16:0] N_y_in_0_516 ;
wire [14:0] N_z_in_0_517 ;
wire [16:0] N_x_out_1_518 ;
wire [16:0] N_y_out_1_519 ;
wire [14:0] N_z_out_1_520 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(21),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(21),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000000101;
assign N_3 = 15'b111111111111011;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_521 ;
wire [16:0] N_y_in_0_522 ;
wire [14:0] N_z_in_0_523 ;
wire [16:0] N_x_out_1_524 ;
wire [16:0] N_y_out_1_525 ;
wire [14:0] N_z_out_1_526 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(20),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(20),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000001010;
assign N_3 = 15'b111111111110110;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_527 ;
wire [16:0] N_y_in_0_528 ;
wire [14:0] N_z_in_0_529 ;
wire [16:0] N_x_out_1_530 ;
wire [16:0] N_y_out_1_531 ;
wire [14:0] N_z_out_1_532 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(19),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(19),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000010100;
assign N_3 = 15'b111111111101100;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_533 ;
wire [16:0] N_y_in_0_534 ;
wire [14:0] N_z_in_0_535 ;
wire [16:0] N_x_out_1_536 ;
wire [16:0] N_y_out_1_537 ;
wire [14:0] N_z_out_1_538 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(18),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(18),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000101001;
assign N_3 = 15'b111111111010111;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_539 ;
wire [16:0] N_y_in_0_540 ;
wire [14:0] N_z_in_0_541 ;
wire [16:0] N_x_out_1_542 ;
wire [16:0] N_y_out_1_543 ;
wire [14:0] N_z_out_1_544 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(17),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(17),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000001010001;
assign N_3 = 15'b111111110101111;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_545 ;
wire [16:0] N_y_in_0_546 ;
wire [14:0] N_z_in_0_547 ;
wire [16:0] N_x_out_1_548 ;
wire [16:0] N_y_out_1_549 ;
wire [14:0] N_z_out_1_550 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(16),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(16),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000010100010;
assign N_3 = 15'b111111101011110;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_551 ;
wire [16:0] N_y_in_0_552 ;
wire [14:0] N_z_in_0_553 ;
wire [16:0] N_x_out_1_554 ;
wire [16:0] N_y_out_1_555 ;
wire [14:0] N_z_out_1_556 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(15),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(15),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000100111111;
assign N_3 = 15'b111111011000001;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_557 ;
wire [16:0] N_y_in_0_558 ;
wire [14:0] N_z_in_0_559 ;
wire [16:0] N_x_out_1_560 ;
wire [16:0] N_y_out_1_561 ;
wire [14:0] N_z_out_1_562 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(14),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(14),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000001001011101;
assign N_3 = 15'b111110110100011;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_563 ;
wire [16:0] N_y_in_0_564 ;
wire [14:0] N_z_in_0_565 ;
wire [16:0] N_x_out_1_566 ;
wire [16:0] N_y_out_1_567 ;
wire [14:0] N_z_out_1_568 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(24),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(24),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    assign N_20 = N_9;
    assign N_21 = N_10;
    assign N_22 = N_18;
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000000001;
assign N_3 = 15'b111111111111111;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_569 ;
wire [16:0] N_y_in_0_570 ;
wire [14:0] N_z_in_0_571 ;
wire [16:0] N_x_out_1_572 ;
wire [16:0] N_y_out_1_573 ;
wire [14:0] N_z_out_1_574 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(23),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(23),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    assign N_20 = N_9;
    assign N_21 = N_10;
    assign N_22 = N_18;
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000000001;
assign N_3 = 15'b111111111111111;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_575 ;
wire [16:0] N_y_in_0_576 ;
wire [14:0] N_z_in_0_577 ;
wire [16:0] N_x_out_1_578 ;
wire [16:0] N_y_out_1_579 ;
wire [14:0] N_z_out_1_580 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(22),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(22),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_4 = 15'b000000000000011;
assign N_3 = 15'b111111111111101;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [14:0] z_out, // sfix15_En13
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in // sfix15_En13
);
wire [14:0] N_6 ;
wire [14:0] N_11 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_18 ;
wire [0:0] N_15 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [14:0] N_4 ;
wire [14:0] N_3 ;
wire [14:0] N_22 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [14:0] N_z_in_0_581 ;
wire [16:0] N_x_out_1_582 ;
wire [16:0] N_y_out_1_583 ;
wire [14:0] N_z_out_1_584 ;
wire GlobalResetSel;
assign z_out = N_22;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  generate
  begin: Add2_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_6_0;
    wire signed [15:0] tmp_N_11_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_6_0 = ($signed(N_6) << 0);
    assign tmp_N_11_1 = ($signed(N_11) << 0);
    assign  tmpOutPre =   tmp_N_6_0 - tmp_N_11_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_18) );
  end // Add2_block
  endgenerate
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_9), .outp(N_20) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_10), .outp(N_21) );
    synDelayWithEnable #( .bitwidth(15), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_18), .outp(N_22) );
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
  assign N_11 = (N_15 == 0) ? N_4 : N_3; // mux block
assign N_9 = 17'b00001001101101111;
assign N_27 = 17'b11110110010010001;
assign N_26 = 17'b00001001101101111;
assign N_4 = 15'b000010000000000;
assign N_3 = 15'b111110000000000;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in, // sfix15_En13
  input [16:0] y_in, // sfix17_En13
  input [16:0] x_in // sfix17_En13
);
wire [16:0] N_5 ;
wire [16:0] N_28 ;
wire [16:0] N_8 ;
wire [16:0] N_25 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [14:0] N_6 ;
wire [0:0] N_15 ;
wire [16:0] N_29 ;
wire [16:0] N_30 ;
wire [16:0] N_26 ;
wire [16:0] N_27 ;
wire [16:0] N_21 ;
wire [16:0] N_20 ;
wire [16:0] N_x_in_0_585 ;
wire [16:0] N_y_in_0_586 ;
wire [14:0] N_z_in_0_587 ;
wire [16:0] N_x_out_1_588 ;
wire [16:0] N_y_out_1_589 ;
wire GlobalResetSel;
assign y_out = N_21;
assign x_out = N_20;
  assign N_6 = z_in;
  assign N_8 = y_in;
  assign N_5 = x_in;
  generate
  begin: Add1_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 - tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_29) );
  end // Add1_block
  endgenerate
  generate
  begin: Add3_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_26) );
  end // Add3_block
  endgenerate
  generate
  begin: Add4_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_8_0;
    wire signed [17:0] tmp_N_25_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_8_0 = ($signed(N_8) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 0);
    assign  tmpOutPre =   tmp_N_8_0 - tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_27) );
  end // Add4_block
  endgenerate
  generate
  begin: Add5_block
    wire enab;
    wire [17:0] tmpOut;
    wire signed [17:0] tmp_N_5_0;
    wire signed [17:0] tmp_N_28_1;
    wire [17:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($signed(N_5) << 0);
    assign tmp_N_28_1 = ($signed(N_28) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_28_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(18), .out_width(17), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_30) );
  end // Add5_block
  endgenerate
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(25),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert1 (
      .inp(N_8),
      .outp(N_28)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(17),
      .datatype("signed"),
      .preshift(0),

      .infrac(25),
      .outfrac(13),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert2 (
      .inp(N_5),
      .outp(N_25)
   );
    assign N_20 = N_9;
    assign N_21 = N_10;
  //start Extract1
    assign N_15[0] = N_6[14];
  //end Extract1
  assign N_9 = (N_15 == 0) ? N_29 : N_30; // mux block
  assign N_10 = (N_15 == 0) ? N_26 : N_27; // mux block
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [14:0] z_in // sfix15_En13
);
wire [16:0] N_69 ;
wire [16:0] N_68 ;
wire [16:0] N_43 ;
wire [16:0] N_44 ;
wire [14:0] N_45 ;
wire [16:0] N_38 ;
wire [16:0] N_39 ;
wire [14:0] N_40 ;
wire [16:0] N_33 ;
wire [16:0] N_34 ;
wire [14:0] N_35 ;
wire [16:0] N_28 ;
wire [16:0] N_29 ;
wire [14:0] N_30 ;
wire [16:0] N_23 ;
wire [16:0] N_24 ;
wire [14:0] N_25 ;
wire [16:0] N_18 ;
wire [16:0] N_19 ;
wire [14:0] N_20 ;
wire [16:0] N_13 ;
wire [16:0] N_14 ;
wire [14:0] N_15 ;
wire [16:0] N_8 ;
wire [16:0] N_9 ;
wire [14:0] N_10 ;
wire [16:0] N_58 ;
wire [16:0] N_59 ;
wire [14:0] N_60 ;
wire [16:0] N_53 ;
wire [16:0] N_54 ;
wire [14:0] N_55 ;
wire [16:0] N_48 ;
wire [16:0] N_49 ;
wire [14:0] N_50 ;
wire [14:0] N_5 ;
wire [16:0] N_63 ;
wire [16:0] N_64 ;
wire [14:0] N_65 ;
wire [14:0] N_z_in_0_590 ;
wire [16:0] N_x_out_1_591 ;
wire [16:0] N_y_out_1_592 ;
wire GlobalResetSel;
assign y_out = N_69;
assign x_out = N_68;
  assign N_5 = z_in;
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg9  myCORDIC_stg9 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_43),
      .y_in(N_44),
      .z_in(N_45),
      .x_out(N_48) ,
      .y_out(N_49) ,
      .z_out(N_50)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg8  myCORDIC_stg8 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_38),
      .y_in(N_39),
      .z_in(N_40),
      .x_out(N_43) ,
      .y_out(N_44) ,
      .z_out(N_45)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg7  myCORDIC_stg7 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_33),
      .y_in(N_34),
      .z_in(N_35),
      .x_out(N_38) ,
      .y_out(N_39) ,
      .z_out(N_40)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg6  myCORDIC_stg6 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_28),
      .y_in(N_29),
      .z_in(N_30),
      .x_out(N_33) ,
      .y_out(N_34) ,
      .z_out(N_35)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg5  myCORDIC_stg5 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_23),
      .y_in(N_24),
      .z_in(N_25),
      .x_out(N_28) ,
      .y_out(N_29) ,
      .z_out(N_30)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg4  myCORDIC_stg4 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_18),
      .y_in(N_19),
      .z_in(N_20),
      .x_out(N_23) ,
      .y_out(N_24) ,
      .z_out(N_25)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg3  myCORDIC_stg3 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_13),
      .y_in(N_14),
      .z_in(N_15),
      .x_out(N_18) ,
      .y_out(N_19) ,
      .z_out(N_20)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg2  myCORDIC_stg2 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_8),
      .y_in(N_9),
      .z_in(N_10),
      .x_out(N_13) ,
      .y_out(N_14) ,
      .z_out(N_15)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg12  myCORDIC_stg12 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_58),
      .y_in(N_59),
      .z_in(N_60),
      .x_out(N_63) ,
      .y_out(N_64) ,
      .z_out(N_65)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg11  myCORDIC_stg11 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_53),
      .y_in(N_54),
      .z_in(N_55),
      .x_out(N_58) ,
      .y_out(N_59) ,
      .z_out(N_60)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg10  myCORDIC_stg10 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_48),
      .y_in(N_49),
      .z_in(N_50),
      .x_out(N_53) ,
      .y_out(N_54) ,
      .z_out(N_55)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg1  myCORDIC_stg1 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .z_in(N_5),
      .x_out(N_8) ,
      .y_out(N_9) ,
      .z_out(N_10)    );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1_CORDIC_stg13  myCORDIC_stg13 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x_in(N_63),
      .y_in(N_64),
      .z_in(N_65),
      .x_out(N_68) ,
      .y_out(N_69)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos_CORDIC2_stage (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [16:0] y_out, // sfix17_En13
  output [16:0] x_out, // sfix17_En13
  input [13:0] z_in // sfix14_En13
);
wire [12:0] N_15 ;
wire [2:0] N_25 ;
wire [13:0] N_3 ;
wire [17:0] N_23 ;
wire [17:0] N_24 ;
wire [0:0] N_6 ;
wire [0:0] N_20 ;
wire [16:0] N_7 ;
wire [17:0] N_27 ;
wire [16:0] N_8 ;
wire [17:0] N_28 ;
wire [0:0] N_21 ;
wire [2:0] N_12 ;
wire [2:0] N_13 ;
wire [14:0] N_5 ;
wire [16:0] N_19 ;
wire [16:0] N_18 ;
wire [0:0] N_22 ;
wire [0:0] N_GlobalEnable1_SubSystem_Convert_AutoGen396_1_374 ;
wire [14:0] N_26 ;
wire [0:0] N_GlobalEnable1_0_593 ;
wire [13:0] N_z_in_0_594 ;
wire [16:0] N_x_out_1_595 ;
wire [16:0] N_y_out_1_596 ;
wire GlobalResetSel;
assign y_out = N_19;
assign x_out = N_18;
  assign N_3 = z_in;
  assign N_GlobalEnable1_SubSystem_Convert_AutoGen396_1_374 = GlobalEnable1;
  generate
  begin: Add1_block
    wire enab;
    wire [14:0] tmpOut;
    wire signed [14:0] tmp_N_15_0;
    wire signed [14:0] tmp_N_25_1;
    wire [14:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_15_0 = ($signed(N_15) << 0);
    assign tmp_N_25_1 = ($signed(N_25) << 11);
    assign  tmpOutPre =   tmp_N_15_0 + tmp_N_25_1;
    assign tmpOut = tmpOutPre;
    assign N_5 = $signed(tmpOut) << 0;
  end // Add1_block
  endgenerate
  synBusAdapter #(
      .inp_width(14),
      .out_width(13),
      .datatype("signed"),
      .preshift(0)
    ) Convert (
      .inp(N_3),
      .outp(N_15)
   );
  synBusAdapter #(
      .inp_width(18),
      .out_width(17),
      .datatype("signed"),
      .preshift(0)
    ) Convert3 (
      .inp(N_23),
      .outp(N_18)
   );
  synBusAdapter #(
      .inp_width(18),
      .out_width(17),
      .datatype("signed"),
      .preshift(0)
    ) Convert4 (
      .inp(N_24),
      .outp(N_19)
   );
    synDelayWithEnable #( .bitwidth(1), .delaylength(10) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_6), .outp(N_20) );
  //start Extract2
    assign N_21[0] = N_15[12];
  //end Extract2
  //start Extract3
    assign N_22[0] = N_15[11];
  //end Extract3
  generate
  begin: Mux2_block
    wire [17:0] med  [1:0];
    reg [17:0] tmpOut;
    assign med[0] = $signed(N_7) ;
    assign med[1] = $signed(N_27) ;

    always@(*)
    begin
      if(N_20[0:0] >= 2)
        tmpOut <= med[0];
      else
        tmpOut <= med[N_20[0:0]];
    end

    assign N_23 = tmpOut;
  end // Mux2_Block
  endgenerate
  generate
  begin: Mux3_block
    wire [17:0] med  [1:0];
    reg [17:0] tmpOut;
    assign med[0] = $signed(N_8) ;
    assign med[1] = $signed(N_28) ;

    always@(*)
    begin
      if(N_20[0:0] >= 2)
        tmpOut <= med[0];
      else
        tmpOut <= med[N_20[0:0]];
    end

    assign N_24 = tmpOut;
  end // Mux3_Block
  endgenerate
  assign N_25 = (N_21 == 0) ? N_12 : N_13; // mux block
  generate
  begin: Mux5_block
    wire [14:0] med  [1:0];
    reg [14:0] tmpOut;
    assign med[0] = $signed(N_15) ;
    assign med[1] = $signed(N_5) ;

    always@(*)
    begin
      if(N_6[0:0] >= 2)
        tmpOut <= med[0];
      else
        tmpOut <= med[N_6[0:0]];
    end

    assign N_26 = tmpOut;
  end // Mux5_Block
  endgenerate
  generate
  begin: Negate1_block
    wire signed [17:0] med ;
    wire signed [17:0] medo;
    wire [17:0] tmpOut;
    assign med = $signed(N_7);
    assign medo = $signed(tmpOut) ;
    assign N_27 = medo[17:0];
    synNegate #(
      .bitwidth(18)
    ) Negate1 (
      .inp(med),
      .outp(tmpOut)
    );
  end // Negate1_block;
  endgenerate
  generate
  begin: Negate2_block
    wire signed [17:0] med ;
    wire signed [17:0] medo;
    wire [17:0] tmpOut;
    assign med = $signed(N_8);
    assign medo = $signed(tmpOut) ;
    assign N_28 = medo[17:0];
    synNegate #(
      .bitwidth(18)
    ) Negate2 (
      .inp(med),
      .outp(tmpOut)
    );
  end // Negate2_block;
  endgenerate
  generate
  begin: Binary_Logic_block
    assign N_6 = (N_21 ^ N_22);
  end // Binary_Logic_block;
  endgenerate
assign N_13 = 3'b010;
assign N_12 = 3'b110;
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage_CORDIC_onequadrant1  myCORDIC_onequadrant1 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .z_in(N_26),
      .x_out(N_7) ,
      .y_out(N_8)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos_CORDIC_SinCos (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [16:0] cos, // sfix17_En13
  output [16:0] sin, // sfix17_En13
  input [11:0] theta // ufix12_En12
);
wire [11:0] N_1 ;
wire [12:0] N_2 ;
wire [16:0] N_9 ;
wire [16:0] N_10 ;
wire [0:0] N_GlobalEnable1_SubSystem_Convert_AutoGen395_1_373 ;
wire [13:0] N_3 ;
wire [0:0] N_GlobalEnable1_0_597 ;
wire [11:0] N_theta_0_598 ;
wire [16:0] N_sin_1_599 ;
wire [16:0] N_cos_1_600 ;
wire GlobalResetSel;
assign cos = N_9;
assign sin = N_10;
  assign N_1 = theta;
  assign N_GlobalEnable1_SubSystem_Convert_AutoGen395_1_373 = GlobalEnable1;
  synBusAdapter #(
      .inp_width(12),
      .out_width(13),
      .datatype("unsign"),
      .preshift(0)
    ) Convert (
      .inp(N_1),
      .outp(N_2)
   );
  synBusAdapter #(
      .inp_width(13),
      .out_width(14),
      .datatype("signed"),
      .preshift(-1)
    ) Convert_z (
      .inp(N_2),
      .outp(N_3)
   );
    DDS_SinCos_CORDIC_SinCos_CORDIC2_stage  myCORDIC2_stage (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .z_in(N_3),
      .x_out(N_9) ,
      .y_out(N_10)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS_SinCos (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [11:0] cos, // sfix12_En10
  output [11:0] sin, // sfix12_En10
  input [31:0] phasein // ufix32_En32
);
wire [16:0] N_6 ;
wire [16:0] N_7 ;
wire [31:0] N_1 ;
wire [16:0] N_4 ;
wire [16:0] N_5 ;
wire [11:0] N_2 ;
wire [11:0] N_9 ;
wire [11:0] N_8 ;
wire [0:0] N_GlobalEnable1_SubSystem_Convert_AutoGen394_1_372 ;
wire [11:0] N_3 ;
wire [0:0] N_GlobalEnable1_0_601 ;
wire [31:0] N_phasein_0_602 ;
wire [11:0] N_sin_1_603 ;
wire [11:0] N_cos_1_604 ;
wire GlobalResetSel;
assign cos = N_9;
assign sin = N_8;
  assign N_1 = phasein;
  assign N_GlobalEnable1_SubSystem_Convert_AutoGen394_1_372 = GlobalEnable1;
  synBusAdapter #(
      .inp_width(17),
      .out_width(12),
      .datatype("signed"),
      .preshift(0),

      .infrac(13),
      .outfrac(10),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert3 (
      .inp(N_6),
      .outp(N_8)
   );
  synBusAdapter #(
      .inp_width(17),
      .out_width(12),
      .datatype("signed"),
      .preshift(0),

      .infrac(13),
      .outfrac(10),
      .sat(0),
      .round(5),
      .saType("SS")
    ) Convert4 (
      .inp(N_7),
      .outp(N_9)
   );
  synBusAdapter #(
      .inp_width(32),
      .out_width(12),
      .datatype("unsign"),
      .preshift(20)
    ) Convert_p (
      .inp(N_1),
      .outp(N_2)
   );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay1_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_4), .outp(N_6) );
    synDelayWithEnable #( .bitwidth(17), .delaylength(1) ) Delay2_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_5), .outp(N_7) );
    synDelayWithEnable #( .bitwidth(12), .delaylength(1) ) Delay3_block ( .clk(clk), .en(GlobalEnable1), .grst(GlobalResetSel), .rst(1'b0), .inp(N_2), .outp(N_3) );
    DDS_SinCos_CORDIC_SinCos  myCORDIC_SinCos (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .theta(N_3),
      .sin(N_4) ,
      .cos(N_5)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module synDDS_PhaseGenerator_shrp2 (clk,grst,rst,en,d,q0);
parameter bitwidth=32;
parameter depth=1;
input clk;
input [bitwidth-1:0] d;
input grst;
input rst;
input en;
output [bitwidth-1:0] q0;
wire [bitwidth-1:0] qTemp0;
  assign q0 = qTemp0;
    synDelayWithEnable #( .bitwidth(bitwidth), .delaylength(1) ) Delay0_block ( .clk(clk), .en(en), .grst(grst), .rst(rst), .inp(d), .outp(qTemp0) );
endmodule

//----------------------------------------------------

module synDDS_PhaseGenerator_shrp1 (clk,grst,rst,en,d,q0);
parameter bitwidth=33;
parameter depth=1;
input clk;
input [bitwidth-1:0] d;
input grst;
input rst;
input en;
output [bitwidth-1:0] q0;
wire [bitwidth-1:0] qTemp0;
  assign q0 = qTemp0;
    synDelayWithEnable #( .bitwidth(bitwidth), .delaylength(1) ) Delay0_block ( .clk(clk), .en(en), .grst(grst), .rst(rst), .inp(d), .outp(qTemp0) );
endmodule

//----------------------------------------------------

module DDS_PhaseGenerator (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [31:0] pout, // ufix32_En32
  input [32:0] freq // sfix33_En32
);
wire [32:0] N_2 ;
wire [0:0] N_5 ;
wire [32:0] N_3 ;
wire [33:0] N_7 ;
wire [0:0] N_6 ;
wire [33:0] N_4 ;
wire [32:0] N_1 ;
wire [31:0] N_8 ;
wire [31:0] N_9 ;
wire [32:0] N_freq_0_605 ;
wire [31:0] N_pout_1_606 ;
wire GlobalResetSel;
assign pout = N_9;
  assign N_1 = freq;
  generate
  begin: Acc_p_block
  wire [32:0] accIn;
  wire [32:0] tmpOut;
  wire rst, en;
    assign en = (1'b1 && GlobalEnable1);
    assign rst = 1'b0 && GlobalEnable1;
  assign accIn = $signed(N_2) ;
  assign N_3 = tmpOut[32:0];
    synAccumulator #(
        .bitwidth(33),
        .datatype("signed"),
        .opr("incr")
      ) Acc_p (
        .clk(clk),
        .inp(accIn),
        .grst(GlobalResetSel),
        .rst(rst),
        .en(en),
        .outp(tmpOut)
      );
  end //Acc_p_block;
  endgenerate
  generate
  begin: Add_sf_block
    wire enab;
    wire [33:0] tmpOut;
    wire  [33:0] tmp_N_5_0;
    wire signed [33:0] tmp_N_3_1;
    wire [33:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_5_0 = ($unsigned(N_5) << 32);
    assign tmp_N_3_1 = ($signed(N_3) << 0);
    assign  tmpOutPre =   tmp_N_5_0 + tmp_N_3_1;
    assign tmpOut = tmpOutPre;
    assign N_4 = $signed(tmpOut) << 0;
  end // Add_sf_block
  endgenerate
  synBusAdapter #(
      .inp_width(34),
      .out_width(32),
      .datatype("signed"),
      .preshift(0)
    ) Convert_sf (
      .inp(N_7),
      .outp(N_8)
   );
  //start Extract_sf
    assign N_6[0] = N_3[32];
  //end Extract_sf
  generate
  begin: Mux_sf_block
    wire [33:0] med  [1:0];
    reg [33:0] tmpOut;
    assign med[0] = $signed(N_3) ;
    assign med[1] = $signed(N_4) ;

    always@(*)
    begin
      if(N_6[0:0] >= 2)
        tmpOut <= med[0];
      else
        tmpOut <= med[N_6[0:0]];
    end

    assign N_7 = tmpOut;
  end // Mux_sf_Block
  endgenerate
  generate
  begin: shrp1_block
    wire [32:0] outBuf0;
    wire rst, enab;
    assign rst = 0;
    assign enab = GlobalEnable1;
  synDDS_PhaseGenerator_shrp1 myshrp1(
      .clk(clk),
      .d(N_1),
        .grst(GlobalResetSel),
        .rst(rst),
        .en(enab),
      .q0(outBuf0)
    );
    assign N_2 = outBuf0;
  end //shrp1_block;
  endgenerate
  generate
  begin: shrp2_block
    wire [31:0] outBuf0;
    wire rst, enab;
    assign rst = 0;
    assign enab = GlobalEnable1;
  synDDS_PhaseGenerator_shrp2 myshrp2(
      .clk(clk),
      .d(N_8),
        .grst(GlobalResetSel),
        .rst(rst),
        .en(enab),
      .q0(outBuf0)
    );
    assign N_9 = outBuf0;
  end //shrp2_block;
  endgenerate
assign N_5 = 1'b1;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module synCIC_I_I1_Delay (clk,grst,rst,en,d,q0);
parameter bitwidth=44;
parameter depth=1;
input clk;
input [bitwidth-1:0] d;
input grst;
input rst;
input en;
output [bitwidth-1:0] q0;
wire [bitwidth-1:0] qTemp0;
  assign q0 = qTemp0;
    synDelayWithEnable #( .bitwidth(bitwidth), .delaylength(1) ) Delay0_block ( .clk(clk), .en(en), .grst(grst), .rst(rst), .inp(d), .outp(qTemp0) );
endmodule

//----------------------------------------------------

module CIC_I_I1 (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [43:0] y, // sfix44_En11
  input [43:0] x // sfix44_En11
);
wire [43:0] N_1 ;
wire [43:0] N_3 ;
wire [43:0] N_2 ;
wire [43:0] N_x_0_641 ;
wire [43:0] N_y_1_642 ;
wire GlobalResetSel;
assign y = N_2;
  assign N_1 = x;
  generate
  begin: Add_block
    wire enab;
    wire [44:0] tmpOut;
    wire signed [44:0] tmp_N_1_0;
    wire signed [44:0] tmp_N_3_1;
    wire [44:0] tmpOutPre;
    assign  enab= GlobalEnable1;
    assign tmp_N_1_0 = ($signed(N_1) << 0);
    assign tmp_N_3_1 = ($signed(N_3) << 0);
    assign  tmpOutPre =   tmp_N_1_0 + tmp_N_3_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(45), .out_width(44), .infrac(11), .outfrac(11), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_2) );
  end // Add_block
  endgenerate
  generate
  begin: Delay_syn_block
    wire [43:0] outBuf0;
    wire rst, enab;
    assign rst = 0;
    assign enab = GlobalEnable1;
  synCIC_I_I1_Delay myDelay_syn(
      .clk(clk),
      .d(N_2),
        .grst(GlobalResetSel),
        .rst(rst),
        .en(enab),
      .q0(outBuf0)
    );
    assign N_3 = outBuf0;
  end //Delay_syn_block;
  endgenerate
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module synCIC_I_C1_Delay (clk,grst,rst,en,d,q0);
parameter bitwidth=44;
parameter depth=1;
input clk;
input [bitwidth-1:0] d;
input grst;
input rst;
input en;
output [bitwidth-1:0] q0;
wire [bitwidth-1:0] qTemp0;
  assign q0 = qTemp0;
    synDelayWithEnable #( .bitwidth(bitwidth), .delaylength(1) ) Delay0_block ( .clk(clk), .en(en), .grst(grst), .rst(rst), .inp(d), .outp(qTemp0) );
endmodule

//----------------------------------------------------

module CIC_I_C1 (
  input clkDiv64,
  input GlobalEnable64,
  input GlobalReset,
  output [43:0] y, // sfix44_En11
  input [43:0] x // sfix44_En11
);
wire [43:0] N_1 ;
wire [43:0] N_2 ;
wire [43:0] N_3 ;
wire [43:0] N_x_0_651 ;
wire [43:0] N_y_1_652 ;
wire GlobalResetSel;
assign y = N_3;
  assign N_1 = x;
  generate
  begin: Delay_syn_block
    wire [43:0] outBuf0;
    wire rst, enab;
    assign rst = 0;
    assign enab = GlobalEnable64;
  synCIC_I_C1_Delay myDelay_syn(
      .clk(clkDiv64),
      .d(N_1),
        .grst(GlobalResetSel),
        .rst(rst),
        .en(enab),
      .q0(outBuf0)
    );
    assign N_2 = outBuf0;
  end //Delay_syn_block;
  endgenerate
  generate
  begin: Sub_block
    wire enab;
    wire [44:0] tmpOut;
    wire signed [44:0] tmp_N_1_0;
    wire signed [44:0] tmp_N_2_1;
    wire [44:0] tmpOutPre;
    assign  enab= GlobalEnable64;
    assign tmp_N_1_0 = ($signed(N_1) << 0);
    assign tmp_N_2_1 = ($signed(N_2) << 0);
    assign  tmpOutPre =   tmp_N_1_0 - tmp_N_2_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(45), .out_width(44), .infrac(11), .outfrac(11), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_3) );
  end // Sub_block
  endgenerate
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module DDS (
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [11:0] cos, // sfix12_En10
  output [11:0] sin, // sfix12_En10
  input [31:0] freq // ufix32_En32
);
wire [31:0] N_1 ;
wire [11:0] N_5 ;
wire [11:0] N_4 ;
wire [0:0] N_GlobalEnable1_SubSystem_Convert_AutoGen393_1_371 ;
wire [31:0] N_3 ;
wire [32:0] N_2 ;
wire [0:0] N_GlobalEnable1_0_607 ;
wire [31:0] N_freq_0_608 ;
wire [11:0] N_sin_1_609 ;
wire [11:0] N_cos_1_610 ;
wire GlobalResetSel;
assign cos = N_5;
assign sin = N_4;
  assign N_1 = freq;
  assign N_GlobalEnable1_SubSystem_Convert_AutoGen393_1_371 = GlobalEnable1;
  synBusAdapter #(
      .inp_width(32),
      .out_width(33),
      .datatype("unsign"),
      .preshift(0)
    ) Convert_freq (
      .inp(N_1),
      .outp(N_2)
   );
    DDS_SinCos  mySinCos (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .phasein(N_3),
      .sin(N_4) ,
      .cos(N_5)    );
    DDS_PhaseGenerator  myPhaseGenerator (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .freq(N_2),
      .pout(N_3)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

module CIC_I (
  input clkDiv64,
  input GlobalEnable64,
  input clk,
  input GlobalEnable1,
  input GlobalReset,
  output [13:0] y, // sfix14_En13
  input [13:0] x // sfix14_En11
);
wire [13:0] N_1 ;
wire [43:0] N_13 ;
wire [43:0] N_7 ;
wire [13:0] N_14_w1 ;
wire [13:0] N_14 ;
wire [43:0] N_6 ;
wire [43:0] N_5 ;
wire [43:0] N_4 ;
wire [43:0] N_3 ;
wire [43:0] N_2 ;
wire [43:0] N_12 ;
wire [43:0] N_11 ;
wire [43:0] N_10 ;
wire [43:0] N_9 ;
wire [43:0] N_8 /* synthesis syn_preserve=1 */ /* synthesis syn_keep=1 */;
wire [13:0] N_x_0_653 ;
wire [13:0] N_y_1_654 ;
wire GlobalResetSel;
reg [5:0] DownsampleCounterclkDrate64;
  always @(posedge clk or posedge GlobalResetSel)
  begin: dcntProc1_64_proc
    integer i;
    if(GlobalResetSel==1) 
        DownsampleCounterclkDrate64 <= 0;
      else if( GlobalEnable1==1)
        if(DownsampleCounterclkDrate64 == 63)
          DownsampleCounterclkDrate64 <= 0;
        else
          DownsampleCounterclkDrate64 <= DownsampleCounterclkDrate64 + 1;
    end //dcntProc1_64_proc

assign y = N_14_w1;
  assign N_1 = x;
  synBusAdapter #(
      .inp_width(14),
      .out_width(44),
      .datatype("signed"),
      .preshift(0)
    ) GainAdjust (
      .inp(N_1),
      .outp(N_2)
   );
  synBusAdapter #(
      .inp_width(44),
      .out_width(14),
      .datatype("signed"),
      .preshift(28)
    ) Normalize (
      .inp(N_13),
      .outp(N_14)
   );
  generate
  begin: Rate_block
    wire enDs;

    assign enDs = (DownsampleCounterclkDrate64 == 0) && GlobalEnable1;
    synDelayWithEnable #( .bitwidth(44), .delaylength(1) ) dsDelay_block ( .clk(clk), .en(enDs), .grst(GlobalResetSel), .rst(1'b0), .inp(N_7), .outp(N_8) );
  end //Rate_block;
  endgenerate
    synDelayWithEnable #( .bitwidth(14), .delaylength(1) ) Delay_RG1_block ( .clk(clkDiv64), .en(GlobalEnable64), .grst(GlobalResetSel), .rst(1'b0), .inp(N_14), .outp(N_14_w1) );
    CIC_I_I1  myI5 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_6),
      .y(N_7)    );
    CIC_I_I1  myI4 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_5),
      .y(N_6)    );
    CIC_I_I1  myI3 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_4),
      .y(N_5)    );
    CIC_I_I1  myI2 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_3),
      .y(N_4)    );
    CIC_I_I1  myI1 (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_2),
      .y(N_3)    );
    CIC_I_C1  myC5 (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .GlobalReset(GlobalResetSel),
      .x(N_12),
      .y(N_13)    );
    CIC_I_C1  myC4 (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .GlobalReset(GlobalResetSel),
      .x(N_11),
      .y(N_12)    );
    CIC_I_C1  myC3 (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .GlobalReset(GlobalResetSel),
      .x(N_10),
      .y(N_11)    );
    CIC_I_C1  myC2 (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .GlobalReset(GlobalResetSel),
      .x(N_9),
      .y(N_10)    );
    CIC_I_C1  myC1 (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .GlobalReset(GlobalResetSel),
      .x(N_8),
      .y(N_9)    );
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

//@
module ddc (
  input clk,
  input clkDiv128,
  input clkDiv64,
  input GlobalReset,
  output [13:0] Q_out, // sfix14_En13
  output [13:0] I_out, // sfix14_En13
  input [31:0] Freq, // ufix32_En32
  input [9:0] ADC // sfix10_En7
//@
);
//@

wire [9:0] N_2 ;
wire [13:0] N_5 ;
wire [31:0] N_6 ;
wire [13:0] N_7 ;
wire [13:0] N_11 ;
wire [13:0] N_12 ;
wire [13:0] N_Downsample_RG0_1_354 /* synthesis syn_preserve=1 */;
wire [13:0] N_Downsample_RG1_1_355 /* synthesis syn_preserve=1 */;
wire [14:0] N_CFIR_Q_Adder_2_356 ;
wire [14:0] N_CFIR_Q_PolyphaseFIR_0_1_357 ;
wire [14:0] N_CFIR_Q_PolyphaseFIR_1_1_358 ;
wire [13:0] N_Downsample_RG2_1_359 /* synthesis syn_preserve=1 */;
wire [13:0] N_Downsample_RG3_1_360 /* synthesis syn_preserve=1 */;
wire [14:0] N_CFIR_I_Adder_2_361 ;
wire [14:0] N_CFIR_I_PolyphaseFIR_0_1_362 ;
wire [14:0] N_CFIR_I_PolyphaseFIR_1_1_363 ;
wire [0:0] GlobalEnableSignal64 ;
wire [0:0] GlobalEnableSignal128 ;
wire [0:0] GlobalEnableSignal1 ;
wire [13:0] N_16 ;
wire [13:0] N_8 ;
wire [11:0] N_3 ;
wire [11:0] N_4 ;
wire GlobalResetSel;
reg [0:0] DownsampleCounterclkDiv64Drate2;
  wire GlobalEnable1;
  wire GlobalEnable128;
  wire GlobalEnable64;
  assign GlobalEnable1 = 1;
  assign GlobalEnable128 = 1;
  assign GlobalEnable64 = 1;
  always @(posedge clkDiv64 or posedge GlobalResetSel)
  begin: dcntProc64_2_proc
    integer i;
    if(GlobalResetSel==1) 
        DownsampleCounterclkDiv64Drate2 <= 0;
      else if( GlobalEnable64==1)
        if(DownsampleCounterclkDiv64Drate2 == 1)
          DownsampleCounterclkDiv64Drate2 <= 0;
        else
          DownsampleCounterclkDiv64Drate2 <= DownsampleCounterclkDiv64Drate2 + 1;
    end //dcntProc64_2_proc

    DDS  myDDS (
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .freq(N_6),
      .sin(N_3) ,
      .cos(N_4)    );
    CIC_I  myCIC_Q (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_5),
      .y(N_8)    );
    CIC_I  myCIC_I (
      .clkDiv64(clkDiv64),
      .GlobalEnable64(GlobalEnable64),
      .clk(clk),
      .GlobalEnable1(GlobalEnable1),
      .GlobalReset(GlobalResetSel),
      .x(N_7),
      .y(N_16)    );
  assign GlobalEnableSignal1 = GlobalEnable1;
  assign GlobalEnableSignal128 = GlobalEnable128;
  assign GlobalEnableSignal64 = GlobalEnable64;
  generate
  begin: CFIR_I_Adder_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_CFIR_I_PolyphaseFIR_0_1_362_0;
    wire signed [15:0] tmp_N_CFIR_I_PolyphaseFIR_1_1_363_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable128;
    assign tmp_N_CFIR_I_PolyphaseFIR_0_1_362_0 = ($signed(N_CFIR_I_PolyphaseFIR_0_1_362) << 0);
    assign tmp_N_CFIR_I_PolyphaseFIR_1_1_363_1 = ($signed(N_CFIR_I_PolyphaseFIR_1_1_363) << 0);
    assign  tmpOutPre =   tmp_N_CFIR_I_PolyphaseFIR_0_1_362_0 + tmp_N_CFIR_I_PolyphaseFIR_1_1_363_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_CFIR_I_Adder_2_361) );
  end // CFIR_I_Adder_block
  endgenerate
  synBusAdapter #(
      .inp_width(15),
      .out_width(14),
      .datatype("signed"),
      .preshift(0)
    ) Convert_AutoGen379 (
      .inp(N_CFIR_I_Adder_2_361),
      .outp(N_12)
   );
  generate
  begin: CFIR_I_PolyphaseFIR_1_block
    wire signed [14:0]  med;
    wire [13:0] tmpIn;
    wire [14:0] tmpOut;
  assign tmpIn = $signed(N_Downsample_RG3_1_360);
    assign med = $signed(tmpOut) ;
    assign N_CFIR_I_PolyphaseFIR_1_1_363 = med[14:0];
    CFIR_I_PolyphaseFIR_1 #(
      .inpBitWidth(14),
      .inpFrac(13),
      .coefBitWidth(9),
      .coefFrac(8),
      .dpBitWidth(15),
      .dpFrac(13),
      .outBitWidth(15),
      .tapLen(24),
      .extraLatency(0)
    ) myCFIR_I_PolyphaseFIR_1 (
      .clk(clkDiv128),
      .gReset(GlobalResetSel),
      .gEnable(GlobalEnable128),
      .inp(tmpIn),
      .outp(tmpOut)
    );
  end // CFIR_I_PolyphaseFIR_1_block
  endgenerate
  synDownsampleSimple #( .bitwidth(14) ) 
    Downsample_RG3 ( .clk(clkDiv128), .en(GlobalEnable128), .grst(GlobalResetSel), .inp(N_16), .outp(N_Downsample_RG3_1_360));
  generate
  begin: CFIR_I_PolyphaseFIR_0_block
    wire signed [14:0]  med;
    wire [13:0] tmpIn;
    wire [14:0] tmpOut;
  assign tmpIn = $signed(N_Downsample_RG2_1_359);
    assign med = $signed(tmpOut) ;
    assign N_CFIR_I_PolyphaseFIR_0_1_362 = med[14:0];
    CFIR_I_PolyphaseFIR_0 #(
      .inpBitWidth(14),
      .inpFrac(13),
      .coefBitWidth(9),
      .coefFrac(8),
      .dpBitWidth(15),
      .dpFrac(13),
      .outBitWidth(15),
      .tapLen(25),
      .extraLatency(0)
    ) myCFIR_I_PolyphaseFIR_0 (
      .clk(clkDiv128),
      .gReset(GlobalResetSel),
      .gEnable(GlobalEnable128),
      .inp(tmpIn),
      .outp(tmpOut)
    );
  end // CFIR_I_PolyphaseFIR_0_block
  endgenerate
  generate
  begin: Downsample_RG2_block
    wire enDs;

    assign enDs = (DownsampleCounterclkDiv64Drate2 == 0) && GlobalEnable64;
    synDelayWithEnable #( .bitwidth(14), .delaylength(1) ) dsDelay_block ( .clk(clkDiv64), .en(enDs), .grst(GlobalResetSel), .rst(1'b0), .inp(N_16), .outp(N_Downsample_RG2_1_359) );
  end //Downsample_RG2_block;
  endgenerate
  generate
  begin: CFIR_Q_Adder_block
    wire enab;
    wire [15:0] tmpOut;
    wire signed [15:0] tmp_N_CFIR_Q_PolyphaseFIR_0_1_357_0;
    wire signed [15:0] tmp_N_CFIR_Q_PolyphaseFIR_1_1_358_1;
    wire [15:0] tmpOutPre;
    assign  enab= GlobalEnable128;
    assign tmp_N_CFIR_Q_PolyphaseFIR_0_1_357_0 = ($signed(N_CFIR_Q_PolyphaseFIR_0_1_357) << 0);
    assign tmp_N_CFIR_Q_PolyphaseFIR_1_1_358_1 = ($signed(N_CFIR_Q_PolyphaseFIR_1_1_358) << 0);
    assign  tmpOutPre =   tmp_N_CFIR_Q_PolyphaseFIR_0_1_357_0 + tmp_N_CFIR_Q_PolyphaseFIR_1_1_358_1;
    assign tmpOut = tmpOutPre;
    synBusSatRnd #( .inp_width(16), .out_width(15), .infrac(13), .outfrac(13), .round(0), .sat(0), .datatype("SS") )
    sat_tmpOut ( .inp(tmpOut), .outp(N_CFIR_Q_Adder_2_356) );
  end // CFIR_Q_Adder_block
  endgenerate
  synBusAdapter #(
      .inp_width(15),
      .out_width(14),
      .datatype("signed"),
      .preshift(0)
    ) Convert_AutoGen378 (
      .inp(N_CFIR_Q_Adder_2_356),
      .outp(N_11)
   );
  generate
  begin: CFIR_Q_PolyphaseFIR_1_block
    wire signed [14:0]  med;
    wire [13:0] tmpIn;
    wire [14:0] tmpOut;
  assign tmpIn = $signed(N_Downsample_RG1_1_355);
    assign med = $signed(tmpOut) ;
    assign N_CFIR_Q_PolyphaseFIR_1_1_358 = med[14:0];
    CFIR_I_PolyphaseFIR_1 #(
      .inpBitWidth(14),
      .inpFrac(13),
      .coefBitWidth(9),
      .coefFrac(8),
      .dpBitWidth(15),
      .dpFrac(13),
      .outBitWidth(15),
      .tapLen(24),
      .extraLatency(0)
    ) myCFIR_Q_PolyphaseFIR_1 (
      .clk(clkDiv128),
      .gReset(GlobalResetSel),
      .gEnable(GlobalEnable128),
      .inp(tmpIn),
      .outp(tmpOut)
    );
  end // CFIR_Q_PolyphaseFIR_1_block
  endgenerate
  synDownsampleSimple #( .bitwidth(14) ) 
    Downsample_RG1 ( .clk(clkDiv128), .en(GlobalEnable128), .grst(GlobalResetSel), .inp(N_8), .outp(N_Downsample_RG1_1_355));
  generate
  begin: CFIR_Q_PolyphaseFIR_0_block
    wire signed [14:0]  med;
    wire [13:0] tmpIn;
    wire [14:0] tmpOut;
  assign tmpIn = $signed(N_Downsample_RG0_1_354);
    assign med = $signed(tmpOut) ;
    assign N_CFIR_Q_PolyphaseFIR_0_1_357 = med[14:0];
    CFIR_I_PolyphaseFIR_0 #(
      .inpBitWidth(14),
      .inpFrac(13),
      .coefBitWidth(9),
      .coefFrac(8),
      .dpBitWidth(15),
      .dpFrac(13),
      .outBitWidth(15),
      .tapLen(25),
      .extraLatency(0)
    ) myCFIR_Q_PolyphaseFIR_0 (
      .clk(clkDiv128),
      .gReset(GlobalResetSel),
      .gEnable(GlobalEnable128),
      .inp(tmpIn),
      .outp(tmpOut)
    );
  end // CFIR_Q_PolyphaseFIR_0_block
  endgenerate
  generate
  begin: Downsample_RG0_block
    wire enDs;

    assign enDs = (DownsampleCounterclkDiv64Drate2 == 0) && GlobalEnable64;
    synDelayWithEnable #( .bitwidth(14), .delaylength(1) ) dsDelay_block ( .clk(clkDiv64), .en(enDs), .grst(GlobalResetSel), .rst(1'b0), .inp(N_8), .outp(N_Downsample_RG0_1_354) );
  end //Downsample_RG0_block;
  endgenerate
  generate
  begin: Q_out_block
    reg [13:0] med;
    wire [13:0] inp_tmp /* synthesis syn_keep = 1 */;
  always @(posedge clkDiv128 or posedge GlobalResetSel)
  begin: Q_out_proc
    integer i;
    if(GlobalResetSel==1) 
      med <= 0;
    else if( GlobalEnable128==1)
      med <= inp_tmp;
  end // inProc
  assign inp_tmp = N_11;
  assign Q_out = med;
  end // Q_out_Block
  endgenerate
  generate
  begin: Mult_Q_block
    wire signed [21:0] tmpOut;
    wire signed [9:0] tmpin1;
    wire signed [11:0] tmpin2;
    wire signed [21:0] med;
    assign med = tmpOut ;
    assign N_5 = med[19:6];
    assign tmpin1 = $signed(N_2);
    assign tmpin2 = $signed(N_3);
    assign tmpOut = tmpin1 * tmpin2;
  end // Mult_Q_block
  endgenerate
  generate
  begin: Mult_I_block
    wire signed [21:0] tmpOut;
    wire signed [9:0] tmpin1;
    wire signed [11:0] tmpin2;
    wire signed [21:0] med;
    assign med = tmpOut ;
    assign N_7 = med[19:6];
    assign tmpin1 = $signed(N_2);
    assign tmpin2 = $signed(N_4);
    assign tmpOut = tmpin1 * tmpin2;
  end // Mult_I_block
  endgenerate
  generate
  begin: I_out_block
    reg [13:0] med;
    wire [13:0] inp_tmp /* synthesis syn_keep = 1 */;
  always @(posedge clkDiv128 or posedge GlobalResetSel)
  begin: I_out_proc
    integer i;
    if(GlobalResetSel==1) 
      med <= 0;
    else if( GlobalEnable128==1)
      med <= inp_tmp;
  end // inProc
  assign inp_tmp = N_12;
  assign I_out = med;
  end // I_out_Block
  endgenerate
  generate
  begin: Freq_block
    wire [31:0] out_tmp /* synthesis syn_keep = 1 */;
    reg [31:0] med;
  always @(posedge clk or posedge GlobalResetSel)
  begin: Freq_proc
    integer i;
    if(GlobalResetSel==1) 
      med <= 0;
    else if( GlobalEnable1==1)
      med <= Freq;
  end // inProc
  assign out_tmp = med;
  assign N_6 = out_tmp;
  end // Freq_Block
  endgenerate
  assign N_2 = ADC;
assign GlobalResetSel = GlobalReset;
endmodule

//-----------------------------------------

