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<doc>
<title>Resource Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Thu Mar 03 13:48:20 2016
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S050T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>896 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>STD</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>ddc</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\synthesis\ddc.edn</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>4183</cell>
 <cell>56340</cell>
 <cell>7.42</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>3688</cell>
 <cell>56340</cell>
 <cell>6.55</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>1131</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>74</cell>
 <cell>377</cell>
 <cell>19.63</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>74</cell>
 <cell>377</cell>
 <cell>19.63</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>0</cell>
 <cell>188</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>72</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>0</cell>
 <cell>69</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>22</cell>
 <cell>72</cell>
 <cell>30.56</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>4</cell>
 <cell>16</cell>
 <cell>25.00</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>0</cell>
 <cell>6</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>2</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>8</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>FDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>3391</cell>
 <cell>2896</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>792</cell>
 <cell>792</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>4183</cell>
 <cell>3688</cell>
</row>
</table>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>2</cell>
 <cell>3</cell>
</row>
<row>
 <cell>6</cell>
 <cell>1</cell>
</row>
<row>
 <cell>9</cell>
 <cell>2</cell>
</row>
<row>
 <cell>10</cell>
 <cell>4</cell>
</row>
<row>
 <cell>11</cell>
 <cell>4</cell>
</row>
<row>
 <cell>12</cell>
 <cell>4</cell>
</row>
<row>
 <cell>13</cell>
 <cell>6</cell>
</row>
<row>
 <cell>14</cell>
 <cell>72</cell>
</row>
<row>
 <cell>15</cell>
 <cell>17</cell>
</row>
<row>
 <cell>17</cell>
 <cell>4</cell>
</row>
<row>
 <cell>18</cell>
 <cell>49</cell>
</row>
<row>
 <cell>32</cell>
 <cell>1</cell>
</row>
<row>
 <cell>42</cell>
 <cell>20</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>187</cell>
</row>
</table>
<section><name>Detailed MACC Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>1</cell>
 <cell>22</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>22</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>46</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>28</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 46</cell>
 <cell> 28</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 74</cell>
 <cell>100.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>2896</cell>
 <cell>INT_NET</cell>
 <cell>Net   : GlobalReset_c</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: GlobalReset_ibuf_RNIP2EB/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>1290</cell>
 <cell>INT_NET</cell>
 <cell>Net   : clkDiv128_c</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: clkDiv128_ibuf_RNITBS9/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>1129</cell>
 <cell>INT_NET</cell>
 <cell>Net   : clk_c</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: clk_ibuf_RNIVTI2/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>477</cell>
 <cell>INT_NET</cell>
 <cell>Net   : clkDiv64_c</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: clkDiv64_ibuf_RNICQH8/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>286</cell>
 <cell>INT_NET</cell>
 <cell>Net   : CFG0_GND_INST_NET</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: CFG0_GND_INST</cell>
</row>
<row>
 <cell>84</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myCIC_Q.enDs</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myCIC_I/enDs</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG3_1_360[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG3/outp_ds[13]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG1_1_355[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG1/outp_ds[13]</cell>
</row>
<row>
 <cell>58</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG2_1_359[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG2_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[13]</cell>
</row>
<row>
 <cell>58</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG0_1_354[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG0_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[13]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_45[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg8/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_50[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg9/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_30[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg5/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_25[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg4/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>286</cell>
 <cell>INT_NET</cell>
 <cell>Net   : CFG0_GND_INST_NET</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: CFG0_GND_INST</cell>
</row>
<row>
 <cell>84</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myCIC_Q.enDs</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myCIC_I/enDs</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG3_1_360[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG3/outp_ds[13]</cell>
</row>
<row>
 <cell>64</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG1_1_355[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG1/outp_ds[13]</cell>
</row>
<row>
 <cell>58</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG2_1_359[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG2_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[13]</cell>
</row>
<row>
 <cell>58</cell>
 <cell>INT_NET</cell>
 <cell>Net   : N_Downsample_RG0_1_354[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Downsample_RG0_block.dsDelay_block/GenBlock.genblk1.theDelay/outreg[13]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_45[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg8/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_50[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg9/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_30[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg5/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
<row>
 <cell>49</cell>
 <cell>INT_NET</cell>
 <cell>Net   : myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/N_25[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: myDDS/mySinCos/myCORDIC_SinCos/myCORDIC2_stage/myCORDIC_onequadrant1/myCORDIC_stg4/Delay3_block/GenBlock.genblk1.theDelay/outreg[14]</cell>
</row>
</table>
</doc>
