set_family {SmartFusion2}
 add_include_path  {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl}
read_verilog {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\ddc.v}
 add_include_path  {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl}
read_verilog {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\hdl\SynLib.v}
set_top_level {ddc}
map_netlist
read_sdc {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\constraint\ddc.sdc}
check_constraints {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\constraint\synthesis_sdc_errors.log}
write_fdc {E:\Libero_11p7_updates\LL_11p6\m2s_tu0312_liberov11p6_df\Solutions\Verilog\DDC_top\designer\ddc\synthesis.fdc}
