Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)

Date      :  Tue Mar 01 09:44:51 2016
Project   :  D:\11.7_Upload\Accessing_EXT_SDRAM\Access_EXT_SDRAM
Component :  Access_EXT_SDRAM
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_feedthrough.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_interconnect_ntom.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_master_stage.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_matrix_m.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_matrix_s.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_ra_arbiter.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_ra_channel.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_rd_channel.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_rdmatrix_16Sto1M.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_rdmatrix_4Mto1S.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_slave_stage.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wa_arbiter.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wa_channel.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wd_arbiter.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wd_channel.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wresp_channel.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wrmatrix_4Mto1S.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/COREAXI/3.2.101/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/CORESDR_AXI/2.0.116/rtl/vlog/core_obfuscated/coresdr.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/CORESDR_AXI/2.0.116/rtl/vlog/core_obfuscated/coresdr_axi.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/CORESDR_AXI/2.0.116/rtl/vlog/core_obfuscated/fastinit.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/CORESDR_AXI/2.0.116/rtl/vlog/core_obfuscated/fastsdram.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/DirectCore/CORESDR_AXI/2.0.116/rtl/vlog/core_obfuscated/openbank.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/Access_EXT_SDRAM.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/COREAXI_0/rtl/vlog/core/coreaxi.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/FCCC_0/Access_EXT_SDRAM_FCCC_0_FCCC.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/OSC_0/Access_EXT_SDRAM_OSC_0_OSC.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/SgCore/OSC/2.0.101/osc_comps.v

HDL source files for Mentor Precision Synthesis tool:
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/Actel/SgCore/OSC/2.0.101/osc_comps_pre.v

Stimulus files for all Simulation tools:
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/subsystem.bfm

    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/COREAXI_0/coreparameters.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/COREAXI_0/rtl/vlog/test/user/axi_master.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/COREAXI_0/rtl/vlog/test/user/axi_slave.v
    D:/11.7_Upload/Accessing_EXT_SDRAM/Access_EXT_SDRAM/component/work/Access_EXT_SDRAM/COREAXI_0/rtl/vlog/test/user/testbench.v

