*******************************************
       Libero SoC, MSS and IP VERSIONS
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This tutorial was created with the following: 
Libero SoC Version: v11.7
MSS Version:  1.1.400
FCCC version: 2.0.200
CoreAXI: 3.2.101
CoreSDR_AXI: 2.0.116


NOTE:	This tutorial works as documented with Verilog as preferred language.
NOTE: 	For VHDL flow:
	 Since the Micron SDRAM memory models are only available in Verilog, if you are using the VHDL flow you need to use the ModelSim full version, for example ModelSim SE, 
	  since ModelSim ME does not support mixed-language flow. If you are using the ModelSim full version, you need to compile with novopt switch.
	 A .do file, run_novopt.do is provided in the Source folder of the Tutorial zip file. The -novopt switch is already set in this macro file.  
	  To use the provided run_novopt.do file, clear the Use automatic DO file check box and browse to the location of the provide run_novopt.do file.

      
	

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     DESIGN FILE DIRECTORY STRUCTURE
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SmartFusion2_SDRAM_Tutorial_DF
    |
    |
    |             
    |---Source
    |
    |---Solution
    |      |
    |      |--Access_EXT_SDRAM 
    |
    |---Readme.txt
    

EXT_SDRAM_Tutorial.PDF
==================================
This is the user's guide for this tutorial which includes step by step instructions for creating and simulating the design using Libero SoC design software.

Source
========
This folder consists of SDRAM simulation model(mt48lc16m16a2.v), the modeified testbench(testbench.v/testbench.vhd), the user.bfm and the ModelSim wave window macro file
(wave.do - to view the necessary design I/O signals in ModelSim simulator waveform window). User can export ports or signals of his/her interest to the Modelsim waveform window.
It also contains the run_novopt.do file for running the Tutorial in VHDL language in ModelSim SE with simulation optimization disabled. 

Solution
============================
For reference, the final Libero SoC Verilog project of this tutorial is given under this folder.

