#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Thu Apr 29 10:00:39 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\CCC_0\SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\FABOSC_0\SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb_MSS\SmartFusion2_FIC_Tutorial_sb_MSS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb_MSS\SmartFusion2_FIC_Tutorial_sb_MSS.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core\coregpio.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_ahbtoapbsm.v" (library COREAHBTOAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_apbaddrdata.v" (library COREAHBTOAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_penablescheduler.v" (library COREAHBTOAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3.v" (library COREAHBTOAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core_obfuscated\AHBLSramIf.v" (library COREAHBLSRAM_OBF_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\lsram_2048to139264x8.v" (library COREAHBLSRAM_OBF_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\usram_128to9216x8.v" (library COREAHBLSRAM_OBF_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\SramCtrlIf.v" (library COREAHBLSRAM_OBF_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\CoreAHBLSRAM.v" (library COREAHBLSRAM_OBF_LIB) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\SmartFusion2_FIC_Tutorial_sb.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module top @N:CG775 : coreahblite.v(23) | Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB @N:CG775 : CoreAHBLSRAM.v(9) | Component SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_COREAHBLSRAM not found in library "work" or "__hyper__lib__", but found in library COREAHBLSRAM_OBF_LIB @N:CG775 : coreahbtoapb3.v(25) | Component COREAHBTOAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAHBTOAPB3_LIB @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC.v(5) | Synthesizing module SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC in library work. Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC ....... @W:CG1283 : coreahblite.v(541) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite.v(541) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2639) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000011 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z1 ....... @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000011 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_3_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_3_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(2703) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z2 ....... @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @W:CG1283 : coreahblite_matrix4x16.v(2767) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : coreahblite_matrix4x16.v(2831) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z3 Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z3 ....... @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000000011 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s Running optimization stage 1 on COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s ....... @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b010011 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b1 M0_AHBSLOT1ENABLE=1'b1 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000000011 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z4 Running optimization stage 1 on CoreAHBLite_Z4 ....... @N:CG364 : AHBLSramIf.v(9) | Synthesizing module CHTOLSRAMII in library COREAHBLSRAM_OBF_LIB. Running optimization stage 1 on CHTOLSRAMII ....... @W:CL169 : AHBLSramIf.v(414) | Pruning unused register CHTOLSRAMi1[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(414) | Pruning unused register CHTOLSRAMO1[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(414) | Pruning unused register CHTOLSRAMIo. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(414) | Pruning unused register CHTOLSRAMlo. Make sure that there are no unused intermediate registers. @N:CG364 : SramCtrlIf.v(9) | Synthesizing module SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf in library COREAHBLSRAM_OBF_LIB. SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000100000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 AHB_DWIDTH=32'b00000000000000000000000000100000 CHTOLSRAMOOI=2'b00 CHTOLSRAMIOI=2'b01 CHTOLSRAMlOI=2'b10 Generated name = SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2 @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... @N:CG364 : lsram_2048to139264x8.v(9) | Synthesizing module CHTOLSRAMi1I in library COREAHBLSRAM_OBF_LIB. CHTOLSRAMOoI=32'b00000000000000000000100000000000 AHB_DWIDTH=32'b00000000000000000000000000001000 Generated name = CHTOLSRAMi1I_2048s_8s Running optimization stage 1 on CHTOLSRAMi1I_2048s_8s ....... @W:CL169 : lsram_2048to139264x8.v(1115) | Pruning unused register CHTOLSRAMIIl[15:9]. Make sure that there are no unused intermediate registers. @N:CG179 : SramCtrlIf.v(1474) | Removing redundant assignment. @W:CG133 : SramCtrlIf.v(185) | Object CHTOLSRAMIlI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : SramCtrlIf.v(193) | Object CHTOLSRAMllI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : SramCtrlIf.v(216) | Removing wire CHTOLSRAMilI, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(219) | Removing wire CHTOLSRAMO0I, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(222) | Removing wire CHTOLSRAMI0I, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(225) | Removing wire CHTOLSRAMl0I, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(256) | Removing wire CHTOLSRAMo1I, as there is no assignment to it. Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2 ....... @N:CG364 : CoreAHBLSRAM.v(9) | Synthesizing module SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_COREAHBLSRAM in library COREAHBLSRAM_OBF_LIB. FAMILY=32'b00000000000000000000000000010011 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000100000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 Generated name = SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_2048s_512s_0s Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_2048s_512s_0s ....... @N:CG364 : coreahbtoapb3_ahbtoapbsm.v(26) | Synthesizing module CoreAHBtoAPB3_AhbToApbSM in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 RSP_OKAY=2'b00 RSP_ERROR=2'b01 IDLE=3'b000 WRITE0=3'b001 WRITE1=3'b010 READ0=3'b011 WAIT=3'b100 Generated name = CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4 Running optimization stage 1 on CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4 ....... @N:CG364 : coreahbtoapb3_penablescheduler.v(26) | Synthesizing module CoreAHBtoAPB3_PenableScheduler in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=2'b00 WAIT=2'b01 WAITCLR=2'b10 Generated name = CoreAHBtoAPB3_PenableScheduler_0s_0_1_2 Running optimization stage 1 on CoreAHBtoAPB3_PenableScheduler_0s_0_1_2 ....... @N:CG364 : coreahbtoapb3_apbaddrdata.v(27) | Synthesizing module CoreAHBtoAPB3_ApbAddrData in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreAHBtoAPB3_ApbAddrData_0s Running optimization stage 1 on CoreAHBtoAPB3_ApbAddrData_0s ....... @N:CG364 : coreahbtoapb3.v(25) | Synthesizing module COREAHBTOAPB3 in library COREAHBTOAPB3_LIB. FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBTOAPB3_19s_0s Running optimization stage 1 on COREAHBTOAPB3_19s_0s ....... @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z5 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z5 ....... @N:CG364 : coregpio.v(23) | Synthesizing module CoreGPIO in library work. FAMILY=32'b00000000000000000000000000001011 IO_NUM=32'b00000000000000000000000000001000 APB_WIDTH=32'b00000000000000000000000000100000 OE_TYPE=1'b1 INT_BUS=1'b0 FIXED_CONFIG_0=1'b1 FIXED_CONFIG_1=1'b1 FIXED_CONFIG_2=1'b1 FIXED_CONFIG_3=1'b1 FIXED_CONFIG_4=1'b1 FIXED_CONFIG_5=1'b1 FIXED_CONFIG_6=1'b1 FIXED_CONFIG_7=1'b1 FIXED_CONFIG_8=1'b0 FIXED_CONFIG_9=1'b0 FIXED_CONFIG_10=1'b0 FIXED_CONFIG_11=1'b0 FIXED_CONFIG_12=1'b0 FIXED_CONFIG_13=1'b0 FIXED_CONFIG_14=1'b0 FIXED_CONFIG_15=1'b0 FIXED_CONFIG_16=1'b0 FIXED_CONFIG_17=1'b0 FIXED_CONFIG_18=1'b0 FIXED_CONFIG_19=1'b0 FIXED_CONFIG_20=1'b0 FIXED_CONFIG_21=1'b0 FIXED_CONFIG_22=1'b0 FIXED_CONFIG_23=1'b0 FIXED_CONFIG_24=1'b0 FIXED_CONFIG_25=1'b0 FIXED_CONFIG_26=1'b0 FIXED_CONFIG_27=1'b0 FIXED_CONFIG_28=1'b0 FIXED_CONFIG_29=1'b0 FIXED_CONFIG_30=1'b0 FIXED_CONFIG_31=1'b0 IO_TYPE_0=2'b01 IO_TYPE_1=2'b01 IO_TYPE_2=2'b01 IO_TYPE_3=2'b01 IO_TYPE_4=2'b01 IO_TYPE_5=2'b01 IO_TYPE_6=2'b01 IO_TYPE_7=2'b01 IO_TYPE_8=2'b00 IO_TYPE_9=2'b00 IO_TYPE_10=2'b00 IO_TYPE_11=2'b00 IO_TYPE_12=2'b00 IO_TYPE_13=2'b00 IO_TYPE_14=2'b00 IO_TYPE_15=2'b00 IO_TYPE_16=2'b00 IO_TYPE_17=2'b00 IO_TYPE_18=2'b00 IO_TYPE_19=2'b00 IO_TYPE_20=2'b00 IO_TYPE_21=2'b00 IO_TYPE_22=2'b00 IO_TYPE_23=2'b00 IO_TYPE_24=2'b00 IO_TYPE_25=2'b00 IO_TYPE_26=2'b00 IO_TYPE_27=2'b00 IO_TYPE_28=2'b00 IO_TYPE_29=2'b00 IO_TYPE_30=2'b00 IO_TYPE_31=2'b00 IO_INT_TYPE_0=3'b111 IO_INT_TYPE_1=3'b111 IO_INT_TYPE_2=3'b111 IO_INT_TYPE_3=3'b111 IO_INT_TYPE_4=3'b111 IO_INT_TYPE_5=3'b111 IO_INT_TYPE_6=3'b111 IO_INT_TYPE_7=3'b111 IO_INT_TYPE_8=3'b111 IO_INT_TYPE_9=3'b111 IO_INT_TYPE_10=3'b111 IO_INT_TYPE_11=3'b111 IO_INT_TYPE_12=3'b111 IO_INT_TYPE_13=3'b111 IO_INT_TYPE_14=3'b111 IO_INT_TYPE_15=3'b111 IO_INT_TYPE_16=3'b111 IO_INT_TYPE_17=3'b111 IO_INT_TYPE_18=3'b111 IO_INT_TYPE_19=3'b111 IO_INT_TYPE_20=3'b111 IO_INT_TYPE_21=3'b111 IO_INT_TYPE_22=3'b111 IO_INT_TYPE_23=3'b111 IO_INT_TYPE_24=3'b111 IO_INT_TYPE_25=3'b111 IO_INT_TYPE_26=3'b111 IO_INT_TYPE_27=3'b111 IO_INT_TYPE_28=3'b111 IO_INT_TYPE_29=3'b111 IO_INT_TYPE_30=3'b111 IO_INT_TYPE_31=3'b111 IO_VAL_0=1'b0 IO_VAL_1=1'b0 IO_VAL_2=1'b0 IO_VAL_3=1'b0 IO_VAL_4=1'b0 IO_VAL_5=1'b0 IO_VAL_6=1'b0 IO_VAL_7=1'b0 IO_VAL_8=1'b0 IO_VAL_9=1'b0 IO_VAL_10=1'b0 IO_VAL_11=1'b0 IO_VAL_12=1'b0 IO_VAL_13=1'b0 IO_VAL_14=1'b0 IO_VAL_15=1'b0 IO_VAL_16=1'b0 IO_VAL_17=1'b0 IO_VAL_18=1'b0 IO_VAL_19=1'b0 IO_VAL_20=1'b0 IO_VAL_21=1'b0 IO_VAL_22=1'b0 IO_VAL_23=1'b0 IO_VAL_24=1'b0 IO_VAL_25=1'b0 IO_VAL_26=1'b0 IO_VAL_27=1'b0 IO_VAL_28=1'b0 IO_VAL_29=1'b0 IO_VAL_30=1'b0 IO_VAL_31=1'b0 FIXED_CONFIG=32'b11111111000000000000000000000000 IO_INT_TYPE=96'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 IO_TYPE=64'b0101010101010101000000000000000000000000000000000000000000000000 IO_VAL=32'b00000000000000000000000000000000 Generated name = CoreGPIO_Z6 @N:CG179 : coregpio.v(504) | Removing redundant assignment. @N:CG179 : coregpio.v(507) | Removing redundant assignment. Running optimization stage 1 on CoreGPIO_Z6 ....... @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_both[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_neg[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[7].APB_32.edge_pos[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[7].gpin3[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[7].gpin1[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[7].gpin2[7]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_both[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_neg[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[6].APB_32.edge_pos[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[6].gpin3[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[6].gpin1[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[6].gpin2[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_both[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_neg[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[5].APB_32.edge_pos[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[5].gpin3[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[5].gpin1[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[5].gpin2[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_both[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_neg[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[4].APB_32.edge_pos[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[4].gpin3[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[4].gpin1[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[4].gpin2[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_both[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_neg[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_pos[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[3].gpin3[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[3].gpin1[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[3].gpin2[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_both[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_neg[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_pos[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[2].gpin3[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[2].gpin1[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[2].gpin2[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_both[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_neg[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_pos[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[1].gpin3[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[1].gpin1[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[1].gpin2[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(456) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_both[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(436) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_neg[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(416) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_pos[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(310) | Pruning unused register xhdl1.GEN_BITS[0].gpin3[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[0].gpin1[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(297) | Pruning unused register xhdl1.GEN_BITS[0].gpin2[0]. Make sure that there are no unused intermediate registers. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[0].APB_32.INTR_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[1].APB_32.INTR_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[2].APB_32.INTR_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[3].APB_32.INTR_reg[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[4].APB_32.INTR_reg[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[5].APB_32.INTR_reg[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[6].APB_32.INTR_reg[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : coregpio.v(476) | Optimizing register bit xhdl1.GEN_BITS[7].APB_32.INTR_reg[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.INTR_reg[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.INTR_reg[1]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.INTR_reg[2]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.INTR_reg[3]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[4].APB_32.INTR_reg[4]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[5].APB_32.INTR_reg[5]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[6].APB_32.INTR_reg[6]. Make sure that there are no unused intermediate registers. @W:CL169 : coregpio.v(476) | Pruning unused register xhdl1.GEN_BITS[7].APB_32.INTR_reg[7]. Make sure that there are no unused intermediate registers. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z7 Running optimization stage 1 on CoreResetP_Z7 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(5) | Synthesizing module SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC ....... @W:CL318 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... @N:CG364 : SmartFusion2_FIC_Tutorial_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... @N:CG364 : SmartFusion2_FIC_Tutorial_sb_MSS.v(9) | Synthesizing module SmartFusion2_FIC_Tutorial_sb_MSS in library work. Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb_MSS ....... @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : SmartFusion2_FIC_Tutorial_sb.v(9) | Synthesizing module SmartFusion2_FIC_Tutorial_sb in library work. Running optimization stage 1 on SmartFusion2_FIC_Tutorial_sb ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb_MSS ....... Running optimization stage 2 on MSS_075 ....... Running optimization stage 2 on TRIBUFF ....... Running optimization stage 2 on INBUF ....... Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC ....... @N:CL159 : SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on CoreResetP_Z7 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused. Running optimization stage 2 on CoreGPIO_Z6 ....... @W:CL246 : coregpio.v(181) | Input port bits 31 to 8 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coregpio.v(185) | Input GPIO_IN is unused. Running optimization stage 2 on CoreAPB3_Z5 ....... @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Running optimization stage 2 on COREAHBTOAPB3_19s_0s ....... @W:CL247 : coreahbtoapb3.v(33) | Input port bit 0 of HTRANS[1:0] is unused Running optimization stage 2 on CoreAHBtoAPB3_ApbAddrData_0s ....... Running optimization stage 2 on CoreAHBtoAPB3_PenableScheduler_0s_0_1_2 ....... @N:CL201 : coreahbtoapb3_penablescheduler.v(111) | Trying to extract state machine for register penableSchedulerState. Extracted state machine for register penableSchedulerState State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4 ....... @N:CL201 : coreahbtoapb3_ahbtoapbsm.v(265) | Trying to extract state machine for register ahbToApbSMState. Extracted state machine for register ahbToApbSMState State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_2048s_512s_0s ....... @W:CL246 : CoreAHBLSRAM.v(122) | Input port bits 31 to 20 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CHTOLSRAMi1I_2048s_8s ....... @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 15 to 11 of CHTOLSRAMIiI[15:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : lsram_2048to139264x8.v(54) | Input CHTOLSRAMOiI is unused. @N:CL159 : lsram_2048to139264x8.v(70) | Input CHTOLSRAMliI is unused. Running optimization stage 2 on RAM1K18 ....... Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2 ....... @N:CL201 : SramCtrlIf.v(258) | Trying to extract state machine for register CHTOLSRAMiOI. Extracted state machine for register CHTOLSRAMiOI State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(99) | Input port bits 19 to 18 of CHTOLSRAMl[19:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CHTOLSRAMII ....... @N:CL201 : AHBLSramIf.v(536) | Trying to extract state machine for register CHTOLSRAMoo. Extracted state machine for register CHTOLSRAMoo State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : AHBLSramIf.v(198) | Input BUSY is unused. Running optimization stage 2 on CoreAHBLite_Z4 ....... @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. Running optimization stage 2 on COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s ....... @N:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused. @N:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z3 ....... @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 ....... Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z2 ....... Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_3_0s_0_1_0 ....... @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 2 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 2 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z1 ....... Running optimization stage 2 on SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 29 10:00:40 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 29 10:00:40 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Apr 29 10:00:40 2021 ###########################################################] @A: : | multi_srs_gen output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Multi-srs Generator Report Linked File: top_multi_srs_gen.srr Premap Report # Thu Apr 29 10:00:41 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Reading constraint file: C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3074) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3028) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_2(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(3350) | Removing instance slavestage_10 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_3_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24598) | Removing sequential instance CHTOLSRAMOli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25583) | Removing sequential instance CHTOLSRAMO0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23613) | Removing sequential instance CHTOLSRAMOIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24401) | Removing sequential instance CHTOLSRAMiIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25386) | Removing sequential instance CHTOLSRAMili (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(26371) | Removing sequential instance CHTOLSRAMi0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23416) | Removing sequential instance CHTOLSRAMiOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24795) | Removing sequential instance CHTOLSRAMIli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25780) | Removing sequential instance CHTOLSRAMI0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23810) | Removing sequential instance CHTOLSRAMIIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24007) | Removing sequential instance CHTOLSRAMlIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24992) | Removing sequential instance CHTOLSRAMlli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25977) | Removing sequential instance CHTOLSRAMl0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24204) | Removing sequential instance CHTOLSRAMoIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25189) | Removing sequential instance CHTOLSRAMoli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23219) | Removing sequential instance CHTOLSRAMoOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24598) | Removing sequential instance CHTOLSRAMOli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25583) | Removing sequential instance CHTOLSRAMO0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23613) | Removing sequential instance CHTOLSRAMOIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24401) | Removing sequential instance CHTOLSRAMiIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25386) | Removing sequential instance CHTOLSRAMili (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(26371) | Removing sequential instance CHTOLSRAMi0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23416) | Removing sequential instance CHTOLSRAMiOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24795) | Removing sequential instance CHTOLSRAMIli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25780) | Removing sequential instance CHTOLSRAMI0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23810) | Removing sequential instance CHTOLSRAMIIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24007) | Removing sequential instance CHTOLSRAMlIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24992) | Removing sequential instance CHTOLSRAMlli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25977) | Removing sequential instance CHTOLSRAMl0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24204) | Removing sequential instance CHTOLSRAMoIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25189) | Removing sequential instance CHTOLSRAMoli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23219) | Removing sequential instance CHTOLSRAMoOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24598) | Removing sequential instance CHTOLSRAMOli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25583) | Removing sequential instance CHTOLSRAMO0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23613) | Removing sequential instance CHTOLSRAMOIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24401) | Removing sequential instance CHTOLSRAMiIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25386) | Removing sequential instance CHTOLSRAMili (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(26371) | Removing sequential instance CHTOLSRAMi0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23416) | Removing sequential instance CHTOLSRAMiOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24795) | Removing sequential instance CHTOLSRAMIli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25780) | Removing sequential instance CHTOLSRAMI0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23810) | Removing sequential instance CHTOLSRAMIIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24007) | Removing sequential instance CHTOLSRAMlIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24992) | Removing sequential instance CHTOLSRAMlli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25977) | Removing sequential instance CHTOLSRAMl0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24204) | Removing sequential instance CHTOLSRAMoIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25189) | Removing sequential instance CHTOLSRAMoli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23219) | Removing sequential instance CHTOLSRAMoOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24598) | Removing sequential instance CHTOLSRAMOli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25583) | Removing sequential instance CHTOLSRAMO0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23613) | Removing sequential instance CHTOLSRAMOIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24401) | Removing sequential instance CHTOLSRAMiIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25386) | Removing sequential instance CHTOLSRAMili (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(26371) | Removing sequential instance CHTOLSRAMi0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23416) | Removing sequential instance CHTOLSRAMiOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24795) | Removing sequential instance CHTOLSRAMIli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25780) | Removing sequential instance CHTOLSRAMI0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23810) | Removing sequential instance CHTOLSRAMIIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24007) | Removing sequential instance CHTOLSRAMlIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24992) | Removing sequential instance CHTOLSRAMlli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25977) | Removing sequential instance CHTOLSRAMl0i (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(24204) | Removing sequential instance CHTOLSRAMoIi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(25189) | Removing sequential instance CHTOLSRAMoli (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(23219) | Removing sequential instance CHTOLSRAMoOi (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMi1I_2048s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_2(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @W:MT688 : synthesis.fdc(8) | No path from master pin (-source) to source of clock SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 due to black box SmartFusion2_FIC_Tutorial_sb_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 15 1 . SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 356 ========================================================================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 15 SmartFusion2_FIC_Tutorial_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.release_sdif0_core.C - SmartFusion2_FIC_Tutorial_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 356 SmartFusion2_FIC_Tutorial_sb_0.CCC_0.CCC_INST.GL0(CCC) SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - SmartFusion2_FIC_Tutorial_sb_0.CCC_0.GL0_INST.I(BUFG) ==================================================================================================================================================================================================================================================================================================================================================================== @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 180MB peak: 183MB) Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine CHTOLSRAMoo[2:0] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine CHTOLSRAMiOI[2:0] (in view: COREAHBLSRAM_OBF_LIB.SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine ahbToApbSMState[4:0] (in view: COREAHBTOAPB3_LIB.CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine penableSchedulerState[2:0] (in view: COREAHBTOAPB3_LIB.CoreAHBtoAPB3_PenableScheduler_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 183MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 93MB peak: 184MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 29 10:00:43 2021 ###########################################################] Map & Optimize Report # Thu Apr 29 10:00:43 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 167MB peak: 167MB) @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : smartfusion2_fic_tutorial_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(929) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 171MB peak: 171MB) @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.SmartFusion2_FIC_Tutorial_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.SmartFusion2_FIC_Tutorial_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine CHTOLSRAMoo[2:0] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[13] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[14] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[15] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[16] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[17] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[18] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(414) | Removing sequential instance CHTOLSRAMo1[19] (in view: COREAHBLSRAM_OBF_LIB.CHTOLSRAMII(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine CHTOLSRAMiOI[2:0] (in view: COREAHBLSRAM_OBF_LIB.SmartFusion2_FIC_Tutorial_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_2048s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[24] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[25] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[26] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[27] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(68) | Removing sequential instance U_ApbAddrData.haddrReg[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[24] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[25] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[26] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[27] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(113) | Removing sequential instance U_ApbAddrData.hwdataReg[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[24] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[25] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[26] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[27] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(97) | Removing sequential instance U_ApbAddrData.nextHaddrReg[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[31] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[30] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[29] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[28] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[27] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[26] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[25] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[24] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[23] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[22] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[21] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[20] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[19] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[18] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[17] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[16] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[15] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[14] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[13] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[12] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[11] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[10] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[9] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(136) | Register bit U_ApbAddrData.HRDATA[8] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine ahbToApbSMState[4:0] (in view: COREAHBTOAPB3_LIB.CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @W:BN132 : coreahbtoapb3_ahbtoapbsm.v(265) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_AhbToApbSM.PWRITE because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_AhbToApbSM.ahbToApbSMState[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine penableSchedulerState[2:0] (in view: COREAHBTOAPB3_LIB.CoreAHBtoAPB3_PenableScheduler_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 173MB peak: 173MB) @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. @W:BN132 : coreahbtoapb3_penablescheduler.v(111) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_PenableScheduler.PENABLE because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_PenableScheduler.penableSchedulerState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : ahblsramif.v(414) | Removing sequential instance COREAHBLSRAM_0_0.CHTOLSRAMlI.CHTOLSRAMl1[2] (in view: work.SmartFusion2_FIC_Tutorial_sb(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.INIT_DONE_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sm0_state[6] (in view: work.top(verilog)) because it does not drive other instances. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[10] (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[9] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[9] because it is equivalent to instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[5] (in view: work.top(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 177MB peak: 177MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 177MB peak: 178MB) @N:BN362 : coreresetp.v(1549) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.release_sdif2_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1517) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.release_sdif1_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1485) | Removing sequential instance SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.release_sdif0_core (in view: work.top(verilog)) because it does not drive other instances. Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\synlog\top_fpga_mapper.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell. Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 177MB peak: 178MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -1.45ns 277 / 174 2 0h:00m:02s -1.45ns 268 / 174 3 0h:00m:02s -1.45ns 268 / 174 4 0h:00m:02s -1.10ns 269 / 174 5 0h:00m:02s -0.93ns 269 / 174 6 0h:00m:03s -0.95ns 269 / 174 @N:FP130 : | Promoting Net SmartFusion2_FIC_Tutorial_sb_0.MSS_HPMS_READY_int_arst on CLKINT I_9 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 184MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 184MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 184 clock pin(s) of sequential element(s) 0 instances converted, 184 sequential instances remain driven by gated/generated clocks =============================================================================================================== Gated/Generated Clocks =============================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 SmartFusion2_FIC_Tutorial_sb_0.CCC_0.CCC_INST CCC 184 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ====================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 150MB peak: 184MB) Writing Analyst data base C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 180MB peak: 184MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 181MB peak: 184MB) Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 180MB peak: 184MB) @W:MT246 : smartfusion2_fic_tutorial_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Thu Apr 29 10:00:48 2021 # Top view: top Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.313 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 100.0 MHz 103.2 MHz 10.000 9.687 0.313 generated (from SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz NA 20.000 NA NA declared default_clkgroup =========================================================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 | 10.000 0.313 | No paths - | No paths - | No paths - ========================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[26] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] 3.053 0.313 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[27] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] 3.030 0.539 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[24] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] 3.023 0.546 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[25] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] 3.051 0.601 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_TRANS1 SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] 3.108 0.836 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE Q masterRegAddrSel 0.094 2.596 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE Q regHADDR[26] 0.094 3.468 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_SIZE[1] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HSIZE[1] 3.198 3.523 SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 MSS_075 F_HM0_SIZE[0] SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HSIZE[0] 3.190 3.528 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE Q SDATASELInt[4] 0.094 3.673 ============================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[0] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[0] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[2] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[2] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[3] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[3] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[4] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[4] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[5] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[5] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[6] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[6] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[7] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[7] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[12] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[12] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[13] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[13] 9.778 0.313 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[14] SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 SLE D haddrReg_5[14] 9.778 0.313 ================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 9.465 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.313 Number of logic level(s): 6 Starting point: SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[26] Ending point: SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[0] / D The start point is clocked by SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE The end point is clocked by SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[26] Out 3.053 3.053 r - SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] Net - - 0.432 - 2 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[26] CFG3 B In - 3.485 r - SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[26] CFG3 Y Out 0.143 3.628 r - M0GATEDHADDR[26] Net - - 0.987 - 15 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2_i_o2[2] CFG2 A In - 4.615 r - SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2_i_o2[2] CFG2 Y Out 0.067 4.683 r - N_94 Net - - 0.708 - 4 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2_i_o2_RNICF151[2] CFG4 D In - 5.391 r - SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_2_i_o2_RNICF151[2] CFG4 Y Out 0.284 5.675 f - m0s1AddrSel Net - - 0.814 - 8 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState_RNITGC72[13] CFG4 D In - 6.489 f - SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState_RNITGC72[13] CFG4 Y Out 0.250 6.739 f - N_148_i Net - - 1.056 - 24 SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNI6SCK3[1] CFG4 C In - 7.795 f - SmartFusion2_FIC_Tutorial_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNI6SCK3[1] CFG4 Y Out 0.182 7.978 f - latchAddr4 Net - - 0.987 - 15 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg_5[0] CFG4 D In - 8.965 f - SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg_5[0] CFG4 Y Out 0.284 9.249 r - haddrReg_5[0] Net - - 0.216 - 1 SmartFusion2_FIC_Tutorial_sb_0.COREAHBTOAPB3_0.U_ApbAddrData.haddrReg[0] SLE D In - 9.465 r - ================================================================================================================================================================================================ Total path delay (propagation time + setup) of 9.687 is 4.485(46.3%) logic and 5.201(53.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(9) | Timing constraint (through [get_nets { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.ddr_settled SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.count_ddr_enable SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.release_sdif*_core SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(10) | Timing constraint (from [get_cells { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sm0_areset_n_rcosc SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.MSS_HPMS_READY_int SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(12) | Timing constraint (through [get_nets { SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG1_DONE SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.CONFIG2_DONE SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF*_PERST_N SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF*_PSEL SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF*_PWRITE SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SDIF*_PRDATA[*] SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_EXT_RESET_OUT SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_RESET_F2M SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_M3_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_FDDR_CORE_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET SmartFusion2_FIC_Tutorial_sb_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { SmartFusion2_FIC_Tutorial_sb_0.SmartFusion2_FIC_Tutorial_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { SmartFusion2_FIC_Tutorial_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 180MB peak: 184MB) Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 180MB peak: 184MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 2 uses MSS_075 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG2 102 uses CFG3 41 uses CFG4 120 uses Sequential Cells: SLE 175 uses DSP Blocks: 0 of 84 (0%) I/O ports: 11 I/O primitives: 10 INBUF 1 use OUTBUF 8 uses TRIBUFF 1 use Global Clock Buffers: 2 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 4 of 109 (3%) Total LUTs: 263 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 144; LUTs = 144; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 175 + 0 + 144 + 0 = 319; Total number of LUTs after P&R: 263 + 0 + 144 + 0 = 407; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 65MB peak: 184MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Thu Apr 29 10:00:48 2021 ###########################################################]