Project Settings
Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 158 156 0 - 00m:01s - 4/29/2021
10:00:40 AM
(premap)out-of-date 114 33 0 0m:01s 0m:01s 184MB 4/29/2021
10:00:42 AM
(fpga_mapper)out-of-date 146 57 0 0m:05s 0m:05s 184MB 4/29/2021
10:00:48 AM

Area Summary
Sequential Cells 175 DSP Blocks (dsp_used) 0
I/O Cells 10 Global Clock Buffers 2
RAM1K18 (v_ram) 4 LUTs (total_luts) 263

Timing Summary
Clock NameReq FreqEst FreqSlack
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0100.0 MHz103.2 MHz0.313
SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT50.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 0 / 1