Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Fri Apr 30 08:42:05 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 10.000 100.000 3.676 WORST
SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0] 5.712 3.676 11.976 15.652 0.407 6.324 WORST
Path 2 SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0] 5.654 3.735 11.918 15.653 0.407 6.265 WORST
Path 3 SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:EN 5.632 3.777 11.896 15.673 0.254 6.223 WORST
Path 4 SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:EN 5.634 3.784 11.898 15.682 0.254 6.216 WORST
Path 5 SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:EN 5.632 3.786 11.896 15.682 0.254 6.214 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0]
data required time 15.652
data arrival time - 11.976
slack 3.676
Data arrival time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 0.000 0.000
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_net + 0.461 4.320 r
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 9 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.618 5.116 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.432 1 r
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 5.839 r
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.048 1 r
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.264 r
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_ADDR[26] cell ADLIB:MSS_075_IP + 1.291 7.555 2 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:B net SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] + 0.433 7.988 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:Y cell ADLIB:CFG3 + 0.074 8.062 15 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:A net SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/M0GATEDHADDR[26] + 0.209 8.271 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:Y cell ADLIB:CFG4 + 0.270 8.541 1 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIACTB1[27]:A net SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/m14_sx + 0.091 8.632 r
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIACTB1[27]:Y cell ADLIB:CFG2 + 0.100 8.732 8 f
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:D net SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/m0s0AddrSel + 0.631 9.363 f
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:Y cell ADLIB:CFG4 + 0.087 9.450 22 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:C net SmartFusion2_FIC_Tutorial_sb_0/HREADYOUT_m_1 + 0.712 10.162 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:Y cell ADLIB:CFG4 + 0.087 10.249 2 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:D net SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3 + 0.097 10.346 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:Y cell ADLIB:CFG4 + 0.087 10.433 1 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:C net SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[2] + 1.261 11.694 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:IPC cell ADLIB:CFG2_IP_BC + 0.208 11.902 1 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0] net SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/A_WEN_net[0] + 0.074 11.976 f
data arrival time 11.976
Data required time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_net + 0.461 14.320 r
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 9 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.617 15.115 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 15.431 8 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_0:CLK net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.490 15.921 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_0:IPCLKn cell ADLIB:SLE_IP_CLK + 0.059 15.980 1 f
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_CLK net SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/A_CLK_net + 0.079 16.059 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0] Library setup time ADLIB:RAM1K18_IP - 0.407 15.652
data required time 15.652
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:CLK GPIO_OUT[1] 8.552 14.483 14.483 WORST
Path 2 SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:CLK GPIO_OUT[5] 8.516 14.459 14.459 WORST
Path 3 SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:CLK GPIO_OUT[6] 8.373 14.320 14.320 WORST
Path 4 SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:CLK GPIO_OUT[4] 8.354 14.301 14.301 WORST
Path 5 SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:CLK GPIO_OUT[7] 8.335 14.295 14.295 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:CLK
To: GPIO_OUT[1]
data required time N/C
data arrival time - 14.483
slack N/C
Data arrival time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 0.000 0.000
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_net + 0.461 4.320 r
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 9 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.605 5.103 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR cell ADLIB:RGB + 0.316 5.419 30 r
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:CLK net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1 + 0.512 5.931 r
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:Q cell ADLIB:SLE + 0.108 6.039 2 f
GPIO_OUT_obuf[1]/U0/U_IOOUTFF:A net GPIO_OUT_c[1] + 5.350 11.389 f
GPIO_OUT_obuf[1]/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 11.719 1 f
GPIO_OUT_obuf[1]/U0/U_IOPAD:D net GPIO_OUT_obuf[1]/U0/DOUT + 0.098 11.817 f
GPIO_OUT_obuf[1]/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 14.483 0 f
GPIO_OUT[1] net GPIO_OUT[1] + 0.000 14.483 f
data arrival time 14.483
Data required time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 N/C N/C
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.859 N/C
GPIO_OUT[1] N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:ALn 3.866 5.800 9.778 15.578 0.353 4.200 -0.019 WORST
Path 2 SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:ALn 3.866 5.800 9.778 15.578 0.353 4.200 -0.019 WORST
Path 3 SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:ALn 3.866 5.800 9.778 15.578 0.353 4.200 -0.019 WORST
Path 4 SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:ALn 3.866 5.800 9.778 15.578 0.353 4.200 -0.019 WORST
Path 5 SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:ALn 3.866 5.800 9.778 15.578 0.353 4.200 -0.019 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK
To: SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:ALn
data required time 15.578
data arrival time - 9.778
slack 5.800
Data arrival time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 0.000 0.000
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_net + 0.461 4.320 r
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 9 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.610 5.108 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YL cell ADLIB:RGB + 0.317 5.425 1 r
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbl_net_1 + 0.487 5.912 r
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:Q cell ADLIB:SLE + 0.092 6.004 1 r
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB:An net SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_Z + 1.927 7.931 f
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB:YEn cell ADLIB:GBM + 0.374 8.305 6 f
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_RGB1_RGB3:An net SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_YWn_GEast + 0.593 8.898 f
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.316 9.214 41 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:ALn net SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_RGB1_RGB3_rgbr_net_1 + 0.564 9.778 r
data arrival time 9.778
Data required time calculation
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_net + 0.461 14.320 r
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 9 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.605 15.103 f
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR cell ADLIB:RGB + 0.316 15.419 41 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:CLK net SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1 + 0.512 15.931 r
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:ALn Library recovery time ADLIB:SLE - 0.353 15.578
data required time 15.578
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets