pin,slack
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_32:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[13]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[13]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[13]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[13]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[13]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_265:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_276:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_36:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_8:B,6405
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_8:C,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_8:IPB,6405
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_8:IPC,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[14]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[14]:CLK,6548
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[14]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[14]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[14]:Q,6548
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_23:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_23:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_195:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_195:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_0:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_0:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_7:IPENn,
GPIO_OUT_obuf[6]/U0/U_IOPAD:D,
GPIO_OUT_obuf[6]/U0/U_IOPAD:E,
GPIO_OUT_obuf[6]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_15:C,8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_15:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_15:IPC,8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_21:B,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_21:IPB,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_21:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_86:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_86:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_23:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_23:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_215:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_215:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_31:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_31:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_3:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[24]:A,1932
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[24]:B,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[24]:C,2084
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[24]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_5:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_5:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m6_i_x2:A,6035
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m6_i_x2:B,5958
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m6_i_x2:C,3458
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m6_i_x2:Y,3458
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_251:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_251:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_199:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_199:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_81:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_81:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0_RNIKAQO4:A,2800
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0_RNIKAQO4:B,1256
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0_RNIKAQO4:C,6824
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0_RNIKAQO4:D,5804
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0_RNIKAQO4:Y,1256
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_16:B,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_16:C,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_16:IPB,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_16:IPC,8812
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[5]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[5]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[5]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[5]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[9]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[9]:B,5485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[9]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[9]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[9]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_23:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_49:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_218:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_218:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_239:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_239:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[8]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[8]:B,5485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[8]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[8]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[8]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_66:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_66:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_2:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0:A,5586
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0:B,4668
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0:C,2878
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0:D,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0:Y,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_34:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[0]:A,7451
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[0]:B,7367
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[0]:C,6166
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[0]:D,6955
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[0]:Y,6166
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:CLK,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:D,7456
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[15]:Q,7032
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_PWRITE_0_o3:A,7964
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_PWRITE_0_o3:B,7870
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_PWRITE_0_o3:C,7816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_PWRITE_0_o3:Y,7816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNO[3]:A,7073
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNO[3]:B,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNO[3]:C,5374
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNO[3]:D,1052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNO[3]:Y,1052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[0]:CLK,5641
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[0]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[0]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[0]:Q,5641
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_2:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_2:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:CLK,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[2]:Q,8466
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_61:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_23:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_23:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:D,7460
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[0]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_6:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_30:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[12]:A,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[12]:B,4578
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[12]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNITGC72[13]:A,5651
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNITGC72[13]:B,5574
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNITGC72[13]:C,5522
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNITGC72[13]:D,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNITGC72[13]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[1]:A,2357
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[1]:B,5414
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[1]:Y,2357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[7]:CLK,7331
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[7]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[7]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[7]:Q,7331
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[4]:CLK,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[4]:D,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[4]:EN,5484
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[4]:Q,-111
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_70:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[4]:CLK,5789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[4]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[4]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[4]:Q,5789
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_134:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2:A,7140
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2:B,7053
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2:C,6972
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2:Y,6972
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_10:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_29:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_29:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:D,7496
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[2]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_160:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_160:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_11:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_152:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_152:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_55:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_55:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_29:EN,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_29:IPENn,9127
GPIO_OUT_obuf[7]/U0/U_IOENFF:A,
GPIO_OUT_obuf[7]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_35:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_32:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[31]:A,7096
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[31]:B,7253
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[31]:Y,7096
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:A,944
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:B,976
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:C,822
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:D,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIA6QI[27]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_110:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_0_0:A,5610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_0_0:B,5777
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_0_0:C,4264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_0_0:D,4624
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_0_0:Y,4264
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:E,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMio_1_sqmuxa_i:A,3723
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMio_1_sqmuxa_i:B,4617
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMio_1_sqmuxa_i:Y,3723
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_236:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_236:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_187:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4:A,1391
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4:B,1220
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4:C,5044
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4:D,4245
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4:Y,1220
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_25:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:CLK,7468
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:D,6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[6]:Q,7468
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_17:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_17:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:A,7011
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:B,7032
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:IPA,7011
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_16:IPB,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_194:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_194:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_1:IPCLKn,
GPIO_OUT_obuf[2]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[2]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_30:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_15:C,8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_15:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_15:IPC,8610
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[12]:A,7190
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[12]:B,7340
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[12]:Y,7190
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[0]:CLK,5905
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[0]:D,1164
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[0]:Q,5905
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_1:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:A,2020
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:B,822
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:C,2172
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:Y,822
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_11:B,7111
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_11:IPB,7111
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int:ALn,8748
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK,9089
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int:D,7875
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q,9089
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0:A,2111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0:B,1839
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0:C,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_0:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_0:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_34:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[19]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[19]:CLK,7199
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[19]:D,6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[19]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[19]:Q,7199
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_12:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_12:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[1]:CLK,2228
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[1]:D,1238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[1]:Q,2228
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[23]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[23]:CLK,7227
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[23]:D,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[23]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[23]:Q,7227
GPIO_OUT_obuf[4]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[4]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_285:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_285:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_14:C,8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_14:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_14:IPC,8607
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[6]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[6]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[6]:C,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[6]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[6]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_7:A,6154
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_7:B,7190
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_7:IPA,6154
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_7:IPB,7190
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_38:IPA,
GPIO_OUT_obuf[7]/U0/U_IOPAD:D,
GPIO_OUT_obuf[7]/U0/U_IOPAD:E,
GPIO_OUT_obuf[7]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[11]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[11]:CLK,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[11]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[11]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[11]:Q,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[7]:CLK,7415
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[7]:D,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[7]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[7]:Q,7415
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_28:B,6421
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_28:C,8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_28:IPB,6421
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_28:IPC,8769
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[26]:A,6996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[26]:B,7153
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[26]:Y,6996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_88:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_88:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[1]:CLK,5543
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[1]:D,2357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[1]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[1]:Q,5543
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2:A,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2:B,2044
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2:C,7614
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2:D,5127
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[17]:A,6962
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[17]:B,7119
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[17]:Y,6962
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_5:B,6368
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_5:IPB,6368
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_5:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[6]:CLK,7384
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[6]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[6]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[6]:Q,7384
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_15:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_26:C,8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_26:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_26:IPC,8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_6:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_111:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_111:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_8:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[20]:A,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[20]:B,7208
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[20]:Y,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_31:C,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_31:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_31:IPC,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[0]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[0]:D,6480
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[0]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[0]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_29:B,6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_29:C,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_29:IPB,6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_29:IPC,8726
GPIO_OUT_obuf[5]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[5]/U0/U_IOOUTFF:Y,
GPIO_OUT_obuf[4]/U0/U_IOPAD:D,
GPIO_OUT_obuf[4]/U0/U_IOPAD:E,
GPIO_OUT_obuf[4]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_168:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_146:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[3]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[3]:B,5485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[3]:C,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[3]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[3]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/nextWrite:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/nextWrite:CLK,5997
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/nextWrite:D,2318
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/nextWrite:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/nextWrite:Q,5997
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_31:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_6:C,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_6:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_6:IPC,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[10],8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[11],8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[12],8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[13],8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[3],8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[4],8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[5],8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[6],8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[7],8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[8],8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[9],8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ARST_N,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_CLK,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[0],6238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[1],6275
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[2],6243
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[3],6288
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[4],6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[5],6395
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[6],6382
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[7],6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[0],6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[1],6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[2],6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[3],6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[4],6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[5],6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[6],6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[7],6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0],761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[10],8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[11],8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[12],8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[13],8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[3],8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[4],8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[5],8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[6],8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[7],8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[8],8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[9],8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ARST_N,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[0],6231
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[1],6264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[2],6232
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[3],6277
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[4],6386
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[5],6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[6],6374
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[7],6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_RXD_PAD/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_RXD_PAD/U_IOPAD:Y,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_118:IPB,
GPIO_OUT_obuf[2]/U0/U_IOENFF:A,
GPIO_OUT_obuf[2]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_10:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_260:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_260:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_6[0]:A,6231
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_6[0]:B,7503
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_6[0]:Y,6231
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_68:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_68:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT:CLK,1989
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT:D,1220
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT:Q,1989
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_263:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_263:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_11:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[8]:A,7168
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[8]:B,7325
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[8]:Y,7168
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_19:C,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_19:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_19:IPC,8793
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[3]:A,4576
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[3]:B,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2_0[3]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[15]:A,7091
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[15]:B,7241
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[15]:Y,7091
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_221:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_221:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_210:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_210:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_3:A,2691
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_3:B,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_3:C,1602
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_3:D,2377
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_3:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_35:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_213:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_213:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_0:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_0:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:D,7404
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[8]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI_RNO:A,7990
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI_RNO:B,7920
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI_RNO:C,7862
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI_RNO:Y,7862
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_107:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[7]:CLK,5859
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[7]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[7]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[7]:Q,5859
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_113:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_113:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_7:C,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_7:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_7:IPC,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i_RNO:A,5731
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i_RNO:B,4226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i_RNO:C,6613
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i_RNO:D,6475
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i_RNO:Y,4226
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_state:ALn,8748
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_state:CLK,7852
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_state:EN,8785
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_state:Q,7852
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_30:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[1]:A,7997
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[1]:B,6896
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[1]:C,3468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[1]:D,2200
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[1]:Y,2200
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_a3_0_0[0]:A,6110
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_a3_0_0[0]:B,7026
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_a3_0_0[0]:Y,6110
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_9:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0:A,6980
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0:B,6928
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0:C,1238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0:D,1273
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0:Y,1238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[15]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[15]:CLK,7241
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[15]:D,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[15]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[15]:Q,7241
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[15]:A,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[15]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[15]:C,5493
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[15]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[15]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[1]:CLK,5061
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[1]:D,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[1]:Q,5061
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[10],8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[11],8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[12],8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[13],8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[3],8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[4],8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[5],8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[6],8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[7],8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[8],8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[9],8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ARST_N,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_CLK,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[0],6399
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[1],6433
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[2],6440
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[3],6442
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[4],6413
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[5],6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[6],6446
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[7],6448
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[0],6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[1],6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[2],6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[3],6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[4],6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[5],6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[6],6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[7],6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0],875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[10],8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[11],8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[12],8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[13],8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[3],8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[4],8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[5],8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[6],8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[7],8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[8],8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[9],8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ARST_N,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[0],6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[1],6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[2],6429
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[3],6431
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[4],6402
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[5],6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[6],6438
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[7],6443
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_16:B,6413
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_16:C,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_16:IPB,6413
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_16:IPC,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[4]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[4]:D,6581
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[4]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[4]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_180:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_34:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_5[0]:A,6264
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_5[0]:B,7511
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_5[0]:Y,6264
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[12]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[12]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[12]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[12]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[12]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_15:C,8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_15:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_15:IPC,8610
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO:A,2228
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO:B,2144
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO:C,1878
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO:D,1758
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO:Y,1758
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending:CLK,5958
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending:D,2098
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending:EN,1224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending:Q,5958
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[16]:A,6380
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[16]:B,7503
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[16]:Y,6380
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[28]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[28]:CLK,7189
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[28]:D,6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[28]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[28]:Q,7189
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_3[0]:A,6277
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_3[0]:B,7515
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_3[0]:Y,6277
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_262:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_262:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_31:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNO:A,1224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNO:B,6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNO:C,5888
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNO:Y,1224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_24:B,6435
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_24:C,8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_24:IPB,6435
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_24:IPC,8821
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[9]:A,6368
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[9]:B,7511
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[9]:Y,6368
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_205:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_6:A,167
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_6:B,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_6:Y,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg[0]:CLK,1878
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg[0]:D,3207
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg[0]:EN,7801
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg[0]:Q,1878
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_30:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_30:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[4]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[4]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[4]:C,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[4]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[4]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[0]:CLK,7677
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[0]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[0]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[0]:Q,7677
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[2]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[2]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[2]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[2]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[2]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_212:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_212:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[4]:CLK,7341
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[4]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[4]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[4]:Q,7341
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_80:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_80:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:CLK,135
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[12]:Q,135
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_9:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_74:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_122:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_18:A,7077
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_18:B,6986
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_18:IPA,7077
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_18:IPB,6986
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_52:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_52:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_208:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_208:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_4:B,6433
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_4:IPB,6433
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_4:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_5:EN,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_5:IPENn,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_30:C,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_30:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_30:IPC,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[12]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[12]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[12]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[12]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[12]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:CLK,2308
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:D,7491
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:Q,2308
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:CLK,5224
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:D,2200
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:Q,5224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_5:B,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_5:IPB,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_5:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_19:C,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_19:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_19:IPC,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_7:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[3]:CLK,6809
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[3]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[3]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[3]:Q,6809
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_25:B,6389
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_25:C,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_25:IPB,6389
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_25:IPC,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[26]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[26]:CLK,7153
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[26]:D,6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[26]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[26]:Q,7153
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_60:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[5]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[5]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[5]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[5]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/GPOUT_reg_0_sqmuxa:A,7829
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/GPOUT_reg_0_sqmuxa:B,7752
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/GPOUT_reg_0_sqmuxa:C,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/GPOUT_reg_0_sqmuxa:D,5749
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/GPOUT_reg_0_sqmuxa:Y,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_RNI6SCK3[1]:A,3476
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_RNI6SCK3[1]:B,6676
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_RNI6SCK3[1]:C,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_RNI6SCK3[1]:D,4108
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt_RNI6SCK3[1]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_33:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_264:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:CLK,1932
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:D,779
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:Q,1932
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[2]:CLK,7034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[2]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[2]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[2]:Q,7034
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[0]:CLK,1758
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[0]:D,4413
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[0]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[0]:Q,1758
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_26:C,8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_26:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_26:IPC,8767
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_181:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_9:B,6404
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_9:C,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_9:IPB,6404
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_9:IPC,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_0:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_0:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_214:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_214:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_165:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_165:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_1:B,6231
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_1:IPB,6231
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_1:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_156:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0_RNO:A,5665
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0_RNO:B,5577
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0_RNO:C,5543
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0_RNO:Y,5543
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[0]:CLK,4376
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[0]:D,7319
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[0]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[0]:Q,4376
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[28]:A,6402
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[28]:B,7535
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[28]:Y,6402
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_35:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_115:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_115:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[15]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[15]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[15]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[15]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[15]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_188:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7:A,4518
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7:B,3458
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7:C,5812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7:D,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7:Y,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0_o2:A,5061
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0_o2:B,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0_o2:Y,5018
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_169:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[29]:A,6420
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[29]:B,7545
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[29]:Y,6420
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_3:A,6113
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_3:B,7168
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_3:IPA,6113
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_3:IPB,7168
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_100:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS[0]:A,6774
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS[0]:B,5749
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS[0]:C,6649
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS[0]:D,6548
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS[0]:Y,5749
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[7]:A,7415
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[7]:B,7331
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[7]:C,6130
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[7]:D,6919
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[7]:Y,6130
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[7].APB_32.GPOUT_reg[7]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_7:C,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_7:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_7:IPC,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_17:B,6402
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_17:C,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_17:IPB,6402
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_17:IPC,8773
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_46:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_8:A,6183
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_8:B,7071
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_8:IPA,6183
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_8:IPB,7071
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_271:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_267:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_267:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_31:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_280:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_280:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_119:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO:A,3707
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO:B,5942
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO:C,2190
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO:D,4208
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO:Y,2190
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_m2_0_a3:A,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_m2_0_a3:B,5757
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/d_m2_0_a3:Y,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[4]:CLK,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[4]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[4]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[4]:Q,8627
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_0:A,3037
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_0:IPA,3037
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_35:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[0]:A,6980
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[0]:B,3479
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[0]:C,7876
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[0]:D,6844
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNO[0]:Y,3479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[0]:CLK,5665
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[0]:D,2357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[0]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMl1_Z[0]:Q,5665
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_283:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_283:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMli:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMli:CLK,4730
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMli:D,7906
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMli:Q,4730
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:CLK,-33
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:D,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[5]:Q,-33
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[1]:CLK,7400
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[1]:D,6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[1]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[1]:Q,7400
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_41:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_41:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_183:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_183:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_217:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_24:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_24:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_8:B,6440
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_8:C,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_8:IPB,6440
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_8:IPC,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[3]:CLK,7376
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[3]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[3]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[3]:Q,7376
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_33:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_29:EN,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_29:IPENn,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_0_a2:A,7003
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_0_a2:B,6955
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_0_a2:C,5034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_0_a2:Y,5034
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[12]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[12]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[12]:C,6495
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[12]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[12]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:CLK,212
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[13]:Q,212
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3_1:A,2934
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3_1:B,6134
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3_1:C,3668
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3_1:D,3564
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3_1:Y,2934
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_21:B,6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_21:IPB,6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_21:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_10:B,7091
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_10:IPB,7091
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[14]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[14]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[14]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[14]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[14]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_5:A,3527
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_5:B,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_5:C,1472
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_5:D,1322
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_5:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:CLK,4886
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D,7382
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:Q,4886
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[5]:CLK,5782
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[5]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[5]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[5]:Q,5782
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:A,6140
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:B,7201
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:IPA,6140
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_6:IPB,7201
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0_a2:A,7010
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0_a2:B,6969
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0_a2:C,6928
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m8_0_a2:Y,6928
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_14:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_10:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_10:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:ALn,8748
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:D,7875
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep:Q,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a4:A,2588
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a4:B,1301
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a4:C,6891
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a4:D,4359
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a4:Y,1301
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_92:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_1:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[0]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[0]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[0]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[0]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_26:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_1[0]:A,6586
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_1[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_1[0]:Y,6586
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:A,5353
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:B,5276
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:C,5224
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:D,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIOQ1G1[13]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[14]:A,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[14]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[14]:C,5545
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[14]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[14]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_269:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_269:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_12:B,6442
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_12:C,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_12:IPB,6442
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_12:IPC,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_25:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_282:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_282:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[27]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[27]:CLK,7204
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[27]:D,6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[27]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[27]:Q,7204
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_21:A,6996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_21:IPA,6996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_21:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIACTB1[27]:A,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIACTB1[27]:B,1707
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR_RNIACTB1[27]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[4]:A,7425
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[4]:B,7341
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[4]:C,6140
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[4]:D,6929
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[4]:Y,6140
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_8:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_3:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_3:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:D,7303
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[4]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_101:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_219:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_219:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_172:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_172:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_25:B,6438
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_25:C,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_25:IPB,6438
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_25:IPC,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_35:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[14]:A,6389
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[14]:B,7528
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[14]:Y,6389
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_1[3]:A,7007
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_1[3]:B,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_1[3]:C,6865
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_1[3]:Y,5944
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[0]:CLK,5276
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[0]:D,3479
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[0]:Q,5276
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_75:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_75:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_57:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_57:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_147:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_147:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[4]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[4]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[4]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[4]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:CLK,167
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:Q,167
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchRdData_0_a3:A,5868
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchRdData_0_a3:B,5824
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchRdData_0_a3:Y,5824
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_18:C,8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_18:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_18:IPC,8839
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[7]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[7]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[7]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[7]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOi_0_sqmuxa_0_a3:A,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOi_0_sqmuxa_0_a3:B,6762
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOi_0_sqmuxa_0_a3:Y,1226
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[31]:A,6443
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[31]:B,7533
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[31]:Y,6443
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[9]:A,7139
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[9]:B,7296
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[9]:Y,7139
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_108:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[4]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[4]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[4]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[4]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[11]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[11]:CLK,7351
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[11]:D,6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[11]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[11]:Q,7351
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_9:B,6394
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_9:C,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_9:IPB,6394
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_9:IPC,8445
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[24]:A,7139
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[24]:B,7291
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[24]:Y,7139
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_24:B,6382
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_24:C,8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_24:IPB,6382
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_24:IPC,8821
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[20]:A,6409
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[20]:B,7535
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[20]:Y,6409
CFG0_GND_INST:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[30]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[30]:CLK,7143
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[30]:D,6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[30]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[30]:Q,7143
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m4:A,7958
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m4:B,7896
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m4:C,7822
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m4:D,4091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m4:Y,4091
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_114:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_114:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_200:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_200:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:CLK,1955
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:D,4387
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[1]:Q,1955
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_245:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_245:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_34:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_203:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_203:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[4]:CLK,7073
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[4]:D,2289
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[4]:Q,7073
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_1:A,4125
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_1:IPA,4125
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[1]:A,7055
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[1]:B,7012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[1]:C,6923
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[1]:D,2362
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[1]:Y,2362
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_284:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_284:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_231:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_231:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_103:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_103:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_33:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_84:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_84:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:A,2365
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:B,1301
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:C,4554
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:D,779
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_RNO:Y,779
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[13]:A,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[13]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[13]:C,5536
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[13]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[13]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_266:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_266:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_17:B,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_17:C,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_17:IPB,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_17:IPC,8773
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_248:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_248:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_185:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_185:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:CLK,5353
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:EN,4411
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:Q,5353
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_inst_1:A,3569
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_inst_1:B,6640
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_inst_1:C,1170
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_inst_1:D,4264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMii_inst_1:Y,1170
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_RXD_PAD/U_IOINFF:A,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MMUART_1_RXD_PAD/U_IOINFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[23]:A,7077
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[23]:B,7227
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[23]:Y,7077
GPIO_OUT_obuf[6]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[6]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[21]:A,7011
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[21]:B,7168
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[21]:Y,7011
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:B,6432
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:C,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:IPB,6432
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_20:IPC,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[5]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[5]:D,6586
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[5]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[5]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[6]:CLK,12
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[6]:D,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[6]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[6]:Q,12
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_9:A,89
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_9:B,12
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_9:C,-33
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_9:D,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_9:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_32:C,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_32:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_32:IPC,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_16:B,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_16:C,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_16:IPB,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_16:IPC,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_29:B,6443
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_29:C,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_29:IPB,6443
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_29:IPC,8726
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_189:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[25]:A,6422
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[25]:B,7511
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[25]:Y,6422
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_64:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_64:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_48:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[10]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[10]:CLK,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[10]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[10]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[10]:Q,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[5]:CLK,8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[5]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[5]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[5]:Q,8607
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_287:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_287:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_202:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_202:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_126:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_126:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOo:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOo:CLK,5610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOo:D,2344
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOo:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMOo:Q,5610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_35:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[3]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[3]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[3]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[3]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[3]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_18:C,8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_18:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_18:IPC,8839
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:CLK,12
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[10]:Q,12
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_26:C,8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_26:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_26:IPC,8767
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[13]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[13]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[13]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[13]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[13]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m1:A,4091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m1:B,4961
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m1:Y,4091
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_132:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_8:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_53:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_53:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[7]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[7]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[7]:C,5521
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[7]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[7]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_97:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20_1_2:A,3873
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20_1_2:B,3638
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20_1_2:C,2803
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20_1_2:D,2530
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20_1_2:Y,2530
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_25:B,6427
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_25:C,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_25:IPB,6427
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_25:IPC,8789
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:CLK,289
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[15]:Q,289
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[3]:A,7458
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[3]:B,7376
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[3]:C,6166
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[3]:D,6964
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[3]:Y,6166
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_8:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_0:B,6238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_0:IPB,6238
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_0:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20:A,1128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20:B,2835
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20:C,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI:CLK,4617
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI:D,7862
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoI:Q,4617
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[9]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[9]:CLK,7296
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[9]:D,6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[9]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[9]:Q,7296
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[8]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[8]:CLK,7325
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[8]:D,6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[8]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[8]:Q,7325
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_140:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_140:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[5]:A,7439
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[5]:B,7355
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[5]:C,6154
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[5]:D,6943
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[5]:Y,6154
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNILAP72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNILAP72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNILAP72[13]:C,6518
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNILAP72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNILAP72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2_i:A,7990
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2_i:B,7906
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2_i:Y,7906
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_28:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_28:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_6:C,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_6:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_6:IPC,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_12:B,6288
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_12:C,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_12:IPB,6288
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_12:IPC,8629
GPIO_OUT_obuf[6]/U0/U_IOENFF:A,
GPIO_OUT_obuf[6]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:CLK,7439
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:D,6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[5]:Q,7439
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[11]:A,6377
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[11]:B,7515
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[11]:Y,6377
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[19]:A,7042
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[19]:B,7199
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[19]:Y,7042
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[17]:A,6409
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[17]:B,7511
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[17]:Y,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[4]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[4]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[4]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[4]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[4]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[12]:A,6408
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[12]:B,7535
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[12]:Y,6408
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[1]:CLK,5742
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[1]:D,1164
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[1]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[1]:Q,5742
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_157:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[7]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[7]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[7]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[7]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[22]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[22]:CLK,6966
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[22]:D,6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[22]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[22]:Q,6966
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_1[0]:A,6393
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_1[0]:B,7545
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_1[0]:Y,6393
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO_0:A,2031
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO_0:B,1989
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO_0:C,1955
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1_RNO_0:Y,1955
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_192:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[20]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[20]:CLK,7208
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[20]:D,6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[20]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[20]:Q,7208
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_59:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_14:A,7042
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_14:IPA,7042
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_105:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_105:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_29:B,6416
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_29:C,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_29:IPB,6416
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_29:IPC,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNIAIIE:A,5860
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNIAIIE:B,6785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/pending_RNIAIIE:Y,5860
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNINCP72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNINCP72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNINCP72[13]:C,6325
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNINCP72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNINCP72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[0]:A,4257
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[0]:B,2878
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[0]:C,4376
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[0]:Y,2878
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:CLK,3132
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:D,5905
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:Q,3132
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[10]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[10]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[10]:C,6407
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[10]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[10]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:CLK,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:D,7508
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[14]:Q,7032
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_184:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_184:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[13]:A,6418
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[13]:B,7545
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[13]:Y,6418
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_109:IPA,
GPIO_OUT_obuf[0]/U0/U_IOENFF:A,
GPIO_OUT_obuf[0]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_34:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_255:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_255:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:CLK,2084
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:D,7500
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:Q,2084
GPIO_OUT_obuf[3]/U0/U_IOPAD:D,
GPIO_OUT_obuf[3]/U0/U_IOPAD:E,
GPIO_OUT_obuf[3]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_72:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_35:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:CLK,7875
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:Q,7875
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_40:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_40:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:CLK,212
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[14]:Q,212
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_17:B,6386
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_17:C,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_17:IPB,6386
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_17:IPC,8773
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_207:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_207:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_10:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[3]:CLK,5804
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[3]:D,1052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[3]:Q,5804
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:D,7385
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[10]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_2:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_2:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_85:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_85:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_4[0]:A,6480
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_4[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_4[0]:Y,6480
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_10:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_1_0_a2:A,4773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_1_0_a2:B,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_1_0_a2:C,6548
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_1_0_a2:D,6447
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_0_sqmuxa_1_0_a2:Y,3736
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_141:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_141:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:A,2168
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:B,944
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:C,2320
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[26]:Y,944
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_258:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_258:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[2]:CLK,167
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[2]:D,4434
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[2]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[2]:Q,167
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[8]:A,6350
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[8]:B,7503
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[8]:Y,6350
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[6]:A,7468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[6]:B,7384
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[6]:C,6183
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[6]:D,6972
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[6]:Y,6183
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_286:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_286:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_12:B,6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_12:C,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_12:IPB,6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_12:IPC,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_27:C,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_27:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_27:IPC,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0_1:A,5708
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0_1:B,5630
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0_1:C,5586
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_0_1:Y,5586
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO_0:A,5044
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO_0:B,5997
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO_0:Y,5044
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_148:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_148:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_32:C,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_32:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_32:IPC,8785
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_93:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_15:C,8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_15:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_15:IPC,8610
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_9:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_65:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_65:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[10]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[10]:B,5485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[10]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[10]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[10]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:D,7484
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[7]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_24:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_24:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_20:A,7049
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_20:IPA,7049
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_20:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_240:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_5:B,6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_5:IPB,6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_5:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:CLK,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:D,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[3]:Q,90
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_176:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_176:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_9:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_243:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_243:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_209:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_209:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_34:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_143:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:CLK,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[3]:Q,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_10:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_16:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_16:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_6:C,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_6:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_6:IPC,8466
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_3:A,5789
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_3:B,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_3:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNI063P:A,3031
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNI063P:B,1707
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNI063P:C,3130
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNI063P:Y,1707
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[0]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[0]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[0]:C,6482
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[0]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[0]:Y,2128
GPIO_OUT_obuf[4]/U0/U_IOENFF:A,
GPIO_OUT_obuf[4]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_1:B,6350
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_1:IPB,6350
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_1:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_150:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_150:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:A,5819
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:B,7139
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPA,5819
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_4:IPB,7139
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_99:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_99:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0_RNI2S2K:A,6083
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0_RNI2S2K:B,4125
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_ss0_RNI2S2K:Y,4125
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_22:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_22:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[22]:A,6809
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[22]:B,6966
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[22]:Y,6809
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_30:C,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_30:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_30:IPC,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_5:EN,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_5:IPENn,9089
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_104:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_104:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:D,7462
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[11]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_a3:A,5382
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_a3:B,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_a3:C,6587
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_a3:D,3392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_a3:Y,2091
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B[0]:A,6591
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B[0]:Y,6591
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[1]:CLK,6447
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[1]:D,4034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[1]:Q,6447
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[1]:A,4251
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[1]:B,2885
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[1]:C,4363
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHSIZE[1]:Y,2885
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_242:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_242:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_7:C,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_7:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_7:IPC,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_1:A,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_1:B,5824
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_1:C,4302
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_1:D,4208
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_1:Y,4208
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_32:C,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_32:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_32:IPC,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_28:B,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_28:C,8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_28:IPB,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_28:IPC,8769
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_15:A,7051
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_15:B,7047
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_15:IPA,7051
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_15:IPB,7047
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWRITE:A,1273
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWRITE:B,4327
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWRITE:Y,1273
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_7:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_4[0]:A,6232
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_4[0]:B,7523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_4[0]:Y,6232
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_0:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_0:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[2]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[2]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[2]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[2]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_35:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[27]:A,7047
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[27]:B,7204
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[27]:Y,7047
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_206:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_206:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[1]:CLK,7889
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[1]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[1]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[1]:Q,7889
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[14]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[14]:CLK,7264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[14]:D,6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[14]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[14]:Q,7264
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_2:A,6166
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_2:IPA,6166
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_11:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1:An,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0_RGB1:YL,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_9:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_7:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_77:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_77:IPB,
GPIO_OUT_obuf[1]/U0/U_IOENFF:A,
GPIO_OUT_obuf[1]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_127:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_127:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[7]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[7]:D,6591
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[7]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[7]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:CLK,2320
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:D,7447
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:Q,2320
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_30:C,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_30:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_30:IPC,8790
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_151:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_151:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_34:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_244:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_244:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_27:C,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_27:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_27:IPC,8716
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[15]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[15]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[15]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[15]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[15]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_136:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_136:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[9]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[9]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[9]:C,6493
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[9]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[9]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMiI:A,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMiI:B,4730
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMiI:Y,3736
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[25]:A,7049
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[25]:B,7206
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[25]:Y,7049
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_3:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_3:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[29]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[29]:CLK,7146
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[29]:D,6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[29]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[29]:Q,7146
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNIKT9C1[0]:A,6884
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNIKT9C1[0]:B,6794
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNIKT9C1[0]:C,6750
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNIKT9C1[0]:D,4224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_RNIKT9C1[0]:Y,4224
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32:A,6852
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32:B,6809
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32:C,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32:D,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32:Y,5641
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_q1:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select:ALn,8748
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select:EN,7852
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_145:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[2]:CLK,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[2]:D,7816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[2]:Q,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_26:C,8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_26:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_26:IPC,8767
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:CLK,7153
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:D,7478
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[1]:Q,7153
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_25:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_158:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL:A,89
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL:B,12
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL:C,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL:D,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_225:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_225:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_32:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_32:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[0]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[0]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[0]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[0]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[0]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[1]:A,7400
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[1]:B,7316
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[1]:C,6113
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[1]:D,6904
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[1]:Y,6113
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_149:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_149:IPB,
GPIO_OUT_obuf[5]/U0/U_IOPAD:D,
GPIO_OUT_obuf[5]/U0/U_IOPAD:E,
GPIO_OUT_obuf[5]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_82:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_250:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_250:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[0]:CLK,7451
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[0]:D,6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[0]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[0]:Q,7451
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[18]:A,6891
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[18]:B,7048
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[18]:Y,6891
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_9:B,6429
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_9:C,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_9:IPB,6429
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_9:IPC,8445
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:CLK,89
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[8]:Q,89
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_253:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_44:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_44:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_228:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_247:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_247:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_153:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_153:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_1:B,6380
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_1:IPB,6380
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_1:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_28:B,6448
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_28:C,8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_28:IPB,6448
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_28:IPC,8769
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_1:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_1:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_196:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_196:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2:A,2850
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2:B,2803
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0_a2_0_2:Y,2803
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState_ns_0_a3_0_a3[0]:A,7964
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState_ns_0_a3_0_a3[0]:B,7870
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState_ns_0_a3_0_a3[0]:C,1256
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState_ns_0_a3_0_a3[0]:Y,1256
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H[0]:A,6388
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H[0]:B,7533
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H[0]:Y,6388
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_7:A,212
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_7:B,135
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_7:C,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_7:D,12
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_7:Y,12
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[14]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[14]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[14]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[14]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[14]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_261:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_261:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIK9P72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIK9P72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIK9P72[13]:C,6500
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIK9P72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIK9P72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_RGB1:An,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0_RGB1:YL,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_m3:A,3723
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_m3:B,5494
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_m3:C,2982
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_m3:D,2878
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOIs2_m3:Y,2878
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_62:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_q1:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_q1:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_q1:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_29:EN,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_29:IPENn,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_4:B,6275
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_4:IPB,6275
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_4:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_18:C,8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_18:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_18:IPC,8839
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_211:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_211:IPB,
GPIO_OUT_obuf[2]/U0/U_IOPAD:D,
GPIO_OUT_obuf[2]/U0/U_IOPAD:E,
GPIO_OUT_obuf[2]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_22:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_22:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[10],8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[11],8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[12],8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[13],8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[3],8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[4],8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[5],8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[6],8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[7],8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[8],8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[9],8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ARST_N,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_CLK,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[0],6357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[1],6379
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[2],6415
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[3],6388
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[4],6419
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[5],6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[6],6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[7],6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[0],6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[1],6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[2],6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[3],6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[4],6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[5],6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[6],6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[7],6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0],761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[10],8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[11],8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[12],8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[13],8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[3],8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[4],8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[5],8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[6],8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[7],8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[8],8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[9],8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ARST_N,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[0],6350
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[1],6368
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[2],6404
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[3],6377
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[4],6408
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[5],6418
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[6],6389
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[7],6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2[1]:A,6867
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2[1]:B,6824
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2[1]:C,6735
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2[1]:D,2200
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2[1]:Y,2200
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_24:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0:A,6960
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0:B,6979
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0:C,1157
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0:D,4224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0:Y,1157
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_252:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_11:IPB,
GPIO_OUT_obuf[3]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[3]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[5].APB_32.GPOUT_reg[5]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0_RNO[4]:A,7013
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0_RNO[4]:B,5968
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0_RNO[4]:C,6895
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0_RNO[4]:Y,5968
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[0]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[0]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[0]:C,5497
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[0]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[0]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_73:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[25]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[25]:CLK,7206
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[25]:D,6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[25]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[25]:Q,7206
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:D,7471
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[9]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_249:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_249:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL:CLK,5749
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL:D,2190
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL:Q,5749
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_17:B,6408
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_17:C,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_17:IPB,6408
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_17:IPC,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[3]:A,7677
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[3]:B,7573
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[3]:C,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[3]:D,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[3]:Y,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m5:A,4034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m5:B,4961
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m5:Y,4034
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:CLK,5651
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:EN,4348
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:Q,5651
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_120:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[12]:CLK,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[12]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[12]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[12]:Q,8785
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HWRITE:A,2318
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HWRITE:B,5467
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HWRITE:Y,2318
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_32:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[11]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[11]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[11]:C,6484
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[11]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[11]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[0]:CLK,6548
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[0]:D,4091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI[0]:Q,6548
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[2]:A,5523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[2]:B,5493
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[2]:C,5453
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[2]:D,4434
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[2]:Y,4434
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_162:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_162:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_177:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_177:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_56:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_56:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_27:C,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_27:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_27:IPC,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_3:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_3:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_20:B,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_20:C,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_20:IPB,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_20:IPC,761
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_144:A,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_144:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_0:B,6357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_0:IPB,6357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_0:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK,8748
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q,8748
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_12:B,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_12:C,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_12:IPB,6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_12:IPC,8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0[4]:A,2289
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0[4]:B,5968
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0[4]:C,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_0[4]:Y,2289
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[0]:A,2357
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[0]:B,5438
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HSIZE[0]:Y,2357
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[1]:A,7153
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[1]:B,6832
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[1]:C,5643
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[1]:D,1232
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[1]:Y,1232
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_112:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_112:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_79:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_79:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_51:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_51:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_254:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_254:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_12:A,6962
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_12:IPA,6962
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_11:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_7:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_7:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:CLK,90
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:D,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[11]:Q,90
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_10:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS_1[0]:A,5834
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS_1[0]:B,5749
SmartFusion2_FIC_Tutorial_sb_0/CoreAPB3_0/iPSELS_1[0]:Y,5749
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[6]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[6]:D,6587
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[6]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[6]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_22:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_22:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_8:B,6243
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_8:C,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_8:IPB,6243
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_8:IPC,8495
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_155:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_1:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_14:C,8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_14:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_14:IPC,8607
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_275:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_275:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[13]:CLK,7224
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[13]:D,6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[13]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[13]:Q,7224
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_246:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_246:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_25:B,6374
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_25:C,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_25:IPB,6374
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_25:IPC,8789
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_37:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_19:C,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_19:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_19:IPC,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[0]:A,7685
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[0]:B,7615
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[0]:C,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[0]:D,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[0]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[31]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[31]:CLK,7253
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[31]:D,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[31]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[31]:Q,7253
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[26]:A,6429
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[26]:B,7523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[26]:Y,6429
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_31:C,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_31:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_31:IPC,8766
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_87:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_87:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_159:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_159:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[7]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[7]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[7]:C,6506
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[7]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[7]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3_1:A,4566
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3_1:B,3491
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3_1:C,5679
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3_1:D,779
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3_1:Y,779
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[0]:CLK,2144
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[0]:D,1170
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_Z[0]:Q,2144
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_121:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIPEP72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIPEP72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIPEP72[13]:C,6421
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIPEP72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIPEP72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:A,4711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:B,5543
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:C,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:D,2885
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_ss3_0:Y,875
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_278:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_278:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_45:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_45:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO:A,6941
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO:B,5044
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO:C,6796
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO:D,6739
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_RNO:Y,5044
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_257:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_257:IPB,
GPIO_OUT_obuf[7]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[7]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_6:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_20:B,6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_20:C,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_20:IPB,6422
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_20:IPC,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_14:C,8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_14:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_14:IPC,8607
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIMBP72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIMBP72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIMBP72[13]:C,6485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIMBP72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIMBP72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_5:EN,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_5:IPENn,9089
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_128:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_128:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_67:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_67:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[0]:CLK,7367
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[0]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[0]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[0]:Q,7367
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_2:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_2:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/un1_m5_i_o4:A,3592
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/un1_m5_i_o4:B,6885
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/un1_m5_i_o4:C,1157
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/un1_m5_i_o4:D,4287
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/un1_m5_i_o4:Y,1157
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_281:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_281:IPB,
SmartFusion2_FIC_Tutorial_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_220:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_220:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0:An,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNI9DDB/U0:YWn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_32:C,8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_32:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_32:IPC,8785
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_223:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_223:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/N_49_i_1:A,2800
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/N_49_i_1:B,6058
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/N_49_i_1:C,3605
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/N_49_i_1:D,3443
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/N_49_i_1:Y,2800
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[12]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[12]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[12]:C,5510
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[12]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[12]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_a3_0[3]:A,7103
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_a3_0[3]:B,7073
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns_i_a3_0[3]:Y,7073
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[6]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[6]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[6]:C,5436
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[6]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[6]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_123:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_123:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_31:C,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_31:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_31:IPC,8766
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_25:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i:A,3592
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i:B,5860
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i:C,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i:D,4226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_1_sqmuxa_i:Y,2052
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg[0]:CLK,2031
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg[0]:D,3168
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg[0]:EN,8745
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg[0]:Q,2031
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3:A,779
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3:B,4415
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3:C,2312
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3:D,3338
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_1_3:Y,779
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_30:C,8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_30:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_30:IPC,8790
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:CLK,89
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:D,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:EN,5468
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[7]:Q,89
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_137:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_137:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[16]:A,7111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[16]:B,7268
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[16]:Y,7111
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_259:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_259:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_96:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_30:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[10]:A,7207
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[10]:B,7357
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[10]:Y,7207
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_34:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_170:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_0[0]:A,6374
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_0[0]:B,7528
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_0[0]:Y,6374
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_91:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_0:B,6387
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_0:IPB,6387
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_0:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_24:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_24:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:D,7463
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[3]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[18]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[18]:CLK,7048
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[18]:D,6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[18]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[18]:Q,7048
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:D,7473
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[12]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[5]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[5]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[5]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[5]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[5]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[5]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[5]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[5]:C,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[5]:D,5299
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[5]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[30]:A,6438
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[30]:B,7528
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[30]:Y,6438
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_222:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_222:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_6:C,8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_6:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_6:IPC,8466
GPIO_OUT_obuf[3]/U0/U_IOENFF:A,
GPIO_OUT_obuf[3]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_235:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_235:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_154:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_33:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_33:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[18]:A,6394
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[18]:B,7523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[18]:Y,6394
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_182:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_34:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[9]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[9]:CLK,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[9]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[9]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[9]:Q,8716
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_58:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_197:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_197:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[13]:CLK,5834
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[13]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[13]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[13]:Q,5834
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_17:A,6809
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_17:B,6989
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_17:IPA,6809
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_17:IPB,6989
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[7]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[7]:B,5487
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[7]:C,4575
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[7]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[7]:Y,4575
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_83:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_1_sqmuxa_0_a2:A,5092
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_1_sqmuxa_0_a2:B,5034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMIII_1_sqmuxa_0_a2:Y,5034
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[19]:A,6398
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[19]:B,7515
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[19]:Y,6398
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[2]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[2]:D,6480
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[2]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[2]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_a3_0_0:A,7036
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_a3_0_0:B,6979
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_a3_0_0:Y,6979
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[6]:CLK,8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[6]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[6]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[6]:Q,8773
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:CLK,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:D,7499
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[13]:Q,7032
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_25:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_238:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_238:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[21]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[21]:CLK,7168
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[21]:D,6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[21]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[21]:Q,7168
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0:A,6972
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0:B,6896
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0:C,1366
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0:D,1170
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMoo_ns_1_0_.m4_0:Y,1170
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:D,7399
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[6]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMi:A,5720
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMi:B,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMi:C,5610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMi:Y,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[16]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[16]:CLK,7268
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[16]:D,6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[16]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[16]:Q,7268
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_256:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_256:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[15]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[15]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[15]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[15]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[15]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHWRITE:A,4774
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHWRITE:B,3443
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHWRITE:C,4886
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/GATEDHWRITE:Y,3443
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_201:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_201:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[8]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[8]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[8]:C,6426
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[8]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HADDR[8]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:CLK,7458
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:D,6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[3]:Q,7458
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_63:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_63:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK,7919
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_clk_base:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/RESET_N_M2F_clk_base:Q,7919
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_39:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_39:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0:A,6011
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0:B,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/clrPenable_0:Y,5944
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_224:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_224:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_2:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_2:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[2]:A,7111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[2]:B,7034
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[2]:C,5819
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[2]:D,6622
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4[2]:Y,5819
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_89:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_89:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:CLK0,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:CLK1,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:CLK2,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:CLK3,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GPD0_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GPD1_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GPD2_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GPD3_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:LOCK,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_HOLD_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX0_SEL,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_HOLD_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX1_SEL,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_HOLD_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX2_SEL,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_HOLD_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:NGMUX3_SEL,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[3],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[4],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[5],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[6],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PADDR[7],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PCLK,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PENABLE,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_BYPASS_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PLL_POWERDOWN_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PRESET_N,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PSEL,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[0],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[1],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[2],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[3],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[4],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[5],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[6],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWDATA[7],
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:PWRITE,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/INST_CCC_IP:RCOSC_25_50MHZ,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_13:B,6377
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_13:C,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_13:IPB,6377
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_13:IPC,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[3]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[3]:D,6504
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[3]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[3]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[6]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[6]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[6]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[6]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[6]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[24]:A,6392
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[24]:B,7503
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[24]:Y,6392
GPIO_OUT_obuf[0]/U0/U_IOPAD:D,
GPIO_OUT_obuf[0]/U0/U_IOPAD:E,
GPIO_OUT_obuf[0]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_125:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_125:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_178:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3:A,2934
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3:B,1391
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3:C,6992
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3:D,5893
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/HREADYOUT_4_3:Y,1391
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNIKU7U:A,4884
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNIKU7U:B,3605
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNIKU7U:C,5023
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNIKU7U:D,4888
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_RNIKU7U:Y,3605
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[27]:A,2156
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[27]:B,976
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[27]:C,2308
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[27]:Y,976
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:CLK,5522
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:D,2362
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:Q,5522
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_29:EN,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_29:IPENn,9127
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[29]:A,6989
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[29]:B,7146
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[29]:Y,6989
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_13:B,6398
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_13:C,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_13:IPB,6398
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_13:IPC,8627
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[5]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[5]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[5]:C,5525
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[5]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[5]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_13:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_13:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1:A,1758
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1:B,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1:C,1955
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20_m1:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[1]:CLK,4363
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[1]:D,7295
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[1]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHSIZE[1]:Q,4363
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_11:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_28:B,6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_28:C,8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_28:IPB,6393
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_28:IPC,8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[2]:CLK,7111
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[2]:D,6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[2]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[2]:Q,7111
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_130:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_129:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_129:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_270:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_270:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_13:B,6431
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_13:C,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_13:IPB,6431
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_13:IPC,8627
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_166:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[2]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[2]:CLK,6852
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[2]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[2]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[2]:Q,6852
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_69:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_69:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_273:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_273:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20:A,3698
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20:B,2530
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20:C,4722
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20:D,2513
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREVDATASLAVEREADY_20:Y,2513
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[12]:CLK,6774
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[12]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[12]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[12]:Q,6774
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_42:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_42:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[3]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[3]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[3]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[3]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[3]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_227:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_227:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_173:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_173:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_31:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_8:A,289
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_8:B,212
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_8:C,167
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_8:D,89
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/DEFSLAVEDATASEL_8:Y,89
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_116:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_116:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_21:B,6418
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_21:IPB,6418
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_21:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m8:A,7958
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m8:B,7896
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m8:C,7822
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m8:D,4034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiOI_ns_1_0_.m8:Y,4034
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_102:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_102:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[4]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[4]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[4]:C,5340
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[4]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[4]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[1]:A,1232
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[1]:B,1164
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[1]:C,7889
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[1]:Y,1164
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_50:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_27:C,8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_27:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_27:IPC,8716
GPIO_OUT_obuf[1]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[1]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:CLK,7316
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[1]:Q,7316
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[10]:A,6404
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[10]:B,7523
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[10]:Y,6404
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_98:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_13:A,6891
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_13:IPA,6891
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[6]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[6]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[6]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[6]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[12]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[12]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[12]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[12]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState:A,1128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState:B,3132
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState:Y,1128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_2:A,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_2:B,5905
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_2:Y,5018
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_1:B,6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_1:IPB,6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_1:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[8]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[8]:CLK,8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[8]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[8]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[8]:Q,8789
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[3]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[3]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[3]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[3]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_13:B,6277
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_13:C,8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_13:IPB,6277
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_13:IPC,8627
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[2]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[2]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[2]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[2]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_272:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_272:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_22:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_4:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_4:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[17]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[17]:CLK,7119
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[17]:D,6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[17]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[17]:Q,7119
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_22:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_22:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_5[0]:A,6502
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_5[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_5[0]:Y,6502
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_33:C,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_33:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_33:IPC,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[1]:A,7677
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[1]:B,7615
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[1]:C,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[1]:D,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI[1]:Y,761
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[30]:A,6986
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[30]:B,7143
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[30]:Y,6986
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_229:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_4:B,6379
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_4:IPB,6379
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_4:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[6]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[6]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[6]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[6]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_21:B,6430
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_21:IPB,6430
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_21:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_131:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[7]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[7]:CLK,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[7]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[7]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[7]:Q,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_20:B,6395
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_20:C,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_20:IPB,6395
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_20:IPC,761
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[1]:CLK,6785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[1]:D,1157
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState[1]:Q,6785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[6]:CLK,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[6]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[6]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[6]:Q,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_33:C,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_33:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_33:IPC,8816
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_19:A,7139
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_19:B,7096
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_19:IPA,7139
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_19:IPB,7096
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_31:C,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_31:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_31:IPC,8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_5:B,6264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_5:IPB,6264
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_5:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_0:A,2691
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_0:B,3903
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_0:Y,2691
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[15]:A,6392
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[15]:B,7533
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[15]:Y,6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_33:C,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_33:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_33:IPC,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_10:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[13]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[13]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[13]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[13]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[13]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_24:B,6446
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_24:C,8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_24:IPB,6446
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_24:IPC,8821
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CAN_RXBUS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CAN_TXBUS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CAN_TX_EBL_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE,761
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_MDDR_APB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:COLF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CONFIG_PRESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CRSF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2HCALIB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[11],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[12],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[13],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[14],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[15],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2H_INTERRUPT[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2_DMAREADY[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F2_DMAREADY[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_AVALID,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_HOSTDISCON,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_IDDIG,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_LINESTATE[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_LINESTATE[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_M3_RESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_PLL_LOCK,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_RXACTIVE,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_RXERROR,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_RXVALID,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_RXVALIDH,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_SESSEND,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_TXREADY,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VBUSVALID,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_VSTATUS[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FAB_XDATAIN[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FPGA_MDDR_ARESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:FPGA_RESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[11],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[12],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[13],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[14],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[15],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[16],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[17],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[18],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[19],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[20],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[21],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[22],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[23],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[24],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[25],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[26],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[27],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[28],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[29],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[30],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[31],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARBURST_HTRANS1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARBURST_HTRANS1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARID_HSEL1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARID_HSEL1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARID_HSEL1[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARID_HSEL1[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLEN_HBURST1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLEN_HBURST1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLEN_HBURST1[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLEN_HBURST1[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLOCK_HMASTLOCK1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARLOCK_HMASTLOCK1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARSIZE_HSIZE1[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARSIZE_HSIZE1[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARVALID_HWRITE1,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[11],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[12],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[13],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[14],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[15],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[16],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[17],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[18],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[19],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[20],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[21],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[22],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[23],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[24],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[25],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[26],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[27],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[28],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[29],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[30],
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWADDR_HADDR0[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWBURST_HTRANS0[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWBURST_HTRANS0[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWID_HSEL0[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWID_HSEL0[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWID_HSEL0[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWID_HSEL0[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLEN_HBURST0[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLEN_HBURST0[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLEN_HBURST0[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLEN_HBURST0[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLOCK_HMASTLOCK0[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWLOCK_HMASTLOCK0[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[0],
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_WDATA[8],6350
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_RMW_AXI,
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[20],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[21],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[22],
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[43],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[44],
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SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[59],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[60],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[61],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[62],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[63],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WDATA_HWDATA01[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WID_HREADY01[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WID_HREADY01[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WID_HREADY01[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WID_HREADY01[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WLAST,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WVALID,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:GTX_CLKPF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C0_BCLK,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C0_SCL_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C0_SDA_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C1_BCLK,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C1_SCL_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C1_SDA_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PENABLE,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PSEL,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[11],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[12],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[13],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[14],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[15],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWRITE,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDIF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO0A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO11A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO11B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO12A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO13A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO14A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO15A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO16A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO17B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO18B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO19B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO1A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO20B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO21B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO22B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO24B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO25B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO26B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO27B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO28B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO29B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO2A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO30B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO31B_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO3A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO4A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO5A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO6A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO7A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO8A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO9A_F2H_GPIN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_CTS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_DCD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_DSR_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_DTR_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_RI_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_RTS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_RXD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_SCK_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART0_TXD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_CTS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_DCD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_DSR_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_RI_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_RTS_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_RXD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_SCK_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[10],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[11],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[12],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[13],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[14],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[15],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[16],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[17],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[18],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[19],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[20],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[21],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[22],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[23],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[24],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[25],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[26],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[27],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[28],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[29],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[30],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[31],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PRDATA[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PREADY,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PSLVERR,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PRESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[8],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RCGF[9],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[0],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[1],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[2],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[3],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[4],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[5],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[6],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RXDF[7],
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_CLKPF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_DVF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_ERRF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:RX_EV,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SLEEPHOLDREQ,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SMBALERT_NI0,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SMBALERT_NI1,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SMBSUS_NI0,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SMBSUS_NI1,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_CLK_IN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDI_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SDO_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SS0_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SS1_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SS2_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SS3_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_CLK_IN,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SDI_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SDO_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SS0_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SS1_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SS2_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI1_SS3_F2H_SCP,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:TX_CLKPF,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_GPIO_RESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:XCLK_FAB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_76:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_76:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_29:B,6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_29:C,8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_29:IPB,6392
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_29:IPC,8726
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_138:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_138:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0:An,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/GL0_INST/U0:YWn,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_11:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_11:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_10:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_6:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CCC_0/CCC_INST/IP_INTERFACE_6:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_124:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_124:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:A,6166
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:B,7207
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPA,6166
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_5:IPB,7207
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_71:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0:A,5841
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0:B,5804
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/setPenable_i_0:Y,5804
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_274:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_274:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[1]:A,3527
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[1]:B,2362
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[1]:C,7869
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[1]:D,7752
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[1]:Y,2362
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[3]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[3]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[3]:C,5500
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[3]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[3]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_230:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_230:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_233:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_233:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[7]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[7]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[7]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[7]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[7]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[0]:CLK,5574
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[0]:D,3453
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[0]:Q,5574
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[21]:A,6430
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[21]:B,7545
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[21]:Y,6430
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_4:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_4:B,7919
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_4:C,7875
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/MSS_HPMS_READY_int_4:Y,7875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_24:B,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_24:C,8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_24:IPB,6397
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_24:IPC,8821
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[27]:A,6431
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[27]:B,7515
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[27]:Y,6431
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_133:IPA,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[0]:CLK,7882
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[0]:D,1256
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/penableSchedulerState[0]:Q,7882
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[22]:A,6427
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[22]:B,7528
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[22]:Y,6427
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2_0[0]:A,7096
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2_0[0]:B,7060
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2_0[0]:Y,7060
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_33:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_3:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_3:IPC,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2[2]:A,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2[2]:B,1028
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2[2]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[10],8767
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[11],8769
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[12],8790
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[13],8785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[3],8466
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[4],8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[5],8629
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[6],8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[7],8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[8],8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ADDR[9],8821
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_ARST_N,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_CLK,6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[0],6387
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[1],6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[2],6405
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[3],6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[4],6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[5],6432
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[6],6435
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[7],6421
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[0],6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[1],6673
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[2],6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[3],6711
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[4],6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[5],6686
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[6],6662
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT[7],6650
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[0],875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:A_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[10],8716
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[11],8726
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[12],8766
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[13],8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[3],8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[4],8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[5],8627
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[6],8610
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[7],8773
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[8],8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ADDR[9],8789
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_ARST_N,9127
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_BLK[2],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[0],6380
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[10],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[11],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[12],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[13],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[14],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[15],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[16],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[17],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[1],6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[2],6394
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[3],6398
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[4],6409
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[5],6430
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[6],6427
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[7],6416
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[8],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DIN[9],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_ARST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_EN,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_DOUT_SRST_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[0],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/INST_RAM1K18_IP:B_WEN[1],
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_33:C,8816
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_33:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_33:IPC,8816
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_226:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_226:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_90:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_90:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_7:C,8479
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_7:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_7:IPC,8479
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2_0[0]:A,6880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2_0[0]:B,6844
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_ns_i_a2_0[0]:Y,6844
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_179:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[25]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[25]:CLK,2172
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[25]:D,7473
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[25]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[25]:Q,2172
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3_0_a3:A,5436
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3_0_a3:B,2939
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3_0_a3:C,2885
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3_0_a3:Y,2885
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_2[0]:A,6386
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_2[0]:B,7535
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/masterDataInProg_RNI1Q6H_2[0]:Y,6386
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_47:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_18:C,8839
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_18:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_18:IPC,8839
GPIO_OUT_obuf[1]/U0/U_IOPAD:D,
GPIO_OUT_obuf[1]/U0/U_IOPAD:E,
GPIO_OUT_obuf[1]/U0/U_IOPAD:PAD,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_277:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_277:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_241:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiII:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiII:CLK,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiII:D,5034
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMiII:Q,8590
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[14]:A,7108
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[14]:B,7264
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[14]:Y,7108
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_8:B,6415
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_8:C,8495
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_8:IPB,6415
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_8:IPC,8495
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_186:IPA,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[23]:A,6416
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[23]:B,7533
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/HWDATA[23]:Y,6416
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_16:B,6419
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_16:C,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_16:IPB,6419
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_16:IPC,8812
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[15]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[15]:CLK,6649
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[15]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[15]:EN,2052
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg[15]:Q,6649
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_19:C,8793
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_19:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_19:IPC,8793
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_232:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_232:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_o2:A,6785
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_o2:B,6776
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_o2:C,6683
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_o2:D,6587
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/latchNextAddr_0_o2:Y,6587
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_193:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:CLK,5436
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:EN,1226
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMlI/CHTOLSRAMo1[1]:Q,5436
SmartFusion2_FIC_Tutorial_sb_0/SYSRESET_POR/INST_SYSRESET_IP:DEVRST_N,
SmartFusion2_FIC_Tutorial_sb_0/SYSRESET_POR/INST_SYSRESET_IP:POWER_ON_RESET_N,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/FF_35:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_24:CLK,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_24:IPCLKn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_5:EN,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_5:IPENn,9089
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_o3_0:A,6941
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_o3_0:B,6870
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_o3_0:C,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_m7_0_o3_0:Y,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:CLK,7425
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:D,6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[4]:Q,7425
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[2]:A,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[2]:B,6704
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[2]:C,5533
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[2]:D,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/HADDR[2]:Y,1104
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_6[0]:A,6480
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_6[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_6[0]:Y,6480
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_4:B,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_4:IPB,6420
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_4:IPC,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[1]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[1]:CLK,8867
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[1]:D,6502
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[1]:EN,8719
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/hwdataReg[1]:Q,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[13]:A,7071
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[13]:B,7224
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[13]:Y,7071
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[11]:A,7201
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[11]:B,7351
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[11]:Y,7201
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_27:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_27:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[4].APB_32.GPOUT_reg[4]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_0:A,5998
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_0:B,5942
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_0:C,6868
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/PSEL_RNO_0:Y,5942
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:A,7685
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:B,7573
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:C,3736
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:D,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMoOI_m3[2]:Y,875
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[5]:CLK,7355
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[5]:D,5746
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[5]:EN,7753
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/HRDATA[5]:Q,7355
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_1:A,3572
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_1:B,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_1:C,1138
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2_2_1:Y,-111
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_6:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_279:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_279:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:CLK,7025
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:D,7488
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR_Z[5]:Q,7025
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/FF_32:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:CLK,3130
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:EN,-111
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS:Q,3130
GPIO_OUT_obuf[0]/U0/U_IOOUTFF:A,
GPIO_OUT_obuf[0]/U0/U_IOOUTFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[11]:A,5584
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[11]:B,5485
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[11]:C,4556
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[11]:D,5381
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_0_a2[11]:Y,4556
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/FF_11:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[0]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[0]:CLK,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[0]:D,2082
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[0]:EN,2091
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/nextHaddrReg[0]:Q,8017
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIODP72[13]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIODP72[13]:B,7689
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIODP72[13]:C,6510
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIODP72[13]:D,2128
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIODP72[13]:Y,2128
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:A,6130
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:B,7108
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:IPA,6130
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:IPB,7108
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_234:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_234:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_142:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[12]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[12]:CLK,7340
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[12]:D,6705
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[12]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[12]:Q,7340
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_54:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_54:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/nextPenableSchedulerState_0_0[1]:A,7964
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/nextPenableSchedulerState_0_0[1]:B,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/nextPenableSchedulerState_0_0[1]:C,7882
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_PenableScheduler/nextPenableSchedulerState_0_0[1]:Y,5944
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[14]:A,8017
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[14]:B,6819
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[14]:C,1104
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[14]:D,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_ApbAddrData/haddrReg_5[14]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_11:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[10]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[10]:CLK,7357
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[10]:D,6704
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[10]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[10]:Q,7357
GPIO_OUT_obuf[5]/U0/U_IOENFF:A,
GPIO_OUT_obuf[5]/U0/U_IOENFF:Y,
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:CLK,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:D,8867
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:EN,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[6].APB_32.GPOUT_reg[6]:Q,8010
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns[0]:A,6110
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns[0]:B,1164
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns[0]:C,7842
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns[0]:D,6743
SmartFusion2_FIC_Tutorial_sb_0/COREAHBTOAPB3_0/U_AhbToApbSM/ahbToApbSMState_ns[0]:Y,1164
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_9:B,6232
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_9:C,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_9:IPB,6232
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIoI/CHTOLSRAMo0i/CFG_9:IPC,8445
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[24]:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[24]:CLK,7291
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[24]:D,6659
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[24]:EN,8590
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOI[24]:Q,7291
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_135:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_135:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[28]:A,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[28]:B,7189
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HRDATA_4_0[28]:Y,7032
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[0]:A,7060
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[0]:B,3453
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[0]:C,7876
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[0]:D,7688
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState_RNO[0]:Y,3453
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2_RNICF151[2]:A,2082
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2_RNICF151[2]:B,2055
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2_RNICF151[2]:C,1960
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2_RNICF151[2]:D,996
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL_2_i_o2_RNICF151[2]:Y,996
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_167:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[1]:A,8010
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[1]:B,6012
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[1]:C,5746
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/CoreAPB3_0_APBmslave0_PRDATA_m_cZ[1]:Y,5746
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_174:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_174:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_14:C,8607
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_14:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/CFG_14:IPC,8607
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_78:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_78:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select4:A,7922
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select4:B,7852
SmartFusion2_FIC_Tutorial_sb_0/CORERESETP_0/mss_ready_select4:Y,7852
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_117:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_117:IPB,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_139:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_139:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_0[0]:A,6587
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_0[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_0[0]:Y,6587
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a0_0:A,3572
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a0_0:B,4945
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/d_masterRegAddrSel_i_a0_0:Y,3572
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_4:A,5859
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_4:B,5782
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_4:C,5742
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_4:D,5641
SmartFusion2_FIC_Tutorial_sb_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg32_4:Y,5641
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMlOl/CHTOLSRAMo0i/FF_8:IPENn,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_0:B,6399
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_0:IPB,6399
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMoOl/CHTOLSRAMo0i/CFG_0:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_106:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_23:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/genblk1.CHTOLSRAMIOl/CHTOLSRAMo0i/CFG_23:IPC,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_43:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_43:IPB,
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOlI:ALn,7051
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOlI:CLK,7920
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOlI:D,5968
SmartFusion2_FIC_Tutorial_sb_0/COREAHBLSRAM_0_0/CHTOLSRAMOl/CHTOLSRAMOlI:Q,7920
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_3[0]:A,6504
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_3[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_3[0]:Y,6504
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_237:IPA,
SmartFusion2_FIC_Tutorial_sb_0/SmartFusion2_FIC_Tutorial_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_237:IPB,
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20s2:A,2530
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20s2:B,2640
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_pre_20s2:Y,2530
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_2[0]:A,6581
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_2[0]:B,7880
SmartFusion2_FIC_Tutorial_sb_0/CoreAHBLite_0/matrix4x16/slavestage_1/masterDataInProg_RNI2E5B_2[0]:Y,6581
GPIO_OUT[7],
GPIO_OUT[6],
GPIO_OUT[5],
GPIO_OUT[4],
GPIO_OUT[3],
GPIO_OUT[2],
GPIO_OUT[1],
GPIO_OUT[0],
DEVRST_N,
MMUART_1_RXD,
MMUART_1_TXD,
