#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\synthesis\run_options.txt
#--  Written on Thu Apr 29 10:00:39 2021


#project files
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/CCC_0/SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/FABOSC_0/SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb_MSS/SmartFusion2_FIC_Tutorial_sb_MSS_syn.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb_MSS/SmartFusion2_FIC_Tutorial_sb_MSS.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vlog/core/coregpio.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core/coreahbtoapb3.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog -lib COREAHBLSRAM_OBF_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/Actel/DirectCore/COREAHBLSRAM/2.0.113/rtl/vlog/core_obfuscated/AHBLSramIf.v"
add_file -verilog -lib COREAHBLSRAM_OBF_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/COREAHBLSRAM_0_0/rtl/vlog/core_obfuscated/lsram_2048to139264x8.v"
add_file -verilog -lib COREAHBLSRAM_OBF_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/COREAHBLSRAM_0_0/rtl/vlog/core_obfuscated/usram_128to9216x8.v"
add_file -verilog -lib COREAHBLSRAM_OBF_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/COREAHBLSRAM_0_0/rtl/vlog/core_obfuscated/SramCtrlIf.v"
add_file -verilog -lib COREAHBLSRAM_OBF_LIB "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/COREAHBLSRAM_0_0/rtl/vlog/core_obfuscated/CoreAHBLSRAM.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/SmartFusion2_FIC_Tutorial_sb/SmartFusion2_FIC_Tutorial_sb.v"
add_file -verilog "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/igloo2_task_feb_2021/SF2/TU0310_SF2_FIC/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip SmartFusion2
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
