set_device -family {SmartFusion2} -die {M2S090TS} -speed {-1}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\CCC_0\SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\FABOSC_0\SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb_MSS\SmartFusion2_FIC_Tutorial_sb_MSS.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core\coregpio.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_ahbtoapbsm.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_apbaddrdata.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_penablescheduler.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v}
read_verilog -mode system_verilog -lib COREAHBLSRAM_OBF_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core_obfuscated\AHBLSramIf.v}
read_verilog -mode system_verilog -lib COREAHBLSRAM_OBF_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\lsram_2048to139264x8.v}
read_verilog -mode system_verilog -lib COREAHBLSRAM_OBF_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\usram_128to9216x8.v}
read_verilog -mode system_verilog -lib COREAHBLSRAM_OBF_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\SramCtrlIf.v}
read_verilog -mode system_verilog -lib COREAHBLSRAM_OBF_LIB {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\COREAHBLSRAM_0_0\rtl\vlog\core_obfuscated\CoreAHBLSRAM.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\SmartFusion2_FIC_Tutorial_sb.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\top\top.v}
set_top_level {top}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\CCC_0\SmartFusion2_FIC_Tutorial_sb_CCC_0_FCCC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb\FABOSC_0\SmartFusion2_FIC_Tutorial_sb_FABOSC_0_OSC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\component\work\SmartFusion2_FIC_Tutorial_sb_MSS\SmartFusion2_FIC_Tutorial_sb_MSS.sdc}
derive_constraints
write_sdc {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\constraint\top_derived_constraints.sdc}
write_pdc {C:\igloo2_task_feb_2021\SF2\TU0310_SF2_FIC\Libero_Project\constraint\fp\top_derived_constraints.pdc}
