# Creating SmartDesign "EPCS_SERDES"
set sd_name {EPCS_SERDES}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PENABLE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PRESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {EPCS_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK1_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK1_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD0_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD0_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD1_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD1_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD2_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD2_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD3_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RXD3_P} -port_direction {IN} -port_is_pad {1}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PSLVERR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_RX_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_RX_IDLE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_RX_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_TX_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane1_TX_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane2_RX_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane2_RX_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane2_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane2_TX_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Lane2_TX_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_OUT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD0_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD1_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD1_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD2_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD2_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD3_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TXD3_P} -port_direction {OUT} -port_is_pad {1}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PADDR} -port_direction {IN} -port_range {[13:2]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Lane1_TX_data} -port_direction {IN} -port_range {[19:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Lane2_TX_data} -port_direction {IN} -port_range {[19:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Lane1_RX_data} -port_direction {OUT} -port_range {[19:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Lane2_RX_data} -port_direction {OUT} -port_range {[19:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_S_PADDR" \
"PSELx:APB_S_PSEL" \
"PENABLE:APB_S_PENABLE" \
"PWRITE:APB_S_PWRITE" \
"PRDATA:APB_S_PRDATA" \
"PWDATA:APB_S_PWDATA" \
"PREADY:APB_S_PREADY" \
"PSLVERR:APB_S_PSLVERR" } 

# Add epcs_rx_intf_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {epcs_rx_intf} -hdl_file {hdl\epcs_rx_intf.v} -instance_name {epcs_rx_intf_1}



# Add epcs_rx_intf_2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {epcs_rx_intf} -hdl_file {hdl\epcs_rx_intf.v} -instance_name {epcs_rx_intf_2}



# Add epcs_tx_intf_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {epcs_tx_intf} -hdl_file {hdl\epcs_tx_intf.v} -instance_name {epcs_tx_intf_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {epcs_tx_intf_1:txvali} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {epcs_tx_intf_1:txvalo}



# Add epcs_tx_intf_2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {epcs_tx_intf} -hdl_file {hdl\epcs_tx_intf.v} -instance_name {epcs_tx_intf_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {epcs_tx_intf_2:txvali} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {epcs_tx_intf_2:txvalo}



# Add rx_delay_line1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {delay_line} -hdl_file {hdl\delay_line.v} -instance_name {rx_delay_line1}



# Add rx_delay_line2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {delay_line} -hdl_file {hdl\delay_line.v} -instance_name {rx_delay_line2}



# Add SERDES_IF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {SERDES_IF_C0} -instance_name {SERDES_IF_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_1_PWRDN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_1_TX_VAL} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_1_TX_OOB} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_1_RX_ERR} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_PWRDN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_TX_VAL} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_TX_OOB} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_RX_ERR} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_1_TX_CLK_STABLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SERDES_IF_C0_0:EPCS_2_TX_CLK_STABLE}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_S_PCLK" "SERDES_IF_C0_0:APB_S_PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_S_PRESET_N" "SERDES_IF_C0_0:APB_S_PRESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"EPCS_RESET_N" "SERDES_IF_C0_0:EPCS_1_RESET_N" "SERDES_IF_C0_0:EPCS_2_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_READY" "SERDES_IF_C0_0:EPCS_1_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_RX_CLK" "SERDES_IF_C0_0:EPCS_1_RX_CLK" "epcs_rx_intf_1:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_RX_IDLE" "SERDES_IF_C0_0:EPCS_1_RX_IDLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_RX_RESET_N" "SERDES_IF_C0_0:EPCS_1_RX_RESET_N" "epcs_rx_intf_1:rstn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_RX_VAL" "epcs_rx_intf_1:rxvalo" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_TX_CLK" "SERDES_IF_C0_0:EPCS_1_TX_CLK" "epcs_tx_intf_1:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_TX_RESET_N" "SERDES_IF_C0_0:EPCS_1_TX_RESET_N" "epcs_tx_intf_1:rstn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_RX_CLK" "SERDES_IF_C0_0:EPCS_2_RX_CLK" "epcs_rx_intf_2:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_RX_RESET_N" "SERDES_IF_C0_0:EPCS_2_RX_RESET_N" "epcs_rx_intf_2:rstn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_RX_VAL" "epcs_rx_intf_2:rxvalo" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_TX_CLK" "SERDES_IF_C0_0:EPCS_2_TX_CLK" "epcs_tx_intf_2:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_TX_RESET_N" "SERDES_IF_C0_0:EPCS_2_TX_RESET_N" "epcs_tx_intf_2:rstn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK1_N" "SERDES_IF_C0_0:REFCLK1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK1_P" "SERDES_IF_C0_0:REFCLK1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK_OUT" "SERDES_IF_C0_0:REFCLK1_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD0_N" "SERDES_IF_C0_0:RXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD0_P" "SERDES_IF_C0_0:RXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD1_N" "SERDES_IF_C0_0:RXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD1_P" "SERDES_IF_C0_0:RXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD2_N" "SERDES_IF_C0_0:RXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD2_P" "SERDES_IF_C0_0:RXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD3_N" "SERDES_IF_C0_0:RXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RXD3_P" "SERDES_IF_C0_0:RXD3_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_1_RX_VAL" "epcs_rx_intf_1:rxvali" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_2_RX_VAL" "epcs_rx_intf_2:rxvali" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD0_N" "TXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD0_P" "TXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD1_N" "TXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD1_P" "TXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD2_N" "TXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD2_P" "TXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD3_N" "TXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:TXD3_P" "TXD3_P" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_RX_data" "epcs_rx_intf_1:rxdout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane1_TX_data" "epcs_tx_intf_1:txdin" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_RX_data" "epcs_rx_intf_2:rxdout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Lane2_TX_data" "epcs_tx_intf_2:txdin" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_1_RX_DATA" "rx_delay_line1:in_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_1_TX_DATA" "epcs_tx_intf_1:txdout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_2_RX_DATA" "rx_delay_line2:in_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SERDES_IF_C0_0:EPCS_2_TX_DATA" "epcs_tx_intf_2:txdout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"epcs_rx_intf_1:rxdin" "rx_delay_line1:out_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"epcs_rx_intf_2:rxdin" "rx_delay_line2:out_data" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_SLAVE" "SERDES_IF_C0_0:APB_SLAVE" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "EPCS_SERDES"
generate_component -component_name ${sd_name}
