///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//
// © 2021 Microchip Technology Inc. and its subsidiaries
// All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED 
// IN ADVANCE IN WRITING.

//  File Name       : delay_line.v 
//
//  Description     : This module implements the delay line logic.

//  Targeted device : Family           Die          Package
//                    SmartFusion2     M2S090TS     484 FBGA
//  Author          : Solutions Team
//                              

//-------------------------------------------------------------------------

module delay_line 
 #(
    parameter BUS_WIDTH = 20,
    parameter DELAY = 4
   )(
    output wire[BUS_WIDTH-1:0] out_data, 
    input  wire[BUS_WIDTH-1:0] in_data);

wire [BUS_WIDTH-1:0] data_d[DELAY-1:0];

assign data_d[0] = in_data;
assign out_data = data_d[DELAY-1];

genvar i, j;
generate 
  for (i=1; i<DELAY; i=i+1) begin
	  bufd_bus
	  #(
		 .BUS_WIDTH	(BUS_WIDTH)
	 ) 
	  dly1 (
		  .out_data (data_d[i][BUS_WIDTH-1:0]),
		  .in_data (data_d[i-1][BUS_WIDTH-1:0])
	  );
  end
endgenerate
 
endmodule

module bufd_bus 
 #(
    parameter BUS_WIDTH = 20
   )(
    output wire[BUS_WIDTH-1:0] out_data, 
    input  wire[BUS_WIDTH-1:0] in_data);

 genvar i;
 generate
 for (i=0; i<BUS_WIDTH; i=i+1) begin
	 BUFD bufd (
		 .Y (out_data[i]),
		 .A(in_data[i])
	 );
 end
 endgenerate
endmodule

