# Exporting Component Description of SERDES_IF_C0 to TCL
# Family: IGLOO2
# Part Number: M2GL010T-1FG484
# Create and Configure the core component SERDES_IF_C0
create_and_configure_core -core_vlnv Actel:SgCore:SERDES_IF:$SERDES_IFver -component_name {SERDES_IF_C0} -params {\
"ACT_SIM:2"  \
"BAR0_PREFETCH_IS_USED:false"  \
"BAR0_SIZE:KB4"  \
"BAR0_TYPE:MEM"  \
"BAR0_WID:32BIT"  \
"BAR1_PREFETCH_IS_USED:false"  \
"BAR1_SIZE:BLANK"  \
"BAR1_TYPE:BLANK"  \
"BAR1_WID:NONE"  \
"BAR2_PREFETCH_IS_USED:false"  \
"BAR2_SIZE:BLANK"  \
"BAR2_TYPE:BLANK"  \
"BAR2_WID:NONE"  \
"BAR3_PREFETCH_IS_USED:false"  \
"BAR3_SIZE:BLANK"  \
"BAR3_TYPE:BLANK"  \
"BAR3_WID:NONE"  \
"BAR4_PREFETCH_IS_USED:false"  \
"BAR4_SIZE:BLANK"  \
"BAR4_TYPE:BLANK"  \
"BAR4_WID:NONE"  \
"BAR5_PREFETCH_IS_USED:false"  \
"BAR5_SIZE:BLANK"  \
"BAR5_TYPE:BLANK"  \
"BAR5_WID:NONE"  \
"BRIDGE_EMPH:DB35"  \
"BRIDGE_SPEC_REV:REV20"  \
"ECC_INTR_RP_IS_USED:false"  \
"ECC_INTR_RX_IS_USED:false"  \
"ECC_INTR_TX_IS_USED:false"  \
"ECC_RP_IS_USED:true"  \
"ECC_RX_IS_USED:true"  \
"ECC_TX_IS_USED:true"  \
"FABIF_BUS_IS_USED:AXIBUS"  \
"FABIF_INTERFACE:MASTER"  \
"IS_BAR_2GB_AVAILABLE:0"  \
"IS_GEN2_AVAILABLE:1"  \
"L2_P2_IS_USED:false"  \
"LANE0_ATXDRA_DYN_7_0:0x0"  \
"LANE0_ATXDRA_DYN_15_8:0x0"  \
"LANE0_ATXDRA_DYN_20_16:0x0"  \
"LANE0_ATXDRA_EI1_7_0:0x0"  \
"LANE0_ATXDRA_EI1_15_8:0x0"  \
"LANE0_ATXDRA_EI1_20_16:0x0"  \
"LANE0_ATXDRA_EI2_7_0:0x0"  \
"LANE0_ATXDRA_EI2_15_8:0x0"  \
"LANE0_ATXDRA_EI2_20_16:0x0"  \
"LANE0_ATXDRP_DYN_7_0:0x0"  \
"LANE0_ATXDRP_DYN_15_8:0x0"  \
"LANE0_ATXDRP_DYN_20_16:0x0"  \
"LANE0_ATXDRP_EI1_7_0:0x0"  \
"LANE0_ATXDRP_EI1_15_8:0x0"  \
"LANE0_ATXDRP_EI1_20_16:0x0"  \
"LANE0_ATXDRP_EI2_7_0:0x0"  \
"LANE0_ATXDRP_EI2_15_8:0x0"  \
"LANE0_ATXDRP_EI2_20_16:0x0"  \
"LANE0_ATXDRR_7_0:0x0"  \
"LANE0_ATXDRR_14_8:0x0"  \
"LANE0_ATXDRT_DYN_7_0:0x0"  \
"LANE0_ATXDRT_DYN_15_8:0x0"  \
"LANE0_ATXDRT_DYN_20_16:0x0"  \
"LANE0_ATXDRT_EI1_7_0:0x0"  \
"LANE0_ATXDRT_EI1_15_8:0x0"  \
"LANE0_ATXDRT_EI1_20_16:0x0"  \
"LANE0_ATXDRT_EI2_7_0:0x0"  \
"LANE0_ATXDRT_EI2_15_8:0x0"  \
"LANE0_ATXDRT_EI2_20_16:0x0"  \
"LANE0_CALIB_STABILITY_COUNT:0x0"  \
"LANE0_CDR_PLL_MANUAL_CR:0x0"  \
"LANE0_CNT250NS_MAX:0x0"  \
"LANE0_CNT250NS_MAX_5GBPS:0x0"  \
"LANE0_CR0:0x0"  \
"LANE0_CUST_INDEX:0"  \
"LANE0_CUSTOM_PATTERN_7_0:0x0"  \
"LANE0_CUSTOM_PATTERN_15_8:0x0"  \
"LANE0_CUSTOM_PATTERN_23_16:0x0"  \
"LANE0_CUSTOM_PATTERN_31_24:0x0"  \
"LANE0_CUSTOM_PATTERN_39_32:0x0"  \
"LANE0_CUSTOM_PATTERN_47_40:0x0"  \
"LANE0_CUSTOM_PATTERN_55_48:0x0"  \
"LANE0_CUSTOM_PATTERN_63_56:0x0"  \
"LANE0_CUSTOM_PATTERN_71_64:0x0"  \
"LANE0_CUSTOM_PATTERN_79_72:0x0"  \
"LANE0_CUSTOM_PATTERN_CTRL:0x0"  \
"LANE0_CUSTOM_PATTERN_STATUS:0x0"  \
"LANE0_ENDCALIB_MAX:0x0"  \
"LANE0_EPCS_DATA_WIDTH:20"  \
"LANE0_ERRCNT_DEC:0x0"  \
"LANE0_FORCE_ATXDRA_7_0:0x0"  \
"LANE0_FORCE_ATXDRA_15_8:0x0"  \
"LANE0_FORCE_ATXDRA_20_16:0x0"  \
"LANE0_FORCE_ATXDRP_7_0:0x0"  \
"LANE0_FORCE_ATXDRP_15_8:0x0"  \
"LANE0_FORCE_ATXDRP_20_16:0x0"  \
"LANE0_FORCE_ATXDRR_7_0:0x0"  \
"LANE0_FORCE_ATXDRR_15_8:0x0"  \
"LANE0_FORCE_ATXDRR_20_16:0x0"  \
"LANE0_FORCE_ATXDRT_7_0:0x0"  \
"LANE0_FORCE_ATXDRT_15_8:0x0"  \
"LANE0_FORCE_ATXDRT_20_16:0x0"  \
"LANE0_FORCE_RXD_OFFSET_CALIB:0x0"  \
"LANE0_FORCE_RXT_OFFSET_CALIB:0x0"  \
"LANE0_FORCE_SCHMITT_TRIG_CALIB:0x0"  \
"LANE0_GEN1_RX_PLL_CCP:0x0"  \
"LANE0_GEN1_TX_PLL_CCP:0x0"  \
"LANE0_GEN2_RX_PLL_CCP:0x0"  \
"LANE0_GEN2_TX_PLL_CCP:0x0"  \
"LANE0_IMPED_RATIO:0x0"  \
"LANE0_OVERRIDE_CALIB:0x0"  \
"LANE0_PCS_LOOPBACK_CTRL:0x0"  \
"LANE0_PHY_POWER_OVERRIDE:0x0"  \
"LANE0_PHY_RESET_OVERRIDE:0x0"  \
"LANE0_PLL_F_PCLK_RATIO:0x0"  \
"LANE0_PLL_F_PCLK_RATIO_5GBPS:0x0"  \
"LANE0_PLL_M_N:0x0"  \
"LANE0_PLL_M_N_5GBPS:0x0"  \
"LANE0_PMA_STATUS:0x0"  \
"LANE0_POWER_DOWN:0x0"  \
"LANE0_PRBS_CTRL:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_7_0:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_15_8:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_23_16:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_31_24:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_39_32:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_47_40:0x0"  \
"LANE0_PRBS_ERR_CYC_FIRST_49_48:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_7_0:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_15_8:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_23_16:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_31_24:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_39_32:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_47_40:0x0"  \
"LANE0_PRBS_ERR_CYC_LAST_49_48:0x0"  \
"LANE0_PRBS_ERRCNT:0x0"  \
"LANE0_RE_AMP_RATIO:0x0"  \
"LANE0_RE_AMP_RATIO_DEEMP0:0x0"  \
"LANE0_RE_AMP_RATIO_DEEMP1:0x0"  \
"LANE0_RE_AMP_RATIO_USER:0"  \
"LANE0_RE_CHAN_CHARS_USER:User Defined"  \
"LANE0_RE_CUT_RATIO:0x0"  \
"LANE0_RE_CUT_RATIO_DEEMP0:0x0"  \
"LANE0_RE_CUT_RATIO_DEEMP1:0x0"  \
"LANE0_RE_CUT_RATIO_USER:0"  \
"LANE0_RE_IMPED_RATIO_USER:100"  \
"LANE0_RE_SWEEP_CENTER:0x0"  \
"LANE0_RECEIVE_CTL_EQUALIZATION:Short-Reach"  \
"LANE0_RX_OFFSET_COUNT:0x0"  \
"LANE0_RX_SWEEP_CENTER:0x0"  \
"LANE0_RXD_OFFSET_CALIB_RESULT:0x0"  \
"LANE0_RXIDLE_MAX_ERRCNT_THR:0x0"  \
"LANE0_RXT_OFFSET_CALIB_RESULT:0x0"  \
"LANE0_SCHMITT_TRIG_CALIB_RESULT:0x0"  \
"LANE0_TX_AMP_RATIO:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN0_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN0_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN1_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN1_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN2_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN2_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN3_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN3_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN4_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN4_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN5_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN5_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN6_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN6_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN7_FULL:0x0"  \
"LANE0_TX_AMP_RATIO_MARGIN7_HALF:0x0"  \
"LANE0_TX_AMP_RATIO_USER:1200"  \
"LANE0_TX_POST_RATIO_ACTUAL:0.0"  \
"LANE0_TX_POST_RATIO_USER:0.0"  \
"LANE0_TX_PRE_RATIO:0x0"  \
"LANE0_TX_PRE_RATIO_ACTUAL:0.0"  \
"LANE0_TX_PRE_RATIO_DEEMP0_FULL:0x0"  \
"LANE0_TX_PRE_RATIO_DEEMP0_HALF:0x0"  \
"LANE0_TX_PRE_RATIO_DEEMP1_FULL:0x0"  \
"LANE0_TX_PRE_RATIO_DEEMP1_HALF:0x0"  \
"LANE0_TX_PRE_RATIO_USER:0.0"  \
"LANE0_TX_PST_RATIO:0x0"  \
"LANE0_TX_PST_RATIO_DEEMP0_FULL:0x0"  \
"LANE0_TX_PST_RATIO_DEEMP0_HALF:0x0"  \
"LANE0_TX_PST_RATIO_DEEMP1_FULL:0x0"  \
"LANE0_TX_PST_RATIO_DEEMP1_HALF:0x0"  \
"LANE0_TX_SWEEP_CENTER:0x0"  \
"LANE0_UPDATE_SETTINGS:0x0"  \
"LANE1_ATXDRA_DYN_7_0:0x0"  \
"LANE1_ATXDRA_DYN_15_8:0x0"  \
"LANE1_ATXDRA_DYN_20_16:0x0"  \
"LANE1_ATXDRA_EI1_7_0:0x0"  \
"LANE1_ATXDRA_EI1_15_8:0x0"  \
"LANE1_ATXDRA_EI1_20_16:0x0"  \
"LANE1_ATXDRA_EI2_7_0:0x0"  \
"LANE1_ATXDRA_EI2_15_8:0x0"  \
"LANE1_ATXDRA_EI2_20_16:0x0"  \
"LANE1_ATXDRP_DYN_7_0:0x0"  \
"LANE1_ATXDRP_DYN_15_8:0x0"  \
"LANE1_ATXDRP_DYN_20_16:0x0"  \
"LANE1_ATXDRP_EI1_7_0:0x0"  \
"LANE1_ATXDRP_EI1_15_8:0x0"  \
"LANE1_ATXDRP_EI1_20_16:0x0"  \
"LANE1_ATXDRP_EI2_7_0:0x0"  \
"LANE1_ATXDRP_EI2_15_8:0x0"  \
"LANE1_ATXDRP_EI2_20_16:0x0"  \
"LANE1_ATXDRR_7_0:0x0"  \
"LANE1_ATXDRR_14_8:0x0"  \
"LANE1_ATXDRT_DYN_7_0:0x0"  \
"LANE1_ATXDRT_DYN_15_8:0x0"  \
"LANE1_ATXDRT_DYN_20_16:0x0"  \
"LANE1_ATXDRT_EI1_7_0:0x0"  \
"LANE1_ATXDRT_EI1_15_8:0x0"  \
"LANE1_ATXDRT_EI1_20_16:0x0"  \
"LANE1_ATXDRT_EI2_7_0:0x0"  \
"LANE1_ATXDRT_EI2_15_8:0x0"  \
"LANE1_ATXDRT_EI2_20_16:0x0"  \
"LANE1_CALIB_STABILITY_COUNT:0x38"  \
"LANE1_CDR_PLL_MANUAL_CR:0x0"  \
"LANE1_CNT250NS_MAX:0x20"  \
"LANE1_CNT250NS_MAX_5GBPS:0x0"  \
"LANE1_CR0:0x80"  \
"LANE1_CUST_INDEX:0"  \
"LANE1_CUSTOM_PATTERN_7_0:0x0"  \
"LANE1_CUSTOM_PATTERN_15_8:0x0"  \
"LANE1_CUSTOM_PATTERN_23_16:0x0"  \
"LANE1_CUSTOM_PATTERN_31_24:0x0"  \
"LANE1_CUSTOM_PATTERN_39_32:0x0"  \
"LANE1_CUSTOM_PATTERN_47_40:0x0"  \
"LANE1_CUSTOM_PATTERN_55_48:0x0"  \
"LANE1_CUSTOM_PATTERN_63_56:0x0"  \
"LANE1_CUSTOM_PATTERN_71_64:0x0"  \
"LANE1_CUSTOM_PATTERN_79_72:0x0"  \
"LANE1_CUSTOM_PATTERN_CTRL:0x0"  \
"LANE1_CUSTOM_PATTERN_STATUS:0x0"  \
"LANE1_ENDCALIB_MAX:0x10"  \
"LANE1_EPCS_DATA_WIDTH:20"  \
"LANE1_ERRCNT_DEC:0x20"  \
"LANE1_FORCE_ATXDRA_7_0:0x0"  \
"LANE1_FORCE_ATXDRA_15_8:0x0"  \
"LANE1_FORCE_ATXDRA_20_16:0x0"  \
"LANE1_FORCE_ATXDRP_7_0:0x0"  \
"LANE1_FORCE_ATXDRP_15_8:0x0"  \
"LANE1_FORCE_ATXDRP_20_16:0x0"  \
"LANE1_FORCE_ATXDRR_7_0:0x0"  \
"LANE1_FORCE_ATXDRR_15_8:0x0"  \
"LANE1_FORCE_ATXDRR_20_16:0x0"  \
"LANE1_FORCE_ATXDRT_7_0:0x0"  \
"LANE1_FORCE_ATXDRT_15_8:0x0"  \
"LANE1_FORCE_ATXDRT_20_16:0x0"  \
"LANE1_FORCE_RXD_OFFSET_CALIB:0x0"  \
"LANE1_FORCE_RXT_OFFSET_CALIB:0x0"  \
"LANE1_FORCE_SCHMITT_TRIG_CALIB:0x0"  \
"LANE1_GEN1_RX_PLL_CCP:0x22"  \
"LANE1_GEN1_TX_PLL_CCP:0x2"  \
"LANE1_GEN2_RX_PLL_CCP:0x0"  \
"LANE1_GEN2_TX_PLL_CCP:0x0"  \
"LANE1_IMPED_RATIO:0x80"  \
"LANE1_OVERRIDE_CALIB:0x0"  \
"LANE1_PCS_LOOPBACK_CTRL:0x0"  \
"LANE1_PHY_POWER_OVERRIDE:0x0"  \
"LANE1_PHY_RESET_OVERRIDE:0x0"  \
"LANE1_PLL_F_PCLK_RATIO:0x0"  \
"LANE1_PLL_F_PCLK_RATIO_5GBPS:0x0"  \
"LANE1_PLL_M_N:0x13"  \
"LANE1_PLL_M_N_5GBPS:0x0"  \
"LANE1_PMA_STATUS:0x0"  \
"LANE1_POWER_DOWN:0x00"  \
"LANE1_PRBS_CTRL:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_7_0:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_15_8:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_23_16:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_31_24:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_39_32:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_47_40:0x0"  \
"LANE1_PRBS_ERR_CYC_FIRST_49_48:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_7_0:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_15_8:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_23_16:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_31_24:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_39_32:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_47_40:0x0"  \
"LANE1_PRBS_ERR_CYC_LAST_49_48:0x0"  \
"LANE1_PRBS_ERRCNT:0x0"  \
"LANE1_RE_AMP_RATIO:0x00"  \
"LANE1_RE_AMP_RATIO_DEEMP0:0x0"  \
"LANE1_RE_AMP_RATIO_DEEMP1:0x0"  \
"LANE1_RE_AMP_RATIO_USER:N/A"  \
"LANE1_RE_CHAN_CHARS_USER:CTLE Disabled"  \
"LANE1_RE_CUT_RATIO:0x00"  \
"LANE1_RE_CUT_RATIO_DEEMP0:0x0"  \
"LANE1_RE_CUT_RATIO_DEEMP1:0x0"  \
"LANE1_RE_CUT_RATIO_USER:N/A"  \
"LANE1_RE_IMPED_RATIO_USER:100"  \
"LANE1_RE_SWEEP_CENTER:0x0"  \
"LANE1_RECEIVE_CTL_EQUALIZATION:Short-Reach"  \
"LANE1_RX_OFFSET_COUNT:0x70"  \
"LANE1_RX_SWEEP_CENTER:0x0"  \
"LANE1_RXD_OFFSET_CALIB_RESULT:0x0"  \
"LANE1_RXIDLE_MAX_ERRCNT_THR:0xF8"  \
"LANE1_RXT_OFFSET_CALIB_RESULT:0x0"  \
"LANE1_SCHMITT_TRIG_CALIB_RESULT:0x0"  \
"LANE1_TX_AMP_RATIO:0x80"  \
"LANE1_TX_AMP_RATIO_MARGIN0_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN0_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN1_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN1_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN2_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN2_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN3_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN3_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN4_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN4_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN5_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN5_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN6_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN6_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN7_FULL:0x0"  \
"LANE1_TX_AMP_RATIO_MARGIN7_HALF:0x0"  \
"LANE1_TX_AMP_RATIO_USER:1200"  \
"LANE1_TX_POST_RATIO_ACTUAL:-3.5"  \
"LANE1_TX_POST_RATIO_USER:-3.5"  \
"LANE1_TX_PRE_RATIO:0x00"  \
"LANE1_TX_PRE_RATIO_ACTUAL:0"  \
"LANE1_TX_PRE_RATIO_DEEMP0_FULL:0x0"  \
"LANE1_TX_PRE_RATIO_DEEMP0_HALF:0x0"  \
"LANE1_TX_PRE_RATIO_DEEMP1_FULL:0x0"  \
"LANE1_TX_PRE_RATIO_DEEMP1_HALF:0x0"  \
"LANE1_TX_PRE_RATIO_USER:0"  \
"LANE1_TX_PST_RATIO:0x15"  \
"LANE1_TX_PST_RATIO_DEEMP0_FULL:0x0"  \
"LANE1_TX_PST_RATIO_DEEMP0_HALF:0x0"  \
"LANE1_TX_PST_RATIO_DEEMP1_FULL:0x0"  \
"LANE1_TX_PST_RATIO_DEEMP1_HALF:0x0"  \
"LANE1_TX_SWEEP_CENTER:0x0"  \
"LANE1_UPDATE_SETTINGS:0x0"  \
"LANE2_ATXDRA_DYN_7_0:0x0"  \
"LANE2_ATXDRA_DYN_15_8:0x0"  \
"LANE2_ATXDRA_DYN_20_16:0x0"  \
"LANE2_ATXDRA_EI1_7_0:0x0"  \
"LANE2_ATXDRA_EI1_15_8:0x0"  \
"LANE2_ATXDRA_EI1_20_16:0x0"  \
"LANE2_ATXDRA_EI2_7_0:0x0"  \
"LANE2_ATXDRA_EI2_15_8:0x0"  \
"LANE2_ATXDRA_EI2_20_16:0x0"  \
"LANE2_ATXDRP_DYN_7_0:0x0"  \
"LANE2_ATXDRP_DYN_15_8:0x0"  \
"LANE2_ATXDRP_DYN_20_16:0x0"  \
"LANE2_ATXDRP_EI1_7_0:0x0"  \
"LANE2_ATXDRP_EI1_15_8:0x0"  \
"LANE2_ATXDRP_EI1_20_16:0x0"  \
"LANE2_ATXDRP_EI2_7_0:0x0"  \
"LANE2_ATXDRP_EI2_15_8:0x0"  \
"LANE2_ATXDRP_EI2_20_16:0x0"  \
"LANE2_ATXDRR_7_0:0x0"  \
"LANE2_ATXDRR_14_8:0x0"  \
"LANE2_ATXDRT_DYN_7_0:0x0"  \
"LANE2_ATXDRT_DYN_15_8:0x0"  \
"LANE2_ATXDRT_DYN_20_16:0x0"  \
"LANE2_ATXDRT_EI1_7_0:0x0"  \
"LANE2_ATXDRT_EI1_15_8:0x0"  \
"LANE2_ATXDRT_EI1_20_16:0x0"  \
"LANE2_ATXDRT_EI2_7_0:0x0"  \
"LANE2_ATXDRT_EI2_15_8:0x0"  \
"LANE2_ATXDRT_EI2_20_16:0x0"  \
"LANE2_CALIB_STABILITY_COUNT:0x38"  \
"LANE2_CDR_PLL_MANUAL_CR:0x0"  \
"LANE2_CNT250NS_MAX:0x20"  \
"LANE2_CNT250NS_MAX_5GBPS:0x0"  \
"LANE2_CR0:0x80"  \
"LANE2_CUST_INDEX:0"  \
"LANE2_CUSTOM_PATTERN_7_0:0x0"  \
"LANE2_CUSTOM_PATTERN_15_8:0x0"  \
"LANE2_CUSTOM_PATTERN_23_16:0x0"  \
"LANE2_CUSTOM_PATTERN_31_24:0x0"  \
"LANE2_CUSTOM_PATTERN_39_32:0x0"  \
"LANE2_CUSTOM_PATTERN_47_40:0x0"  \
"LANE2_CUSTOM_PATTERN_55_48:0x0"  \
"LANE2_CUSTOM_PATTERN_63_56:0x0"  \
"LANE2_CUSTOM_PATTERN_71_64:0x0"  \
"LANE2_CUSTOM_PATTERN_79_72:0x0"  \
"LANE2_CUSTOM_PATTERN_CTRL:0x0"  \
"LANE2_CUSTOM_PATTERN_STATUS:0x0"  \
"LANE2_ENDCALIB_MAX:0x10"  \
"LANE2_EPCS_DATA_WIDTH:20"  \
"LANE2_ERRCNT_DEC:0x20"  \
"LANE2_FORCE_ATXDRA_7_0:0x0"  \
"LANE2_FORCE_ATXDRA_15_8:0x0"  \
"LANE2_FORCE_ATXDRA_20_16:0x0"  \
"LANE2_FORCE_ATXDRP_7_0:0x0"  \
"LANE2_FORCE_ATXDRP_15_8:0x0"  \
"LANE2_FORCE_ATXDRP_20_16:0x0"  \
"LANE2_FORCE_ATXDRR_7_0:0x0"  \
"LANE2_FORCE_ATXDRR_15_8:0x0"  \
"LANE2_FORCE_ATXDRR_20_16:0x0"  \
"LANE2_FORCE_ATXDRT_7_0:0x0"  \
"LANE2_FORCE_ATXDRT_15_8:0x0"  \
"LANE2_FORCE_ATXDRT_20_16:0x0"  \
"LANE2_FORCE_RXD_OFFSET_CALIB:0x0"  \
"LANE2_FORCE_RXT_OFFSET_CALIB:0x0"  \
"LANE2_FORCE_SCHMITT_TRIG_CALIB:0x0"  \
"LANE2_GEN1_RX_PLL_CCP:0x22"  \
"LANE2_GEN1_TX_PLL_CCP:0x2"  \
"LANE2_GEN2_RX_PLL_CCP:0x0"  \
"LANE2_GEN2_TX_PLL_CCP:0x0"  \
"LANE2_IMPED_RATIO:0x80"  \
"LANE2_OVERRIDE_CALIB:0x0"  \
"LANE2_PCS_LOOPBACK_CTRL:0x0"  \
"LANE2_PHY_POWER_OVERRIDE:0x0"  \
"LANE2_PHY_RESET_OVERRIDE:0x0"  \
"LANE2_PLL_F_PCLK_RATIO:0x0"  \
"LANE2_PLL_F_PCLK_RATIO_5GBPS:0x0"  \
"LANE2_PLL_M_N:0x13"  \
"LANE2_PLL_M_N_5GBPS:0x0"  \
"LANE2_PMA_STATUS:0x0"  \
"LANE2_POWER_DOWN:0x00"  \
"LANE2_PRBS_CTRL:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_7_0:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_15_8:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_23_16:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_31_24:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_39_32:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_47_40:0x0"  \
"LANE2_PRBS_ERR_CYC_FIRST_49_48:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_7_0:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_15_8:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_23_16:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_31_24:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_39_32:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_47_40:0x0"  \
"LANE2_PRBS_ERR_CYC_LAST_49_48:0x0"  \
"LANE2_PRBS_ERRCNT:0x0"  \
"LANE2_RE_AMP_RATIO:0x00"  \
"LANE2_RE_AMP_RATIO_DEEMP0:0x0"  \
"LANE2_RE_AMP_RATIO_DEEMP1:0x0"  \
"LANE2_RE_AMP_RATIO_USER:N/A"  \
"LANE2_RE_CHAN_CHARS_USER:CTLE Disabled"  \
"LANE2_RE_CUT_RATIO:0x00"  \
"LANE2_RE_CUT_RATIO_DEEMP0:0x0"  \
"LANE2_RE_CUT_RATIO_DEEMP1:0x0"  \
"LANE2_RE_CUT_RATIO_USER:N/A"  \
"LANE2_RE_IMPED_RATIO_USER:100"  \
"LANE2_RE_SWEEP_CENTER:0x0"  \
"LANE2_RECEIVE_CTL_EQUALIZATION:Short-Reach"  \
"LANE2_RX_OFFSET_COUNT:0x70"  \
"LANE2_RX_SWEEP_CENTER:0x0"  \
"LANE2_RXD_OFFSET_CALIB_RESULT:0x0"  \
"LANE2_RXIDLE_MAX_ERRCNT_THR:0xF8"  \
"LANE2_RXT_OFFSET_CALIB_RESULT:0x0"  \
"LANE2_SCHMITT_TRIG_CALIB_RESULT:0x0"  \
"LANE2_TX_AMP_RATIO:0x80"  \
"LANE2_TX_AMP_RATIO_MARGIN0_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN0_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN1_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN1_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN2_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN2_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN3_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN3_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN4_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN4_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN5_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN5_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN6_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN6_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN7_FULL:0x0"  \
"LANE2_TX_AMP_RATIO_MARGIN7_HALF:0x0"  \
"LANE2_TX_AMP_RATIO_USER:1200"  \
"LANE2_TX_POST_RATIO_ACTUAL:-3.5"  \
"LANE2_TX_POST_RATIO_USER:-3.5"  \
"LANE2_TX_PRE_RATIO:0x00"  \
"LANE2_TX_PRE_RATIO_ACTUAL:0"  \
"LANE2_TX_PRE_RATIO_DEEMP0_FULL:0x0"  \
"LANE2_TX_PRE_RATIO_DEEMP0_HALF:0x0"  \
"LANE2_TX_PRE_RATIO_DEEMP1_FULL:0x0"  \
"LANE2_TX_PRE_RATIO_DEEMP1_HALF:0x0"  \
"LANE2_TX_PRE_RATIO_USER:0"  \
"LANE2_TX_PST_RATIO:0x15"  \
"LANE2_TX_PST_RATIO_DEEMP0_FULL:0x0"  \
"LANE2_TX_PST_RATIO_DEEMP0_HALF:0x0"  \
"LANE2_TX_PST_RATIO_DEEMP1_FULL:0x0"  \
"LANE2_TX_PST_RATIO_DEEMP1_HALF:0x0"  \
"LANE2_TX_SWEEP_CENTER:0x0"  \
"LANE2_UPDATE_SETTINGS:0x0"  \
"LANE3_ATXDRA_DYN_7_0:0x0"  \
"LANE3_ATXDRA_DYN_15_8:0x0"  \
"LANE3_ATXDRA_DYN_20_16:0x0"  \
"LANE3_ATXDRA_EI1_7_0:0x0"  \
"LANE3_ATXDRA_EI1_15_8:0x0"  \
"LANE3_ATXDRA_EI1_20_16:0x0"  \
"LANE3_ATXDRA_EI2_7_0:0x0"  \
"LANE3_ATXDRA_EI2_15_8:0x0"  \
"LANE3_ATXDRA_EI2_20_16:0x0"  \
"LANE3_ATXDRP_DYN_7_0:0x0"  \
"LANE3_ATXDRP_DYN_15_8:0x0"  \
"LANE3_ATXDRP_DYN_20_16:0x0"  \
"LANE3_ATXDRP_EI1_7_0:0x0"  \
"LANE3_ATXDRP_EI1_15_8:0x0"  \
"LANE3_ATXDRP_EI1_20_16:0x0"  \
"LANE3_ATXDRP_EI2_7_0:0x0"  \
"LANE3_ATXDRP_EI2_15_8:0x0"  \
"LANE3_ATXDRP_EI2_20_16:0x0"  \
"LANE3_ATXDRR_7_0:0x0"  \
"LANE3_ATXDRR_14_8:0x0"  \
"LANE3_ATXDRT_DYN_7_0:0x0"  \
"LANE3_ATXDRT_DYN_15_8:0x0"  \
"LANE3_ATXDRT_DYN_20_16:0x0"  \
"LANE3_ATXDRT_EI1_7_0:0x0"  \
"LANE3_ATXDRT_EI1_15_8:0x0"  \
"LANE3_ATXDRT_EI1_20_16:0x0"  \
"LANE3_ATXDRT_EI2_7_0:0x0"  \
"LANE3_ATXDRT_EI2_15_8:0x0"  \
"LANE3_ATXDRT_EI2_20_16:0x0"  \
"LANE3_CALIB_STABILITY_COUNT:0x0"  \
"LANE3_CDR_PLL_MANUAL_CR:0x0"  \
"LANE3_CNT250NS_MAX:0x0"  \
"LANE3_CNT250NS_MAX_5GBPS:0x0"  \
"LANE3_CR0:0x0"  \
"LANE3_CUST_INDEX:0"  \
"LANE3_CUSTOM_PATTERN_7_0:0x0"  \
"LANE3_CUSTOM_PATTERN_15_8:0x0"  \
"LANE3_CUSTOM_PATTERN_23_16:0x0"  \
"LANE3_CUSTOM_PATTERN_31_24:0x0"  \
"LANE3_CUSTOM_PATTERN_39_32:0x0"  \
"LANE3_CUSTOM_PATTERN_47_40:0x0"  \
"LANE3_CUSTOM_PATTERN_55_48:0x0"  \
"LANE3_CUSTOM_PATTERN_63_56:0x0"  \
"LANE3_CUSTOM_PATTERN_71_64:0x0"  \
"LANE3_CUSTOM_PATTERN_79_72:0x0"  \
"LANE3_CUSTOM_PATTERN_CTRL:0x0"  \
"LANE3_CUSTOM_PATTERN_STATUS:0x0"  \
"LANE3_ENDCALIB_MAX:0x0"  \
"LANE3_EPCS_DATA_WIDTH:20"  \
"LANE3_ERRCNT_DEC:0x0"  \
"LANE3_FORCE_ATXDRA_7_0:0x0"  \
"LANE3_FORCE_ATXDRA_15_8:0x0"  \
"LANE3_FORCE_ATXDRA_20_16:0x0"  \
"LANE3_FORCE_ATXDRP_7_0:0x0"  \
"LANE3_FORCE_ATXDRP_15_8:0x0"  \
"LANE3_FORCE_ATXDRP_20_16:0x0"  \
"LANE3_FORCE_ATXDRR_7_0:0x0"  \
"LANE3_FORCE_ATXDRR_15_8:0x0"  \
"LANE3_FORCE_ATXDRR_20_16:0x0"  \
"LANE3_FORCE_ATXDRT_7_0:0x0"  \
"LANE3_FORCE_ATXDRT_15_8:0x0"  \
"LANE3_FORCE_ATXDRT_20_16:0x0"  \
"LANE3_FORCE_RXD_OFFSET_CALIB:0x0"  \
"LANE3_FORCE_RXT_OFFSET_CALIB:0x0"  \
"LANE3_FORCE_SCHMITT_TRIG_CALIB:0x0"  \
"LANE3_GEN1_RX_PLL_CCP:0x0"  \
"LANE3_GEN1_TX_PLL_CCP:0x0"  \
"LANE3_GEN2_RX_PLL_CCP:0x0"  \
"LANE3_GEN2_TX_PLL_CCP:0x0"  \
"LANE3_IMPED_RATIO:0x0"  \
"LANE3_OVERRIDE_CALIB:0x0"  \
"LANE3_PCS_LOOPBACK_CTRL:0x0"  \
"LANE3_PHY_POWER_OVERRIDE:0x0"  \
"LANE3_PHY_RESET_OVERRIDE:0x0"  \
"LANE3_PLL_F_PCLK_RATIO:0x0"  \
"LANE3_PLL_F_PCLK_RATIO_5GBPS:0x0"  \
"LANE3_PLL_M_N:0x0"  \
"LANE3_PLL_M_N_5GBPS:0x0"  \
"LANE3_PMA_STATUS:0x0"  \
"LANE3_POWER_DOWN:0x0"  \
"LANE3_PRBS_CTRL:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_7_0:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_15_8:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_23_16:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_31_24:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_39_32:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_47_40:0x0"  \
"LANE3_PRBS_ERR_CYC_FIRST_49_48:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_7_0:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_15_8:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_23_16:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_31_24:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_39_32:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_47_40:0x0"  \
"LANE3_PRBS_ERR_CYC_LAST_49_48:0x0"  \
"LANE3_PRBS_ERRCNT:0x0"  \
"LANE3_RE_AMP_RATIO:0x0"  \
"LANE3_RE_AMP_RATIO_DEEMP0:0x0"  \
"LANE3_RE_AMP_RATIO_DEEMP1:0x0"  \
"LANE3_RE_AMP_RATIO_USER:0"  \
"LANE3_RE_CHAN_CHARS_USER:User Defined"  \
"LANE3_RE_CUT_RATIO:0x0"  \
"LANE3_RE_CUT_RATIO_DEEMP0:0x0"  \
"LANE3_RE_CUT_RATIO_DEEMP1:0x0"  \
"LANE3_RE_CUT_RATIO_USER:0"  \
"LANE3_RE_IMPED_RATIO_USER:100"  \
"LANE3_RE_SWEEP_CENTER:0x0"  \
"LANE3_RECEIVE_CTL_EQUALIZATION:Short-Reach"  \
"LANE3_RX_OFFSET_COUNT:0x0"  \
"LANE3_RX_SWEEP_CENTER:0x0"  \
"LANE3_RXD_OFFSET_CALIB_RESULT:0x0"  \
"LANE3_RXIDLE_MAX_ERRCNT_THR:0x0"  \
"LANE3_RXT_OFFSET_CALIB_RESULT:0x0"  \
"LANE3_SCHMITT_TRIG_CALIB_RESULT:0x0"  \
"LANE3_TX_AMP_RATIO:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN0_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN0_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN1_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN1_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN2_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN2_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN3_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN3_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN4_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN4_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN5_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN5_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN6_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN6_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN7_FULL:0x0"  \
"LANE3_TX_AMP_RATIO_MARGIN7_HALF:0x0"  \
"LANE3_TX_AMP_RATIO_USER:1200"  \
"LANE3_TX_POST_RATIO_ACTUAL:0.0"  \
"LANE3_TX_POST_RATIO_USER:0.0"  \
"LANE3_TX_PRE_RATIO:0x0"  \
"LANE3_TX_PRE_RATIO_ACTUAL:0.0"  \
"LANE3_TX_PRE_RATIO_DEEMP0_FULL:0x0"  \
"LANE3_TX_PRE_RATIO_DEEMP0_HALF:0x0"  \
"LANE3_TX_PRE_RATIO_DEEMP1_FULL:0x0"  \
"LANE3_TX_PRE_RATIO_DEEMP1_HALF:0x0"  \
"LANE3_TX_PRE_RATIO_USER:0.0"  \
"LANE3_TX_PST_RATIO:0x0"  \
"LANE3_TX_PST_RATIO_DEEMP0_FULL:0x0"  \
"LANE3_TX_PST_RATIO_DEEMP0_HALF:0x0"  \
"LANE3_TX_PST_RATIO_DEEMP1_FULL:0x0"  \
"LANE3_TX_PST_RATIO_DEEMP1_HALF:0x0"  \
"LANE3_TX_SWEEP_CENTER:0x0"  \
"LANE3_UPDATE_SETTINGS:0x0"  \
"LANE_0:LN0"  \
"LANE_0_SPEED:BLANK"  \
"LANE_1:LN1"  \
"LANE_1_SPEED:EPCSCUST"  \
"LANE_2:LN2"  \
"LANE_2_SPEED:EPCSCUST"  \
"LANE_3:LN3"  \
"LANE_3_SPEED:BLANK"  \
"LANES_OF_PROTOCOL1:ONE"  \
"LANES_OF_PROTOCOL2:ONE"  \
"LOCATION_0:true"  \
"LOCATION_1:false"  \
"LOCATION_2:false"  \
"LOCATION_3:false"  \
"LOCATION_ID:SERDESIF_0"  \
"MODE_10V:0"  \
"PCIE_AER_ECRC_CAPABILITY:0x0"  \
"PCIE_ASPM_L0S_CAPABILITY:0x0f3f000f"  \
"PCIE_ASPM_L0S_GEN2:0x0"  \
"PCIE_ASPM_L1_CAPABILITY:0x0405000f"  \
"PCIE_AXI_MASTER_WINDOW0_0:0x0"  \
"PCIE_AXI_MASTER_WINDOW0_1:0x0"  \
"PCIE_AXI_MASTER_WINDOW0_2:0x0"  \
"PCIE_AXI_MASTER_WINDOW0_3:0x0"  \
"PCIE_AXI_MASTER_WINDOW1_0:0x0"  \
"PCIE_AXI_MASTER_WINDOW1_1:0x0"  \
"PCIE_AXI_MASTER_WINDOW1_2:0x0"  \
"PCIE_AXI_MASTER_WINDOW1_3:0x0"  \
"PCIE_AXI_MASTER_WINDOW2_0:0x0"  \
"PCIE_AXI_MASTER_WINDOW2_1:0x0"  \
"PCIE_AXI_MASTER_WINDOW2_2:0x0"  \
"PCIE_AXI_MASTER_WINDOW2_3:0x0"  \
"PCIE_AXI_MASTER_WINDOW3_0:0x0"  \
"PCIE_AXI_MASTER_WINDOW3_1:0x0"  \
"PCIE_AXI_MASTER_WINDOW3_2:0x0"  \
"PCIE_AXI_MASTER_WINDOW3_3:0x0"  \
"PCIE_AXI_SLAVE_WINDOW0_0:0x0"  \
"PCIE_AXI_SLAVE_WINDOW0_1:0x0"  \
"PCIE_AXI_SLAVE_WINDOW0_2:0x0"  \
"PCIE_AXI_SLAVE_WINDOW0_3:0x0"  \
"PCIE_AXI_SLAVE_WINDOW1_0:0x0"  \
"PCIE_AXI_SLAVE_WINDOW1_1:0x0"  \
"PCIE_AXI_SLAVE_WINDOW1_2:0x0"  \
"PCIE_AXI_SLAVE_WINDOW1_3:0x0"  \
"PCIE_AXI_SLAVE_WINDOW2_0:0x0"  \
"PCIE_AXI_SLAVE_WINDOW2_1:0x0"  \
"PCIE_AXI_SLAVE_WINDOW2_2:0x0"  \
"PCIE_AXI_SLAVE_WINDOW2_3:0x0"  \
"PCIE_AXI_SLAVE_WINDOW3_0:0x0"  \
"PCIE_AXI_SLAVE_WINDOW3_1:0x0"  \
"PCIE_AXI_SLAVE_WINDOW3_2:0x0"  \
"PCIE_AXI_SLAVE_WINDOW3_3:0x0"  \
"PCIE_BAR0:0xc"  \
"PCIE_BAR1:0x0"  \
"PCIE_BAR2:0xc"  \
"PCIE_BAR3:0x0"  \
"PCIE_BAR4:0xc"  \
"PCIE_BAR5:0x0"  \
"PCIE_CAPTURED_BUS_DEVICE_NB:0x0"  \
"PCIE_CFG_PMSCR:0x0"  \
"PCIE_CFG_PRMSCR:0x100000"  \
"PCIE_CLASS_CODE:0x0000"  \
"PCIE_CLASS_CODE_REG:0x0"  \
"PCIE_CLKREQ:0x0"  \
"PCIE_CREDIT_ALLOCATION_0:0x0"  \
"PCIE_CREDIT_ALLOCATION_1:0x0"  \
"PCIE_CREDIT_ALLOCATION_2:0x0"  \
"PCIE_CREDIT_ALLOCATION_3:0x0"  \
"PCIE_DEVICE_ID:0x1556"  \
"PCIE_ERROR_COUNTER_0:0x0"  \
"PCIE_ERROR_COUNTER_1:0x0"  \
"PCIE_ERROR_COUNTER_2:0x0"  \
"PCIE_ERROR_COUNTER_3:0x0"  \
"PCIE_INFO:0x0"  \
"PCIE_INTERUPT:INTx"  \
"PCIE_K_CNT_CONFIG_0:0x0"  \
"PCIE_K_CNT_CONFIG_1:0x0"  \
"PCIE_K_CNT_CONFIG_2:0x0"  \
"PCIE_K_CNT_CONFIG_3:0x0"  \
"PCIE_K_CNT_CONFIG_4:0x0"  \
"PCIE_K_CNT_CONFIG_5:0x0"  \
"PCIE_LTSSM:0x0"  \
"PCIE_MAX_PAYLOAD_SIZE:0x0"  \
"PCIE_MSI_0:0x0"  \
"PCIE_MSI_1:0x0"  \
"PCIE_MSI_2:0x0"  \
"PCIE_MSI_3:0x0"  \
"PCIE_MSI_4:0x0"  \
"PCIE_MSI_5:0x0"  \
"PCIE_MSI_6:0x0"  \
"PCIE_MSI_7:0x0"  \
"PCIE_MSI_CTRL_STATUS:0x0"  \
"PCIE_MSTR_WNDW_0:false"  \
"PCIE_MSTR_WNDW_0_BAR:BAR0"  \
"PCIE_MSTR_WNDW_0_LOC_ADD:0x0000"  \
"PCIE_MSTR_WNDW_0_PCIE_ADD:0x0000"  \
"PCIE_MSTR_WNDW_0_SIZE:KB4"  \
"PCIE_MSTR_WNDW_1:false"  \
"PCIE_MSTR_WNDW_1_BAR:BAR0"  \
"PCIE_MSTR_WNDW_1_LOC_ADD:0x0000"  \
"PCIE_MSTR_WNDW_1_PCIE_ADD:0x0000"  \
"PCIE_MSTR_WNDW_1_SIZE:KB4"  \
"PCIE_MSTR_WNDW_2:false"  \
"PCIE_MSTR_WNDW_2_BAR:BAR0"  \
"PCIE_MSTR_WNDW_2_LOC_ADD:0x0000"  \
"PCIE_MSTR_WNDW_2_PCIE_ADD:0x0000"  \
"PCIE_MSTR_WNDW_2_SIZE:KB4"  \
"PCIE_MSTR_WNDW_3:false"  \
"PCIE_MSTR_WNDW_3_BAR:BAR0"  \
"PCIE_MSTR_WNDW_3_LOC_ADD:0x0000"  \
"PCIE_MSTR_WNDW_3_PCIE_ADD:0x0000"  \
"PCIE_MSTR_WNDW_3_SIZE:KB4"  \
"PCIE_PCIE_CONFIG:0x0"  \
"PCIE_PCIE_DEV2SCR:0x0"  \
"PCIE_PCIE_DEVSCR:0x0"  \
"PCIE_PCIE_LINK2SCR:0x0"  \
"PCIE_PCIE_LINKSCR:0x50"  \
"PCIE_PM_DATA_SCALE_0:0x0"  \
"PCIE_PM_DATA_SCALE_1:0x0"  \
"PCIE_PM_DATA_SCALE_2:0x0"  \
"PCIE_PM_DATA_SCALE_3:0x0"  \
"PCIE_POWER_MGT_CAPABILITY:0x0"  \
"PCIE_PREFETCH_IO_WINDOW:0x0"  \
"PCIE_REVISION_ID:0x0000"  \
"PCIE_ROOTCSR:0x0"  \
"PCIE_SLOTCAP:0x0"  \
"PCIE_SLOTCLK:SLOT"  \
"PCIE_SLOTCSR:0x0"  \
"PCIE_SLV_WNDW_0:false"  \
"PCIE_SLV_WNDW_0_LOC_ADD:0x0000"  \
"PCIE_SLV_WNDW_0_NO_SNOOP:false"  \
"PCIE_SLV_WNDW_0_PCIE_ADD:0x0000"  \
"PCIE_SLV_WNDW_0_RLX_ORD:false"  \
"PCIE_SLV_WNDW_0_SIZE:KB4"  \
"PCIE_SLV_WNDW_0_TRAFFIC_CLASS:TC0"  \
"PCIE_SLV_WNDW_1:false"  \
"PCIE_SLV_WNDW_1_LOC_ADD:0x0000"  \
"PCIE_SLV_WNDW_1_NO_SNOOP:false"  \
"PCIE_SLV_WNDW_1_PCIE_ADD:0x0000"  \
"PCIE_SLV_WNDW_1_RLX_ORD:false"  \
"PCIE_SLV_WNDW_1_SIZE:KB4"  \
"PCIE_SLV_WNDW_1_TRAFFIC_CLASS:TC0"  \
"PCIE_SLV_WNDW_2:false"  \
"PCIE_SLV_WNDW_2_LOC_ADD:0x0000"  \
"PCIE_SLV_WNDW_2_NO_SNOOP:false"  \
"PCIE_SLV_WNDW_2_PCIE_ADD:0x0000"  \
"PCIE_SLV_WNDW_2_RLX_ORD:false"  \
"PCIE_SLV_WNDW_2_SIZE:KB4"  \
"PCIE_SLV_WNDW_2_TRAFFIC_CLASS:TC0"  \
"PCIE_SLV_WNDW_3:false"  \
"PCIE_SLV_WNDW_3_LOC_ADD:0x0000"  \
"PCIE_SLV_WNDW_3_NO_SNOOP:false"  \
"PCIE_SLV_WNDW_3_PCIE_ADD:0x0000"  \
"PCIE_SLV_WNDW_3_RLX_ORD:false"  \
"PCIE_SLV_WNDW_3_SIZE:KB4"  \
"PCIE_SLV_WNDW_3_TRAFFIC_CLASS:TC0"  \
"PCIE_SUB_DEVICE_ID:0x0000"  \
"PCIE_SUB_VENDOR_ID:0x0000"  \
"PCIE_SUBSYSTEM_ID:0x0"  \
"PCIE_TC_VC_MAPPING:0x0"  \
"PCIE_TIMEOUT_COMPLETION:0x0"  \
"PCIE_VC1_CAPABILITY:0x0"  \
"PCIE_VENDOR_ID:0x11AA"  \
"PCIE_VID_DEVID:0x11aa1556"  \
"PLL_CLKBASE_FREQ:20"  \
"PLL_LOCK_DELAY:1024"  \
"PLL_LOCK_WINDOW:8000"  \
"PLL_SUPPLY_VOLTAGE:25_V"  \
"PROTOCOL1_PHY_REF_CLK:REFCLK1"  \
"PROTOCOL1_PHY_REF_CLK_FREQ:125"  \
"PROTOCOL1_X1_LANE:1"  \
"PROTOCOL2_PHY_REF_CLK:REFCLK1"  \
"PROTOCOL2_PHY_REF_CLK_FREQ:125"  \
"PROTOCOL2_X1_LANE:2"  \
"SERDESIF_0_AVAILABLE:1"  \
"SERDESIF_1_AVAILABLE:0"  \
"SERDESIF_2_AVAILABLE:0"  \
"SERDESIF_3_AVAILABLE:0"  \
"SIGNAL_INTEGRITY_TEMPARATURE:50"  \
"SPEED_INFO:PCIe must be at GEN1 speed for this device"  \
"SYSTEM_CHIP_ENABLES:0x1"  \
"SYSTEM_CONF_AXI_MSTR_WNDW_0:0x0"  \
"SYSTEM_CONF_AXI_MSTR_WNDW_1:0x0"  \
"SYSTEM_CONF_AXI_MSTR_WNDW_2:0x0"  \
"SYSTEM_CONF_AXI_MSTR_WNDW_3:0x0"  \
"SYSTEM_CONF_AXI_SLV_WNDW_0:0x0"  \
"SYSTEM_CONF_AXI_SLV_WNDW_1:0x0"  \
"SYSTEM_CONF_AXI_SLV_WNDW_2:0x0"  \
"SYSTEM_CONF_AXI_SLV_WNDW_3:0x0"  \
"SYSTEM_CONFIG_AXI_AHB_BRIDGE:0x3"  \
"SYSTEM_CONFIG_BAR_SIZE_0_1:0x0"  \
"SYSTEM_CONFIG_BAR_SIZE_2_3:0x0"  \
"SYSTEM_CONFIG_BAR_SIZE_4_5:0x0"  \
"SYSTEM_CONFIG_ECC_INTR_ENABLE:0x77"  \
"SYSTEM_CONFIG_PCIE_0:0x0"  \
"SYSTEM_CONFIG_PCIE_1:0x0"  \
"SYSTEM_CONFIG_PCIE_2:0x0"  \
"SYSTEM_CONFIG_PCIE_3:0x0"  \
"SYSTEM_CONFIG_PCIE_PM:0x0"  \
"SYSTEM_CONFIG_PHY_MODE_0:0x0"  \
"SYSTEM_CONFIG_PHY_MODE_1:0xF0F"  \
"SYSTEM_CONFIG_PHY_MODE_2:0x0"  \
"SYSTEM_DEBUG_MODE_KEY:0x0"  \
"SYSTEM_DESKEW_CONFIG:0x0"  \
"SYSTEM_EPCS_RSTN_SEL:0x0"  \
"SYSTEM_PCLK_SEL:0x0"  \
"SYSTEM_RC_OSC_SPLL_REFCLK_SEL:0x1"  \
"SYSTEM_REFCLK_SEL:0x0"  \
"SYSTEM_RESERVED0:0x0"  \
"SYSTEM_RESERVED1:0x0"  \
"SYSTEM_RESERVED2:0x0"  \
"SYSTEM_RESERVED3:0x0"  \
"SYSTEM_RESERVED4:0x0"  \
"SYSTEM_SER_CLK_STATUS:0x0"  \
"SYSTEM_SER_INTERRUPT:0x0"  \
"SYSTEM_SER_INTERRUPT_ENABLE:0x0"  \
"SYSTEM_SER_PLL_CONFIG_HIGH:0x7F89"  \
"SYSTEM_SER_PLL_CONFIG_LOW:0x10082"  \
"SYSTEM_SER_SOFT_RESET:0x3F"  \
"SYSTEM_SERDES_FATC_RESET:0x1"  \
"SYSTEM_SERDES_TEST_OUT:0x0"  \
"SYSTEM_SERDESIF_INTR_STATUS:0x0"  \
"SYSTEM_SPREAD_SPECTRUM_CLK:0x0"  \
"TX_SWING_IS_USED:false"  \
"TYPE_OF_PROTOCOL1:EPCS"  \
"TYPE_OF_PROTOCOL2:EPCS"   }
# Exporting Component Description of SERDES_IF_C0 to TCL done
