//////////////////////////////////////////////////////////////////////
// Created by Actel SmartDesign Fri Jan 24 19:21:46 2014
// Testbench Template
// This is a basic testbench that instantiates your design with basic 
// clock and reset pins connected.  If your design has special
// clock/reset or testbench driver requirements then you should 
// copy this file and modify it. 
//////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

module testbench;

parameter SYSCLK_PERIOD = 20; // 50 MHz
parameter REFCLK_PERIOD = 8.0; // 125 MHz


reg SYSCLK;
reg REFCLK;
reg NSYSRESET;

wire L_P1;
wire L_N1;
wire L_P2;
wire L_N2;

initial
begin
    SYSCLK = 1'b0;
    REFCLK = 1'b0;
    NSYSRESET = 1'b0;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 2 )
        NSYSRESET = 1'b1;
end

initial
begin

  wait (top_0.EPCS_Demo_0.SDIF0_PWRITE==1'b1)
    wait (top_0.EPCS_Demo_0.SDIF0_PWRITE==1'b0) 
      $display("\nFinished SERDESIF Initialization\n");
  
  // Forcing INIT_DONE to save time in the simulation.  In the HW this is held longer to allow PLLs to stabilize
  #1_000 force top_0.EPCS_Demo_0.INIT_DONE=1'b1;
	 
  // Wait for the physical layer to come up, then start the checkers
  wait (top_0.CorePCS_C0_0.ALIGNED==1'b1)
    $display("\nSERDESIF Lane1 achieved word alignment\n");
  
  // Forcing the start which enables the checkers.  This is done in the demo using the GUI
  #10_000 force top_0.FabUART_0.start=1'b1;
  
  wait (top_0.prbs7_16_check_lane2.lock==1'b1)
    $display("\nChecker of Lane2 is locked to data pattern\n");  
	  
  wait (top_0.count_check_lane1.lock==1'b1)
    $display("\nChecker of Lane1 is locked to data pattern\n");  
	
  // Toggle the genrate_err which inserts an error into the transmit generator
  $display("\nInserting error into the transmit data streams\n");
  #10_000 force top_0.FabUART_0.genrate_err=1'b1;
  #500 force top_0.FabUART_0.genrate_err=1'b0;
  
  wait (top_0.prbs7_16_check_lane2.error_out==1'b1)
    $display("\nInserted error found by checker of Lane2\n");
  
  wait (top_0.count_check_lane1.error_out==1'b1)
    $display("\nInserted error found by checker of Lane1\n");

  #1_000 $finish;	
  

end



//////////////////////////////////////////////////////////////////////
// 10MHz Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

always @(REFCLK)
    #(REFCLK_PERIOD / 2.0) REFCLK <= !REFCLK;

//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  EPCS_Demo_top
//////////////////////////////////////////////////////////////////////
top top_0 (
    // Inputs
    .DEVRST_N(NSYSRESET),
    //.CLK0(SYSCLK),
    .RXD0_P({1{1'b0}}),
    .RXD0_N({1{1'b0}}),
    .RXD1_P(L_P1),
    .RXD1_N(L_N1),
    .RXD2_P(L_P2),
    .RXD2_N(L_N2),
    .RXD3_P({1{1'b0}}),
    .RXD3_N({1{1'b0}}),
    .RX({1{1'b0}}),
    .REFCLK1_P(REFCLK),
    .REFCLK1_N(!REFCLK),

    // Outputs
    .TXD0_P( ),
    .TXD0_N( ),
    .TXD1_P(L_P1),
    .TXD1_N(L_N1),
    .TXD2_P(L_P2),
    .TXD2_N(L_N2),
    .TXD3_P( ),
    .TXD3_N( ),
    .start( ),
    .connect_o( ),
    .TX( ),
    .switch( )

    // Inouts

);

endmodule

