#Build: Synplify Pro I-2013.09M-SP1-1 , Build 034R, Jan 17 2014
#install: \\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1
#OS: Windows 7 6.1
#Hostname: W764-ALIM

#Implementation: synthesis

$ Start of Compile
#Tue Jul 01 11:19:24 2014

Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\generic\smartfusion2.v"
@I::"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\vlog\umr_capim.v"
@I::"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\vlog\scemi_objects.v"
@I::"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\vlog\scemi_pipes.svh"
@I::"\\dm5\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\lib\vlog\hypermods.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\hdl\Count28.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss\CCC_0\my_mss_CCC_0_FCCC.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\SgCore\OSC\1.0.102\osc_comps.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss\FABOSC_0\my_mss_FABOSC_0_OSC.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss_MSS\my_mss_MSS_syn.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss_MSS\my_mss_MSS.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss\my_mss.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\my_mss_top\my_mss_top.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\hdl\mem_apb_wrp.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\SRAM_64x8\SRAM_64x8_0\SRAM_64x8_SRAM_64x8_0_TPSRAM.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\SRAM_64x8\SRAM_64x8.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\RAM_with_wrapper\RAM_with_wrapper.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\COREAHBTOAPB3\3.0.100\rtl\vlog\core_obfuscated\coreahbtoapb3_ahbtoapbsm.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\COREAHBTOAPB3\3.0.100\rtl\vlog\core_obfuscated\coreahbtoapb3_penablescheduler.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\COREAHBTOAPB3\3.0.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\COREAHBTOAPB3\3.0.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core\coreapb3_muxptob3.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core\coreapb3_iaddr_reg.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core\coreapb3.v"
@I::"D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\component\work\Top_M3_Master\Top_M3_Master.v"
@W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB
@W:CG775 : coreahbtoapb3.v(8) | Found Component COREAHBTOAPB3 in library COREAHBTOAPB3_LIB
@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
Verilog syntax check successful!
Selecting top level module Top_M3_Master
@W:CG775 : coreahbtoapb3.v(8) | Found Component COREAHBTOAPB3 in library COREAHBTOAPB3_LIB
@N:CG364 : coreahbtoapb3_ahbtoapbsm.v(8) | Synthesizing module CAHBtoAPB3O

@N:CG364 : coreahbtoapb3_penablescheduler.v(8) | Synthesizing module CAHBtoAPB3IOl

@N:CG364 : coreahbtoapb3_apbaddrdata.v(8) | Synthesizing module CAHBtoAPB3O1I

@N:CG364 : coreahbtoapb3.v(8) | Synthesizing module COREAHBTOAPB3

	FAMILY=32'b00000000000000000000000000010011
   Generated name = COREAHBTOAPB3_19s

@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3

@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	IADDR_OPTION=32'b00000000000000000000000000000000
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	MADDR_BITS=6'b011100
	UPR_NIBBLE_POSN=4'b0110
	IADDR_NOTINUSE=32'b00000000000000000000000000000000
	IADDR_EXTERNAL=32'b00000000000000000000000000000001
	IADDR_SLOT0=32'b00000000000000000000000000000010
	IADDR_SLOT1=32'b00000000000000000000000000000011
	IADDR_SLOT2=32'b00000000000000000000000000000100
	IADDR_SLOT3=32'b00000000000000000000000000000101
	IADDR_SLOT4=32'b00000000000000000000000000000110
	IADDR_SLOT5=32'b00000000000000000000000000000111
	IADDR_SLOT6=32'b00000000000000000000000000001000
	IADDR_SLOT7=32'b00000000000000000000000000001001
	IADDR_SLOT8=32'b00000000000000000000000000001010
	IADDR_SLOT9=32'b00000000000000000000000000001011
	IADDR_SLOT10=32'b00000000000000000000000000001100
	IADDR_SLOT11=32'b00000000000000000000000000001101
	IADDR_SLOT12=32'b00000000000000000000000000001110
	IADDR_SLOT13=32'b00000000000000000000000000001111
	IADDR_SLOT14=32'b00000000000000000000000000010000
	IADDR_SLOT15=32'b00000000000000000000000000010001
	SL0=16'b0000000000000001
	SL1=16'b0000000000000000
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
	SC=16'b0000000000000000
	SC_qual=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@W:CG360 : coreapb3.v(242) | No assignment to wire IA_PRDATA

@N:CG364 : Count28.v(3) | Synthesizing module counter28

@N:CG364 : smartfusion2.v(371) | Synthesizing module VCC

@N:CG364 : smartfusion2.v(367) | Synthesizing module GND

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

@N:CG364 : smartfusion2.v(722) | Synthesizing module CCC

@N:CG364 : my_mss_CCC_0_FCCC.v(5) | Synthesizing module my_mss_CCC_0_FCCC

@W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB
@N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000001
	MSB_ADDR=32'b00000000000000000000000000011011
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z2

@N:CG364 : coreahblite_defaultslavesm.v(29) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM

@N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000001
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_1_0_1_0

@N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState.
@N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011011
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3

@N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M_AHBSLOTENABLE=17'b00000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0

@N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState.
@N:CG364 : coreahblite_slavearbiter.v(28) | Synthesizing module COREAHBLITE_SLAVEARBITER

@N:CG364 : coreahblite_slavestage.v(30) | Synthesizing module COREAHBLITE_SLAVESTAGE

@N:CG364 : coreahblite_matrix4x16.v(31) | Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000000000000
	M0_AHBSLOTENABLE=17'b00000000000000001
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0

@N:CG364 : coreahblite.v(32) | Synthesizing module CoreAHBLite

	FAMILY=6'b010011
	MEMSPACE=3'b010
	HADDR_SHG_CFG=1'b1
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b1
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b0
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	M0_AHBSLOTENABLE=17'b00000000000000001
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000000000000
   Generated name = CoreAHBLite_Z4

@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z5

@W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] 

@W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] 

@W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] 

@W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] 

@W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc 

@W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable 

@W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable 

@W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable 

@W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable 

@W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable 

@N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset 

@W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int 

@W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base 

@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : my_mss_FABOSC_0_OSC.v(5) | Synthesizing module my_mss_FABOSC_0_OSC

@N:CG364 : my_mss_MSS_syn.v(5) | Synthesizing module MSS_010

@N:CG364 : my_mss_MSS.v(9) | Synthesizing module my_mss_MSS

@W:CG360 : my_mss_MSS.v(77) | No assignment to wire FIC_0_AHB_M_HTRANS_0

@N:CG364 : smartfusion2.v(713) | Synthesizing module SYSRESET

@N:CG364 : my_mss.v(9) | Synthesizing module my_mss

@N:CG364 : my_mss_top.v(9) | Synthesizing module my_mss_top

@N:CG364 : mem_apb_wrp.v(19) | Synthesizing module mem_apb_wrp

	DATA_WIDTH=32'b00000000000000000000000000001000
	ADDR_WIDTH=32'b00000000000000000000000000001000
   Generated name = mem_apb_wrp_8s_8s

@N:CG364 : smartfusion2.v(377) | Synthesizing module RAM1K18

@N:CG364 : SRAM_64x8_SRAM_64x8_0_TPSRAM.v(5) | Synthesizing module SRAM_64x8_SRAM_64x8_0_TPSRAM

@N:CG364 : SRAM_64x8.v(9) | Synthesizing module SRAM_64x8

@N:CG364 : RAM_with_wrapper.v(9) | Synthesizing module RAM_with_wrapper

@N:CG364 : Top_M3_Master.v(9) | Synthesizing module Top_M3_Master

@N:CL201 : mem_apb_wrp.v(78) | Trying to extract state machine for register fsm
Extracted state machine for register fsm
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : mem_apb_wrp.v(40) | Input PENABLE is unused
@W:CL157 : my_mss_MSS.v(56) | *Output FIC_0_AHB_M_HTRANS has undriven bits -- simulation mismatch possible.
@W:CL157 : my_mss_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : my_mss_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W:CL157 : my_mss_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : my_mss_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W:CL159 : my_mss_FABOSC_0_OSC.v(14) | Input XTL is unused
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
@W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
@W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
@W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
@W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
@W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
@W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
@W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
@W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
@W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
@W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
@W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
@W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
@W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
@W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused
@W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused
@W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused
@W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused
@W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused
@W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused
@W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused
@W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused
@W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused
@W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused
@W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused
@W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused
@W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused
@W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused
@W:CL247 : coreahblite.v(128) | Input port bit 0 of HTRANS_M0[1:0] is unused

@W:CL247 : coreahblite.v(139) | Input port bit 0 of HTRANS_M1[1:0] is unused

@W:CL247 : coreahblite.v(150) | Input port bit 0 of HTRANS_M2[1:0] is unused

@W:CL247 : coreahblite.v(161) | Input port bit 0 of HTRANS_M3[1:0] is unused

@W:CL247 : coreahblite.v(171) | Input port bit 1 of HRESP_S0[1:0] is unused

@W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S1[1:0] is unused

@W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S2[1:0] is unused

@W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S3[1:0] is unused

@W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S4[1:0] is unused

@W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S5[1:0] is unused

@W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S6[1:0] is unused

@W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S7[1:0] is unused

@W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S8[1:0] is unused

@W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S9[1:0] is unused

@W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S10[1:0] is unused

@W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S11[1:0] is unused

@W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S12[1:0] is unused

@W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S13[1:0] is unused

@W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S14[1:0] is unused

@W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S15[1:0] is unused

@W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S16[1:0] is unused

@W:CL159 : coreahblite.v(131) | Input HBURST_M0 is unused
@W:CL159 : coreahblite.v(132) | Input HPROT_M0 is unused
@W:CL159 : coreahblite.v(142) | Input HBURST_M1 is unused
@W:CL159 : coreahblite.v(143) | Input HPROT_M1 is unused
@W:CL159 : coreahblite.v(153) | Input HBURST_M2 is unused
@W:CL159 : coreahblite.v(154) | Input HPROT_M2 is unused
@W:CL159 : coreahblite.v(164) | Input HBURST_M3 is unused
@W:CL159 : coreahblite.v(165) | Input HPROT_M3 is unused
@W:CL159 : coreahblite_matrix4x16.v(58) | Input HWDATA_M1 is unused
@W:CL159 : coreahblite_matrix4x16.v(67) | Input HWDATA_M2 is unused
@W:CL159 : coreahblite_matrix4x16.v(76) | Input HWDATA_M3 is unused
@W:CL159 : coreahblite_matrix4x16.v(91) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(92) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(93) | Input HRESP_S1 is unused
@W:CL159 : coreahblite_matrix4x16.v(102) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(103) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(104) | Input HRESP_S2 is unused
@W:CL159 : coreahblite_matrix4x16.v(113) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(114) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(115) | Input HRESP_S3 is unused
@W:CL159 : coreahblite_matrix4x16.v(124) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(125) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(126) | Input HRESP_S4 is unused
@W:CL159 : coreahblite_matrix4x16.v(135) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(136) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(137) | Input HRESP_S5 is unused
@W:CL159 : coreahblite_matrix4x16.v(146) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(147) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(148) | Input HRESP_S6 is unused
@W:CL159 : coreahblite_matrix4x16.v(157) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(158) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(159) | Input HRESP_S7 is unused
@W:CL159 : coreahblite_matrix4x16.v(168) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(169) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(170) | Input HRESP_S8 is unused
@W:CL159 : coreahblite_matrix4x16.v(179) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(180) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(181) | Input HRESP_S9 is unused
@W:CL159 : coreahblite_matrix4x16.v(190) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(191) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(192) | Input HRESP_S10 is unused
@W:CL159 : coreahblite_matrix4x16.v(201) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(202) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(203) | Input HRESP_S11 is unused
@W:CL159 : coreahblite_matrix4x16.v(212) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(213) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(214) | Input HRESP_S12 is unused
@W:CL159 : coreahblite_matrix4x16.v(223) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(224) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(225) | Input HRESP_S13 is unused
@W:CL159 : coreahblite_matrix4x16.v(234) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(235) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(236) | Input HRESP_S14 is unused
@W:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S15 is unused
@W:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S15 is unused
@W:CL159 : coreahblite_matrix4x16.v(256) | Input HRDATA_S16 is unused
@W:CL159 : coreahblite_matrix4x16.v(257) | Input HREADYOUT_S16 is unused
@W:CL159 : coreahblite_matrix4x16.v(258) | Input HRESP_S16 is unused
@W:CL246 : coreahblite_slavestage.v(46) | Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused

@N:CL201 : coreahblite_slavearbiter.v(452) | Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W:CL159 : coreahblite_masterstage.v(50) | Input SDATAREADY is unused
@W:CL159 : coreahblite_masterstage.v(51) | Input SHRESP is unused
@W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused
@W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused
@W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused
@W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused
@W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused
@W:CL246 : coreahblite_masterstage.v(50) | Input port bits 16 to 1 of SDATAREADY[16:0] are unused

@W:CL246 : coreahblite_masterstage.v(51) | Input port bits 16 to 1 of SHRESP[16:0] are unused

@W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused
@W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused
@W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused
@W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused
@W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused
@W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused
@W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused
@W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused
@W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused
@W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused
@W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused
@W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused
@W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused
@W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused
@W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused
@W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused
@W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused
@W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused
@W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused
@W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused
@W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused
@W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused
@W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused
@W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused
@W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused
@W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused
@W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused
@W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused
@W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused
@W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused
@W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused
@W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused
@W:CL159 : coreapb3.v(70) | Input IADDR is unused
@W:CL159 : coreapb3.v(71) | Input PRESETN is unused
@W:CL159 : coreapb3.v(72) | Input PCLK is unused
@W:CL159 : coreapb3.v(103) | Input PRDATAS1 is unused
@W:CL159 : coreapb3.v(104) | Input PRDATAS2 is unused
@W:CL159 : coreapb3.v(105) | Input PRDATAS3 is unused
@W:CL159 : coreapb3.v(106) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(107) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(108) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(109) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(110) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(111) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(112) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(113) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(114) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(115) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(116) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(117) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(120) | Input PREADYS1 is unused
@W:CL159 : coreapb3.v(121) | Input PREADYS2 is unused
@W:CL159 : coreapb3.v(122) | Input PREADYS3 is unused
@W:CL159 : coreapb3.v(123) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(124) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(125) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(126) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(127) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(128) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(129) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(130) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(131) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(132) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(133) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(134) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(137) | Input PSLVERRS1 is unused
@W:CL159 : coreapb3.v(138) | Input PSLVERRS2 is unused
@W:CL159 : coreapb3.v(139) | Input PSLVERRS3 is unused
@W:CL159 : coreapb3.v(140) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(141) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(142) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(143) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(144) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(145) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(146) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(147) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(148) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(149) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(150) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(151) | Input PSLVERRS15 is unused
@W:CL247 : coreahbtoapb3.v(40) | Input port bit 0 of HTRANS[1:0] is unused

@N:CL201 : coreahbtoapb3_penablescheduler.v(152) | Trying to extract state machine for register CAHBtoAPB3OIl
Extracted state machine for register CAHBtoAPB3OIl
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : coreahbtoapb3_ahbtoapbsm.v(646) | Trying to extract state machine for register CAHBtoAPB3IOI
Extracted state machine for register CAHBtoAPB3IOI
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@END

At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jul 01 11:19:25 2014

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 004R, Built May 28 2014 16:50:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Linked File: Top_M3_Master_scck.rpt
Printing clock  summary report in "D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\synthesis\Top_M3_Master_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)

@W:BN132 : coreahblite_matrix4x16.v(3612) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_16,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_15
@W:BN132 : coreahblite_matrix4x16.v(3567) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W:BN132 : coreahblite_matrix4x16.v(3522) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W:BN132 : coreahblite_matrix4x16.v(3477) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W:BN132 : coreahblite_matrix4x16.v(3432) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W:BN132 : coreahblite_matrix4x16.v(3387) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3297) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3252) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3207) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3162) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3117) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3072) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3027) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_3,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W:BN132 : coreahblite_matrix4x16.v(3342) | Removing user instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_1
@W:BN132 : coreresetp.v(1089) | Removing sequential instance my_mss_top_0.my_mss_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance my_mss_top_0.my_mss_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2708) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2771) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2834) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_matrix4x16.v(2937) | Removing instance slavestage_1 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance sm0_state[6:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_1(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN115 : coreahblite_slavestage.v(90) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1581) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1549) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1517) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1485) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1613) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_1_0_1_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=21  set on top level netlist Top_M3_Master


Clock Summary
**************

Start                                        Requested     Requested     Clock        Clock              
Clock                                        Frequency     Period        Type         Group              
---------------------------------------------------------------------------------------------------------
System                                       1.0 MHz       1000.000      system       system_clkgroup    
my_mss_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
=========================================================================================================

@W:MT530 : coreahbtoapb3_ahbtoapbsm.v(786) | Found inferred clock my_mss_CCC_0_FCCC|GL0_net_inferred_clock which controls 269 sequential elements including COREAHBTOAPB3_0.CAHBtoAPB3Oll.HREADYOUT. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\synthesis\Top_M3_Master.sap. 
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jul 01 11:19:28 2014

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 004R, Built May 28 2014 16:50:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

@W:MO111 : my_mss_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module my_mss_FABOSC_0_OSC) 
@W:MO111 : my_mss_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module my_mss_FABOSC_0_OSC) 
@W:MO111 : my_mss_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module my_mss_FABOSC_0_OSC) 
@W:MO111 : my_mss_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module my_mss_FABOSC_0_OSC) 
@W:MO111 : my_mss_mss.v(56) | Tristate driver FIC_0_AHB_M_HTRANS_1 on net FIC_0_AHB_M_HTRANS_1 has its enable tied to GND (module my_mss_MSS) 
@W:MO111 :  | Tristate driver my_mss_MSS_0_FIC_0_AHB_MASTER_HTRANS_t[0] on net my_mss_MSS_0_FIC_0_AHB_MASTER_HTRANS[0] has its enable tied to GND (module my_mss)  
@W:MO171 : coreresetp.v(769) | Sequential instance my_mss_top_0.my_mss_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W:MO171 : coreresetp.v(769) | Sequential instance my_mss_top_0.my_mss_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W:MO171 : coreresetp.v(1388) | Sequential instance my_mss_top_0.my_mss_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[8] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[9] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[10] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[11] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[12] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[13] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[14] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[15] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[16] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[17] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[18] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[19] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[20] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[21] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[22] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[23] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[28] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[29] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[30] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(105) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3I1I[31] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[8] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[9] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[10] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[11] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[12] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[13] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[14] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[15] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[16] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[17] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[18] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[19] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[20] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[21] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[22] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[23] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[24] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[25] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[26] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[27] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[28] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[29] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[30] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(220) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3OOl[31] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[31],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[30]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[30],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[29]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[29],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[28]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[28],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[27]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[27],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[26]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[26],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[25]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[25],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[24]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[24],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[23]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[23],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[22]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[22],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[21]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[21],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[20]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[20],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[19]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[19],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[18]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[18],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[17]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[17],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[16]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[16],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[15]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[15],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[14]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[14],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[13]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[13],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[12]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[12],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[11]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[11],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[10]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[9],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[10]
@W:BN132 : coreahbtoapb3_apbaddrdata.v(285) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[8],  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[10]
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[8] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[9] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[10] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[11] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[12] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[13] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[14] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[15] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[16] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[17] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[18] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[19] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[20] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[21] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[22] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[23] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[28] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[29] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[30] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(178) | Removing sequential instance CAHBtoAPB3lll.CAHBtoAPB3l1I[31] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
@N:BN362 : coreahbtoapb3_apbaddrdata.v(285) | Removing sequential instance CAHBtoAPB3lll.HRDATA[10] in hierarchy view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s(verilog) because there are no references to its outputs 
Encoding state machine CAHBtoAPB3IOI[4:0] (view:COREAHBTOAPB3_LIB.CAHBtoAPB3O(verilog))
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
@W:BN132 : coreahbtoapb3_ahbtoapbsm.v(646) | Removing sequential instance COREAHBTOAPB3_0.CAHBtoAPB3Oll.PWRITE,  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI[2]
Encoding state machine CAHBtoAPB3OIl[2:0] (view:COREAHBTOAPB3_LIB.CAHBtoAPB3IOl(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W:BN132 : coreahbtoapb3_penablescheduler.v(152) | Removing instance COREAHBTOAPB3_0.CAHBtoAPB3Ill.PENABLE,  because it is equivalent to instance COREAHBTOAPB3_0.CAHBtoAPB3Ill.CAHBtoAPB3OIl[1]
@N: : count28.v(16) | Found counter in view:work.counter28(verilog) inst cnt[27:0]
@N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] in hierarchy view:work.my_mss(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] in hierarchy view:work.my_mss(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] in hierarchy view:work.my_mss(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] in hierarchy view:work.my_mss(verilog) because there are no references to its outputs 
@W:BN132 : coreahblite_masterstage.v(167) | Removing instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[25],  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24]
@W:BN132 : coreahblite_masterstage.v(167) | Removing instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26],  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24]
@W:BN132 : coreahblite_masterstage.v(167) | Removing instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27],  because it is equivalent to instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24]
Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
Encoding state machine fsm[3:0] (view:work.mem_apb_wrp_8s_8s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[8] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[9] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[10] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[11] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[12] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[13] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[14] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[15] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 
@N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] in hierarchy view:work.Top_M3_Master(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 139MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 140MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -8.62ns		 232 /       137
------------------------------------------------------------

@N:FX271 : coreresetp.v(565) | Instance "my_mss_top_0.my_mss_0.CORERESETP_0.MSS_HPMS_READY_int" with 13 loads replicated 1 times to improve timing 
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -8.40ns		 233 /       138
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -8.40ns		 233 /       138
------------------------------------------------------------

@N:FP130 :  | Promoting Net MSS_READY_c on CLKINT  I_20  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 148MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 148MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 141 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

======================================================= Non-Gated/Non-Generated Clocks =======================================================
Clock Tree ID     Driving Element                          Drive Element Type     Fanout     Sample Instance                                  
----------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        my_mss_top_0.my_mss_0.CCC_0.GL0_INST     CLKINT                 141        my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST
==============================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\Appsnotes\2014\Tamper\zerioze\MSS_MSTR_RAM_INIT\synthesis\Top_M3_Master.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 137MB peak: 148MB)

Writing EDIF Netlist and constraint files
@N:BW103 :  | Synopsys Constraint File time units using default value of 1ns  
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
I-2013.09M-SP1-1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 137MB peak: 148MB)

@W:MT246 : my_mss.v(812) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : my_mss_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock my_mss_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_mss_top_0.my_mss_0.CCC_0.GL0_net" 



##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jul 01 11:19:33 2014
#


Top view:               Top_M3_Master
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary 
*******************


Worst slack in design: 1.388

                                             Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                               Frequency     Frequency      Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------
my_mss_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     116.1 MHz      10.000        8.612         1.388     inferred     Inferred_clkgroup_0
System                                       100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                  Ending                                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                    System                                    |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
System                                    my_mss_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      8.526  |  No paths    -      |  No paths    -      |  No paths    -    
my_mss_CCC_0_FCCC|GL0_net_inferred_clock  System                                    |  10.000      8.924  |  No paths    -      |  No paths    -      |  No paths    -    
my_mss_CCC_0_FCCC|GL0_net_inferred_clock  my_mss_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      1.388  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: my_mss_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                                                Arrival          
Instance                                                                         Reference                                    Type        Pin                Net                                         Time        Slack
                                                                                 Clock                                                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_TRANS1       my_mss_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]     3.019       1.388
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[26]     my_mss_MSS_0_FIC_0_AHB_MASTER_HADDR[26]     3.098       1.714
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[24]     my_mss_MSS_0_FIC_0_AHB_MASTER_HADDR[24]     3.012       1.824
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[25]     my_mss_MSS_0_FIC_0_AHB_MASTER_HADDR[25]     2.882       2.005
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_ADDR[27]     my_mss_MSS_0_FIC_0_AHB_MASTER_HADDR[27]     3.008       2.139
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                my_mss_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_HM0_WRITE        my_mss_MSS_0_FIC_0_AHB_MASTER_HWRITE        2.976       2.719
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3]      my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[3]                              0.094       2.875
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9]      my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[9]                              0.094       3.059
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1]      my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[1]                              0.076       3.079
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[13]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[13]                             0.094       3.126
==========================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                   Starting                                                                                Required          
Instance                                           Reference                                    Type     Pin     Net                       Time         Slack
                                                   Clock                                                                                                     
-------------------------------------------------------------------------------------------------------------------------------------------------------------
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI[3]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       N_91_i_0                  9.778        1.388
COREAHBTOAPB3_0.CAHBtoAPB3Oll.HREADYOUT            my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       HREADYOUT_N_5_mux_i_0     9.778        1.697
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[4]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[4]        9.848        1.815
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[1]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[1]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[2]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[2]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[3]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[3]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[5]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[5]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[6]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[6]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3I1I[7]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3I1I_5[7]        9.778        1.964
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI[1]     my_mss_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       CAHBtoAPB3IOI_ns[1]       9.778        1.976
=============================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.778

    - Propagation time:                      8.390
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.388

    Number of logic level(s):                6
    Starting point:                          my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST / F_HM0_TRANS1
    Ending point:                            COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI[3] / D
    The start point is clocked by            my_mss_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            my_mss_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                                       Pin              Pin               Arrival     No. of    
Name                                                                                                                     Type        Name             Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
my_mss_top_0.my_mss_0.my_mss_MSS_0.MSS_ADLIB_INST                                                                        MSS_010     F_HM0_TRANS1     Out     3.019     3.019       -         
my_mss_MSS_0_FIC_0_AHB_MASTER_HTRANS[1]                                                                                  Net         -                -       0.983     -           5         
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.GATEDHTRANS                                                 CFG3        B                In      -         4.002       -         
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.GATEDHTRANS                                                 CFG3        Y                Out     0.143     4.145       -         
M0GATEDHTRANS                                                                                                            Net         -                -       0.548     -           2         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3Il_m2_e_0_0_0                                                                    CFG4        B                In      -         4.693       -         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3Il_m2_e_0_0_0                                                                    CFG4        Y                Out     0.143     4.836       -         
CAHBtoAPB3I1I_m3_0_a2_0                                                                                                  Net         -                -       0.802     -           16        
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_0_RNI6N7E2[0]     CFG4        C                In      -         5.638       -         
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_0_RNI6N7E2[0]     CFG4        Y                Out     0.182     5.821       -         
arbRegSMCurrentState_ns_i_a2_0_RNI6N7E2[0]                                                                               Net         -                -       0.722     -           9         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO_1[3]                                                                     CFG4        B                In      -         6.542       -         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO_1[3]                                                                     CFG4        Y                Out     0.133     6.675       -         
N_91_i_1                                                                                                                 Net         -                -       0.483     -           1         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO_0[3]                                                                     CFG4        D                In      -         7.158       -         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO_0[3]                                                                     CFG4        Y                Out     0.411     7.569       -         
N_91_i_1_0                                                                                                               Net         -                -       0.483     -           1         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO[3]                                                                       CFG4        C                In      -         8.052       -         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI_RNO[3]                                                                       CFG4        Y                Out     0.200     8.252       -         
N_91_i_0                                                                                                                 Net         -                -       0.138     -           1         
COREAHBTOAPB3_0.CAHBtoAPB3Oll.CAHBtoAPB3IOI[3]                                                                           SLE         D                In      -         8.390       -         
==============================================================================================================================================================================================
Total path delay (propagation time + setup) of 8.612 is 4.453(51.7%) logic and 4.160(48.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                    Arrival          
Instance                                                                         Reference     Type        Pin           Net                                 Time        Slack
                                                                                 Clock                                                                                        
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[0]     CoreAPB3_0_APBmslave0_PRDATA[0]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[0]     CoreAPB3_0_APBmslave0_PRDATA[0]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[1]     CoreAPB3_0_APBmslave0_PRDATA[1]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[1]     CoreAPB3_0_APBmslave0_PRDATA[1]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[2]     CoreAPB3_0_APBmslave0_PRDATA[2]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[2]     CoreAPB3_0_APBmslave0_PRDATA[2]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[3]     CoreAPB3_0_APBmslave0_PRDATA[3]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[3]     CoreAPB3_0_APBmslave0_PRDATA[3]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[4]     CoreAPB3_0_APBmslave0_PRDATA[4]     0.000       8.526
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0     System        RAM1K18     A_DOUT[4]     CoreAPB3_0_APBmslave0_PRDATA[4]     0.000       8.526
==============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                                                                         Required          
Instance                                    Reference     Type     Pin                Net                                                    Time         Slack
                                            Clock                                                                                                              
---------------------------------------------------------------------------------------------------------------------------------------------------------------
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[0]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[0]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[1]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[1]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[2]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[2]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[3]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[3]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[4]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[4]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[5]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[5]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[6]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[6]                      9.778        8.526
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[7]     System        SLE      D                  CoreAPB3_0_APBmslave0_PRDATA_m[7]                      9.778        8.526
my_mss_top_0.my_mss_0.CCC_0.CCC_INST        System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       9.029
===============================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.778

    - Propagation time:                      1.252
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.526

    Number of logic level(s):                1
    Starting point:                          RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0 / A_DOUT[0]
    Ending point:                            COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[0] / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            my_mss_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                                 Pin           Pin               Arrival     No. of    
Name                                                                                               Type        Name          Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
RAM_with_wrapper_0.SRAM_64x8_0.SRAM_64x8_0.SRAM_64x8_SRAM_64x8_0_TPSRAM_R0C0                       RAM1K18     A_DOUT[0]     Out     0.000     0.000       -         
CoreAPB3_0_APBmslave0_PRDATA[0]                                                                    Net         -             -       0.971     -           1         
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.CoreAPB3_0_APBmslave0_PRDATA_m[0]     CFG3        B             In      -         0.971       -         
my_mss_top_0.my_mss_0.CoreAHBLite_0.matrix4x16.masterstage_0.CoreAPB3_0_APBmslave0_PRDATA_m[0]     CFG3        Y             Out     0.143     1.115       -         
CoreAPB3_0_APBmslave0_PRDATA_m[0]                                                                  Net         -             -       0.138     -           1         
COREAHBTOAPB3_0.CAHBtoAPB3lll.HRDATA[0]                                                            SLE         D             In      -         1.252       -         
=====================================================================================================================================================================
Total path delay (propagation time + setup) of 1.474 is 0.365(24.8%) logic and 1.109(75.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for Top_M3_Master 

Mapping to part: m2s010tsfbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
SYSRESET        1 use
CFG1           2 uses
CFG2           54 uses
CFG3           57 uses
CFG4           81 uses

Carry primitives used for arithmetic functions:
ARI1           35 uses


Sequential Cells: 
SLE            138 uses

DSP Blocks:    0

I/O ports: 11
I/O primitives: 10
INBUF          1 use
OUTBUF         9 uses


Global Clock Buffers: 2


RAM/ROM usage summary
Block Rams (RAM1K18) : 1

Total LUTs:    229

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 51MB peak: 148MB)

Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Tue Jul 01 11:19:33 2014

###########################################################]