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!s101 -O0
vRAM_with_wrapper_TPSRAM_0_TPSRAM
I=AhMME3i46FEQ<DFXGO2D2
V05l`iT`f4NT;4U<?HS<^T0
R1
R2
R3
R4
L0 1610
R5
r1
31
R6
R7
R8
R9
n@r@a@m_with_wrapper_@t@p@s@r@a@m_0_@t@p@s@r@a@m
!s100 `zDJK;JT`<<ezY:KmOVe^2
!i10b 1
!s85 0
!s101 -O0
vRCOSC_25_50MHZ
IEB6lm8;BLB89GKKK<JfdW1
R11
R12
R13
R14
R15
L0 5
R16
r1
31
R17
R18
R19
R9
n@r@c@o@s@c_25_50@m@h@z
!s110 1397578361
!i10b 1
!s100 ^A6>TEA`k35j9GnzlC]7^0
!s85 0
!s101 -O0
vRESET_GEN
R10
IGlTBC6HFQQd9>IR5Bk60Y3
R11
R12
R20
8E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v
FE:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v
L0 3
R16
r1
31
R9
R21
n@r@e@s@e@t_@g@e@n
!i10b 1
!s100 b3IJeIYIQB4f2^K0:lmF>2
!s85 0
!s108 1397578362.595000
!s107 E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v|
!s90 -reportprogress|300|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/CLK_GEN/1.0.1|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/work/my_testbench|-work|postsynth|E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v|
!s101 -O0
vTop
ITG0jK6994jP363Q;Z[QRB3
VH4?82C[`jna?^HjPh75NO2
R1
R2
R3
R4
L0 5178
R5
r1
31
R6
R7
R8
R9
n@top
!s100 zJgSh5lnzYn741AgRWXa92
!i10b 1
!s85 0
!s101 -O0
vTop_CCC_0_FCCC
IMcL<VgjWB9bMbkJcC:aaY1
V:iML0[2oLKh_eUYX9MINH3
R1
R2
R3
R4
L0 4388
R5
r1
31
R6
R7
R8
R9
n@top_@c@c@c_0_@f@c@c@c
!s100 PdYZ3;MRJGDcfjY0J^G4n3
!i10b 1
!s85 0
!s101 -O0
vTop_M3_Master
R10
I9Y4SY7[QRFHza7Waj;0YR0
R11
R12
R13
R14
R15
L0 5292
R16
r1
31
R17
R18
R19
R9
n@top_@m3_@master
!i10b 1
!s100 az^12>ORL>9=zJ]`VnXhc3
!s85 0
!s101 -O0
vTop_OSC_0_OSC
IbM92bP9MN4eH??LdmkgTc1
V9@]WIFmkFF=]]mXLE7mYi0
R1
R2
R3
R4
L0 1833
R5
r1
31
R6
R7
R8
R9
n@top_@o@s@c_0_@o@s@c
!s100 _lC5k6W`?Q2UdB0MGVoO=2
!i10b 1
!s85 0
!s101 -O0
vuser_rd_wr
R10
I]6nlOG8eQ<3njz^@LazjJ1
R11
R12
w1369141484
8E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus/user_rd_wr.v
FE:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus/user_rd_wr.v
L0 4
R16
r1
31
R9
R21
!i10b 1
!s100 fNhSOG91hf0PjgWk8h>J91
!s85 0
!s108 1397578362.658000
!s107 E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus/user_rd_wr.v|
!s90 -reportprogress|300|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/CLK_GEN/1.0.1|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/Actel/Simulation/RESET_GEN/1.0.1|+incdir+E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/component/work/my_testbench|-work|postsynth|E:/Microsemi_prj/AC392_SRAM_Init/RAM_INIT_FROM_MSS/MSS_MSTR_RAM_INIT/stimulus/user_rd_wr.v|
!s101 -O0
