#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: SJSOC0507 # Fri Mar 24 18:14:38 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\igloo2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\hdl\message_blk.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\hdl\my_sysservice_state.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_AHBLMasterIF.v" (library CORESYSSERVICES_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_CmdDec.v" (library CORESYSSERVICES_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_FSMCtrl.v" (library CORESYSSERVICES_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CORESYSSERVICES\3.1.101\rtl\vlog\core\CoreSysServices_UserIF.v" (library CORESYSSERVICES_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\Coresys_Ctrl_blk\CORESYSSERVICES_0\rtl\vlog\core\CoreSysServices.v" (library CORESYSSERVICES_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\Coresys_Ctrl_blk\Coresys_Ctrl_blk.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\hdl\Hex_to_ascii.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\hdl\APB_register_blk.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\acmtable.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v" (library work) @I:"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\debugblk.v":"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\support.v" (library work) @N:CG334 : debugblk.v(68) | Read directive translate_off. @N:CG333 : debugblk.v(745) | Read directive translate_on. @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\instructions.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\instructnvm_bb.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\iram512x9_rtl.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\instructram.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\ram128x8_smartfusion2.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x16_rtl.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\ram256x8_rtl.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\ramblocks.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\COREABC_0\rtl\vlog\core\coreabc.v" (library work) @N:CG334 : coreabc.v(982) | Read directive translate_off. @N:CG333 : coreabc.v(984) | Read directive translate_on. @N:CG334 : coreabc.v(1379) | Read directive translate_off. @N:CG333 : coreabc.v(1423) | Read directive translate_on. @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\Clock_gen.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\Rx_async.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\Tx_async.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\fifo_256x8.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\CoreUART.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\CoreUARTapb_0\rtl\vlog\core\CoreUARTapb.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\UART_top\UART_top.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms\CCC_0\my_hpms_CCC_0_FCCC.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms\FABOSC_0\my_hpms_FABOSC_0_OSC.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms_HPMS\my_hpms_HPMS_syn.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms_HPMS\my_hpms_HPMS.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms\my_hpms.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\my_hpms_top\my_hpms_top.v" (library work) @I::"C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\component\work\Top\Top.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module Top @W:CG775 : CoreSysServices.v(30) | Found Component Coresys_Ctrl_blk_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB @N:CG364 : CoreSysServices_UserIF.v(30) | Synthesizing module CoreSysServices_UserIF in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000001 CRYPTOAES128DATAPTR=32'b00100000000000000001000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000010000000000000 CRYPTODSTADPTR=32'b00100000000000000011000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = CoreSysServices_UserIF_Z1 @W:CL169 : CoreSysServices_UserIF.v(789) | Pruning unused register cuhprior_flushdone_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(738) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(592) | Pruning unused register custatus_out_en_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_UserIF.v(522) | Pruning unused register pord_comb_d1. Make sure that there are no unused intermediate registers. @W:CL207 : CoreSysServices_UserIF.v(719) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL190 : CoreSysServices_UserIF.v(505) | Optimizing register bit hprior_kp_busy_high to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit uclatchoptions_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_UserIF.v(653) | Optimizing register bit ucmdbyte_req_hold[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 5 to 2 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 0 of uclatchoptions_hold[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 7 to 5 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_UserIF.v(653) | Pruning register bit 3 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_UserIF.v(653) | Pruning register bits 1 to 0 of ucmdbyte_req_hold[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : CoreSysServices_UserIF.v(505) | Pruning unused register hprior_kp_busy_high. Make sure that there are no unused intermediate registers. @N:CG364 : igloo2.v(835) | Synthesizing module FLASH_FREEZE in library work. @N:CG364 : CoreSysServices_CmdDec.v(30) | Synthesizing module CoreSysServices_CmdDec in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000001 CRYPTOAES128DATAPTR=32'b00100000000000000001000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000010000000000000 CRYPTODSTADPTR=32'b00100000000000000011000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 C_IDLE=2'b00 C_REQ_PHASE=2'b01 C_RESP_PHASE=2'b10 REQ_IDLE=6'b000000 REQ_WAIT_MEMWR1=6'b000001 REQ_MEMWR_DESC=6'b000010 REQ_WAIT_MEMWR2=6'b000011 REQ_MEMWR_DATA=6'b000100 REQ_PHASE=6'b000101 REQ_FIIC_INT=6'b000111 REQ_POLL_CINT1=6'b001000 REQ_RDCOMM_STATUS1=6'b001001 REQ_WRCOMM_CTRL=6'b001010 REQ_WRCOMM_INT=6'b001011 REQ_WRCOMM_FRM=6'b001100 REQ_WRCOMM_DATA=6'b001101 REQ_POLL_CINT2=6'b001110 REQ_RDCOMM_STATUS2=6'b001111 REQ_WAIT_REG1=6'b010000 REQ_WAIT_REG2=6'b010001 REQ_WAIT_REG3=6'b010010 REQ_WAIT_REG4=6'b010011 REQ_WAIT_REG5=6'b010100 REQ_WAIT_REG6=6'b010101 REQ_WAIT_REG7=6'b010110 REQ_WAIT_REG8=6'b010111 REQ_WAIT_REG9=6'b011000 REQ_RD_INT=6'b011011 REQ_RDCOMM_INT=6'b011100 REQ_WAIT_REG10=6'b100001 REQ_WAIT_REG11=6'b100010 REQ_WAIT_REG12=6'b100011 REQ_WAIT_REG13=6'b100100 REQ_WRCOMM_CTRL2=6'b100101 REQ_WRCOMM_CTRL3=6'b100110 REQ_WRCOMM_CTRL4=6'b100111 REQ_WRCOMM_INT2=6'b101000 REQ_WAIT_MEMWR22=6'b101001 REQ_MEMWR_DATA1=6'b101010 REQ_WAIT_ASYNCRD1=6'b101011 REQ_RDCOMM_ASYNCFRM1=6'b101100 REQ_WAIT_ASYNCRD2=6'b101101 REQ_RDCOMM_ASYNCFRM2=6'b101110 REQ_ASYNC_OUT1=6'b110000 REQ_ASYNC_OUT2=6'b110001 REQ_WAIT_REG14=6'b110010 REQ_WRCOMM_DESC2=6'b110011 REQ_WAIT_REG15=6'b110100 RESP_IDLE=6'b000000 RESP_PHASE=6'b000001 RESP_RDCOMM_STATUS=6'b000011 RESP_RDCOMM_FRM=6'b000100 RESP_RDCOMM_DESC=6'b000101 RESP_RDCOMM_DATA=6'b000110 RESP_WAIT_MEMRD=6'b000111 RESP_MEMRD=6'b001000 RESP_POLL_CINT1=6'b001001 RESP_POLL_CINT4=6'b001100 RESP_REG1=6'b001101 RESP_REG4=6'b010000 RESP_REG5=6'b010001 RESP_REG6=6'b010010 RESP_REG7=6'b010011 RESP_REG8=6'b010100 RESP_REG9=6'b010101 RESP_WRCOMM_CTRL1=6'b010110 RESP_WAIT_REG11=6'b010111 RESP_WRCOMM_CTRL2=6'b011000 RESP_WAIT_REG12=6'b011001 RESP_RDCOMM_STATUS3=6'b011011 RESP_WRCOMM_INT3=6'b100100 RESP_WAIT_REG13=6'b100101 RESP_FIIC_INT=6'b100110 RESP_WAIT_REG14=6'b100111 RESP_WAIT_ASYNCRD1=6'b101000 RESP_RDCOMM_ASYNCFRM1=6'b101001 RESP_ASYNC_OUT1=6'b101100 RESP_WAIT_ASYNCRD3=6'b101110 RESP_RDCOMM_ASYNCFRM3=6'b101111 RESP_ASYNC_OUT3=6'b110000 ASYNCEVENT_POLL_IDLE=4'b0000 ASYNCEVENT_POLL_WAIT=4'b0001 ASYNCEVENT_POLL_CINT=4'b0010 ASYNCEVENT_REG1=4'b0011 ASYNCEVENT_RDCOMM_STATUS=4'b0100 ASYNCEVENT_WAIT_RD1=4'b0101 ASYNCEVENT_RDCOMM_FRM1=4'b0110 ASYNCEVENT_RDCOMM_OUT1=4'b0111 ASYNCEVENT_WAIT=4'b1000 ASYNCEVENT_PHASE=4'b1001 ASYNCEVENT_WAIT_REG11=4'b1010 ASYNCEVENT_WRCOMM_CTRL1=4'b1011 ASYNCEVENT_WAIT_REG13=4'b1100 ASYNCEVENT_FIIC_INT=4'b1101 ASYNCEVENT_WAIT_REG14=4'b1110 ASYNCEVENT_WRCOMM_INT3=4'b1111 COMM_CTRL_REG=32'b01000000000000010110000000000000 COMM_STATUS_REG=32'b01000000000000010110000000000100 COMM_INTEN_REG=32'b01000000000000010110000000001000 COMM_DATA8_REG=32'b01000000000000010110000000010000 COMM_DATA32_REG=32'b01000000000000010110000000010100 COMM_FRM8_REG=32'b01000000000000010110000000011000 COMM_FRM32_REG=32'b01000000000000010110000000011100 Generated name = CoreSysServices_CmdDec_Z2 @N:CG179 : CoreSysServices_CmdDec.v(1912) | Removing redundant assignment. @W:CG133 : CoreSysServices_CmdDec.v(418) | Object cfwr_req_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(436) | Object cfsrc_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(437) | Object cfdst_addr_int is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(447) | Object memwr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(470) | Object req_srcreg_addr is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(472) | Object req_srcreg_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_CmdDec.v(512) | Object cuhprior_flushdone_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_CmdDec.v(555) | Removing wire cfwr_req_int, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(557) | Removing wire cfwr_req_c, as there is no assignment to it. @W:CG360 : CoreSysServices_CmdDec.v(563) | Removing wire cfdata_w_o, as there is no assignment to it. @W:CL168 : CoreSysServices_CmdDec.v(2927) | Removing instance FLASH_FREEZE_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL169 : CoreSysServices_CmdDec.v(2980) | Pruning unused register FF_exit. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2962) | Pruning unused register FF_exit_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2949) | Pruning unused register FF_entry_led. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2939) | Pruning unused register FF_entry. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning unused register cunvm_bfr_iapverify_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2770) | Pruning unused register latchen_hrdata_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register fiicreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commctrlreg_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(2461) | Pruning unused register commpoll_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1924) | Pruning unused register set_puf_getkcnum_r. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1906) | Pruning unused register wait_count[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1731) | Pruning unused register fctrans_done_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1611) | Pruning unused register pord_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1582) | Pruning unused register req_phase_active_pulse. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register resp_data_done_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1532) | Pruning unused register req_phase_active_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_desc_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1033) | Pruning unused register resp_frm_done. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1015) | Pruning unused register req_desc_done. Make sure that there are no unused intermediate registers. @W:CL271 : CoreSysServices_CmdDec.v(1924) | Pruning unused bits 31 to 8 of fcdataout_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL113 : CoreSysServices_CmdDec.v(2811) | Feedback mux created for signal cutamper_msg[7:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL207 : CoreSysServices_CmdDec.v(2786) | All reachable assignments to cutamper_msg_valid assign 0, register removed by optimization. @W:CL177 : CoreSysServices_CmdDec.v(2461) | Sharing sequential element fcpop_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_fail_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element tamper_detect_valid_r. Add a syn_preserve attribute to the element to prevent sharing. @W:CL207 : CoreSysServices_CmdDec.v(1594) | All reachable assignments to pord assign 0, register removed by optimization. @W:CL250 : CoreSysServices_CmdDec.v(2811) | All reachable assignments to cutamper_msg[7:0] assign 0, register removed by optimization @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_detect_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1944) | Optimizing register bit cutamper_fail_valid to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_addr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(2889) | Optimizing register bit resp_srcreg_data_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 31 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 29 to 17 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 15 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 12 to 5 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 1 to 0 of resp_srcreg_addr_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 31 to 30 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 28 to 8 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : CoreSysServices_CmdDec.v(2889) | Pruning register bits 6 to 5 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 2 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : CoreSysServices_CmdDec.v(2889) | Pruning register bit 0 of resp_srcreg_data_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_detect_valid. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1944) | Pruning unused register cutamper_fail_valid. Make sure that there are no unused intermediate registers. @N:CG364 : CoreSysServices_FSMCtrl.v(30) | Synthesizing module CoreSysServices_FSMCtrl in library CORESYSSERVICES_LIB. @W:CG133 : CoreSysServices_FSMCtrl.v(236) | Object rvalid_out_en_d1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : CoreSysServices_FSMCtrl.v(237) | Object rvalid_out_en_d2 is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : CoreSysServices_FSMCtrl.v(245) | Removing wire fmhaddr_lat, as there is no assignment to it. @W:CL169 : CoreSysServices_FSMCtrl.v(952) | Pruning unused register busreq_prev. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(934) | Pruning unused register pop_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(868) | Pruning unused register fmhtrans_int2[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(732) | Pruning unused register haddr_prev[29:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d2. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(709) | Pruning unused register latch_addr_d3. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(639) | Pruning unused register latch_addr_d1. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_FSMCtrl.v(627) | Pruning unused register state_prev_clk[3:0]. Make sure that there are no unused intermediate registers. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_FSMCtrl.v(853) | Optimizing register bit fmhtrans_int[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_FSMCtrl.v(853) | Pruning register bit 0 of fmhtrans_int[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : CoreSysServices_FSMCtrl.v(293) | Pruning register bits 2 to 1 of fmhburst_d1[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : CoreSysServices_AHBLMasterIF.v(30) | Synthesizing module CoreSysServices_AHBLMasterIF in library CORESYSSERVICES_LIB. @N:CG364 : CoreSysServices.v(30) | Synthesizing module Coresys_Ctrl_blk_CORESYSSERVICES_0_CORESYSSERVICES in library CORESYSSERVICES_LIB. SNSERVICE=32'b00000000000000000000000000000000 DSNPTR=32'b00100000000000000000000000000000 UCSERVICE=32'b00000000000000000000000000000000 USERCODEPTR=32'b00100000000000000000000000000000 DCSERVICE=32'b00000000000000000000000000000000 DEVICECERTPTR=32'b00100000000000000000000000000000 SECDCSERVICE=32'b00000000000000000000000000000000 SECONDECCCERTPTR=32'b00100000000000000000000000000000 UDVSERVICE=32'b00000000000000000000000000000000 DESIGNVERPTR=32'b00100000000000000000000000000000 CRYPTOAES128SERVICE=32'b00000000000000000000000000000001 CRYPTOAES128DATAPTR=32'b00100000000000000001000000000000 CRYPTOAES256SERVICE=32'b00000000000000000000000000000000 CRYPTOAES256DATAPTR=32'b00100000000000000000000000000000 CRYPTOSRCADPTR=32'b00100000000000000010000000000000 CRYPTODSTADPTR=32'b00100000000000000011000000000000 CRYPTOSHA256SERVICE=32'b00000000000000000000000000000000 CRYPTOSHA256DATAPTR=32'b00100000000000000000000000000000 CRYPTORSLTPTR=32'b00100000000000000000000000000000 CRYPTODATAINPPTR=32'b00100000000000000000000000000000 CRYPTOHMACSERVICE=32'b00000000000000000000000000000000 CRYPTOHMACDATAPTR=32'b00100000000000000000000000000000 FFSERVICE=32'b00000000000000000000000000000000 KEYTREESERVICE=32'b00000000000000000000000000000000 KEYTREEDATAPTR=32'b00100000000000000000000000000000 CHRESPSERVICE=32'b00000000000000000000000000000000 CHRESPPTR=32'b00100000000000000000000000000000 CHRESPKEYADDR=32'b00100000000000000000000000000000 NRBGSERVICE=32'b00000000000000000000000000000000 NRBGINSTPTR=32'b00100000000000000000000000000000 NRBGPERSTRINGPTR=32'b00100000000000000000000000000000 NRBGGENPTR=32'b00100000000000000000000000000000 NRBGREQDATAPTR=32'b00100000000000000000000000000000 NRBGRESEEDPTR=32'b00100000000000000000000000000000 NRBGADDINPPTR=32'b00100000000000000000000000000000 ZERSERVICE=32'b00000000000000000000000000000000 PROGIAPSERVICE=32'b00000000000000000000000000000000 PROGNVMDISERVICE=32'b00000000000000000000000000000000 PORDSERVICE=32'b00000000000000000000000000000000 ECCPOINTMULTSERVICE=32'b00000000000000000000000000000000 ECCPMULTDESC=32'b00100000000000000000000000000000 ECCPMULTPPTR=32'b00100000000000000000000000000000 ECCPMULTDPTR=32'b00100000000000000000000000000000 ECCPMULTQPTR=32'b00100000000000000000000000000000 ECCPOINTADDSERVICE=32'b00000000000000000000000000000000 ECCPADDDESC=32'b00100000000000000000000000000000 ECCPADDPPTR=32'b00100000000000000000000000000000 ECCPADDQPTR=32'b00100000000000000000000000000000 ECCPADDRPTR=32'b00100000000000000000000000000000 TAMPERDETECTSERVICE=32'b00000000000000000000000000000000 TAMPERCONTROLSERVICE=32'b00000000000000000000000000000000 PUFSERVICE=32'b00000000000000000000000000000000 PUFUSERACPTR=32'b00100000000000000000000000000000 PUFUSERKCPTR=32'b00100000000000000000000000000000 PUFUSERKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYPTR=32'b00100000000000000000000000000000 PUFPUBLICKEYADDR=32'b00100000000000000000000000000000 PUFSEEDPTR=32'b00100000000000000000000000000000 PUFSEEDADDR=32'b00100000000000000000000000000000 AHB_AWIDTH=32'b00000000000000000000000000100000 AHB_DWIDTH=32'b00000000000000000000000000100000 Generated name = Coresys_Ctrl_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z3 @W:CG360 : CoreSysServices.v(259) | Removing wire cfburst_len_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(265) | Removing wire ustatus_resp_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(266) | Removing wire ubusy_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(267) | Removing wire udata_en_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(268) | Removing wire udata_valid_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(269) | Removing wire udata_r_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(275) | Removing wire uclatchpord_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(281) | Removing wire uccrypto_opmode_o, as there is no assignment to it. @W:CG360 : CoreSysServices.v(304) | Removing wire cudata_wen_o, as there is no assignment to it. @N:CG364 : message_blk.v(5) | Synthesizing module message_blk in library work. @N:CL189 : message_blk.v(28) | Register bit AESDATA[127] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[126] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[123] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[119] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[111] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[110] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[107] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[103] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[99] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[95] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[94] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[91] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[87] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[86] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[83] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[79] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[78] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[75] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[71] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[70] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[67] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[65] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[64] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[63] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[62] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[59] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[55] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[54] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[50] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[47] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[46] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[43] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[39] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[35] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[31] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[30] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[27] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[23] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[22] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[19] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[17] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[15] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[14] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[11] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[7] is always 0. @N:CL189 : message_blk.v(28) | Register bit AESDATA[6] is always 0. @W:CL279 : message_blk.v(28) | Pruning register bits 127 to 117 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 115 to 114 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 112 to 107 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 105 to 82 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 80 to 43 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 41 to 37 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 35 to 34 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 32 to 25 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 23 to 19 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : message_blk.v(28) | Pruning register bit 17 of AESDATA[127:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 15 to 10 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : message_blk.v(28) | Pruning register bits 7 to 5 of AESDATA[127:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : my_sysservice_state.v(5) | Synthesizing module my_sysservice_state in library work. @A:CL282 : my_sysservice_state.v(76) | Feedback mux created for signal SERV_CRYPTO_MODE[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : my_sysservice_state.v(76) | Feedback mux created for signal AES_ENCRYPT_DATA[127:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CMDBYTE_REQ[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[0] is always 1. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[1] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[2] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[3] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[4] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[5] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[6] is always 0. @N:CL189 : my_sysservice_state.v(76) | Register bit SERV_CRYPTO_MODE[7] is always 0. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[7] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[12] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[13] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[14] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : my_sysservice_state.v(76) | Optimizing register bit SERV_CRYPTO_NBLOCKS[15] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : my_sysservice_state.v(76) | Pruning register bits 7 to 2 of SERV_CMDBYTE_REQ[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : my_sysservice_state.v(76) | Pruning register bits 15 to 1 of SERV_CRYPTO_NBLOCKS[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : Coresys_Ctrl_blk.v(9) | Synthesizing module Coresys_Ctrl_blk in library work. @N:CG364 : igloo2.v(376) | Synthesizing module VCC in library work. @N:CG364 : igloo2.v(372) | Synthesizing module GND in library work. @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : igloo2.v(727) | Synthesizing module CCC in library work. @N:CG364 : my_hpms_CCC_0_FCCC.v(5) | Synthesizing module my_hpms_CCC_0_FCCC in library work. @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z4 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z5 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z6 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b011000 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z7 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z8 @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : my_hpms_FABOSC_0_OSC.v(5) | Synthesizing module my_hpms_FABOSC_0_OSC in library work. @N:CG364 : my_hpms_HPMS_syn.v(5) | Synthesizing module MSS_075 in library work. @N:CG364 : my_hpms_HPMS.v(9) | Synthesizing module my_hpms_HPMS in library work. @N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : my_hpms.v(9) | Synthesizing module my_hpms in library work. @N:CG364 : my_hpms_top.v(9) | Synthesizing module my_hpms_top in library work. @N:CG364 : Hex_to_ascii.v(20) | Synthesizing module Nibble2Ascii in library work. @N:CG364 : Hex_to_ascii.v(2) | Synthesizing module Binary2Ascii in library work. @N:CG364 : APB_register_blk.v(2) | Synthesizing module APB_register_blk in library work. DATA_WIDTH=32'b00000000000000000000000000010000 ADDR_WIDTH=32'b00000000000000000000000000100000 Generated name = APB_register_blk_16s_32s @W:CG360 : APB_register_blk.v(33) | Removing wire reg16, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg17, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg18, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg19, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg20, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg21, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg22, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg23, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg24, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg25, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg26, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg27, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg28, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg29, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg30, as there is no assignment to it. @W:CG360 : APB_register_blk.v(33) | Removing wire reg31, as there is no assignment to it. @A:CL282 : APB_register_blk.v(55) | Feedback mux created for signal PRDATA[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N:CG364 : coreabc.v(46) | Synthesizing module UART_top_COREABC_0_COREABC in library work. FAMILY=32'b00000000000000000000000000011000 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000010000 ICWIDTH=32'b00000000000000000000000000001011 ZRWIDTH=32'b00000000000000000000000000000000 IFWIDTH=32'b00000000000000000000000000000100 IIWIDTH=32'b00000000000000000000000000000100 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000001000 EN_RAM=32'b00000000000000000000000000000001 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000000 EN_INDIRECT=32'b00000000000000000000000000000000 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000010010 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000000100000000000 APB_SWIDTH=32'b00000000000000000000000000000100 RAMWIDTH=32'b00000000000000000000000000111010 SYNC_RESET=32'b00000000000000000000000000000000 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = UART_top_COREABC_0_COREABC_Z9 @N:CG364 : ramblocks.v(25) | Synthesizing module UART_top_COREABC_0_RAMBLOCKS in library work. DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011000 Generated name = UART_top_COREABC_0_RAMBLOCKS_32s_24s @N:CG364 : ram256x16_rtl.v(20) | Synthesizing module UART_top_COREABC_0_RAM256X16 in library work. @N:CL134 : ram256x16_rtl.v(32) | Found RAM RAM, depth=256, width=16 @W:CG360 : ramblocks.v(38) | Removing wire RDW, as there is no assignment to it. @W:CG360 : ramblocks.v(44) | Removing wire RDYY, as there is no assignment to it. @N:CG364 : instructions.v(26) | Synthesizing module UART_top_COREABC_0_INSTRUCTIONS in library work. AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000100 ICWIDTH=32'b00000000000000000000000000001011 IIWIDTH=32'b00000000000000000000000000000100 IFWIDTH=32'b00000000000000000000000000000100 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000100 IW=32'b00000000000000000000000000001011 FW=32'b00000000000000000000000000001000 iJUMP=32'b00000000000000000010001000000100 iCALL=32'b00000000000000000010001100000100 iRETURN=32'b00000000000000000010010000000100 iRETISR=32'b00000000000000000010010100000100 iWAIT=32'b00000000000000000010011000000100 iHALT=32'b00000000000000000010011000000100 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Label_WelcomeMessage=32'b00000000000000000000000000000001 Label_Pattern1=32'b00000000000000000000000001101101 Generated name = UART_top_COREABC_0_INSTRUCTIONS_Z10 @W:CG133 : coreabc.v(686) | Object MULT is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(687) | Object A is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(688) | Object B is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(1348) | Object b is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : coreabc.v(227) | Removing wire DEBUG1, as there is no assignment to it. @W:CG360 : coreabc.v(228) | Removing wire DEBUG2, as there is no assignment to it. @W:CG360 : coreabc.v(229) | Removing wire DEBUGBLK_RESETN, as there is no assignment to it. @W:CG133 : coreabc.v(255) | Object iii is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(256) | Object RAMDOUTXX is declared but not assigned. Either assign a value or remove the declaration. @W:CG134 : coreabc.v(260) | No assignment to bit 11 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(260) | No assignment to bit 15 of ins_addr @W:CL169 : coreabc.v(1031) | Pruning unused register ZREGISTER[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreabc.v(1031) | Pruning unused register GETINST. Make sure that there are no unused intermediate registers. @W:CL169 : coreabc.v(501) | Pruning unused register UROM.upper_addr[7:0]. Make sure that there are no unused intermediate registers. @W:CL207 : coreabc.v(1031) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1031) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(808) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @N:CL189 : coreabc.v(484) | Register bit UROM.INSTR_SLOT[4] is always 0. @W:CL260 : coreabc.v(484) | Pruning register bit 4 of UROM.INSTR_SLOT[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000010001 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010100 UPR_NIBBLE_POSN=4'b1000 FAMILY=32'b00000000000000000000000000011000 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000010 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b1000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z11 @N:CG364 : coreapb3_iaddr_reg.v(21) | Synthesizing module coreapb3_iaddr_reg in library COREAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 APB_DWIDTH=6'b100000 MADDR_BITS=6'b010100 Generated name = coreapb3_iaddr_reg_0s_32_20 @N:CG364 : Clock_gen.v(38) | Synthesizing module UART_top_CoreUARTapb_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_Clock_gen_0s_0s @N:CG364 : Tx_async.v(31) | Synthesizing module UART_top_CoreUARTapb_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000001 tx_idle=32'b00000000000000000000000000000000 tx_load=32'b00000000000000000000000000000001 start_bit=32'b00000000000000000000000000000010 tx_data_bits=32'b00000000000000000000000000000011 parity_bit=32'b00000000000000000000000000000100 tx_stop_bit=32'b00000000000000000000000000000101 delay_state=32'b00000000000000000000000000000110 Generated name = UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s @N:CG179 : Tx_async.v(356) | Removing redundant assignment. @N:CG364 : Rx_async.v(30) | Synthesizing module UART_top_CoreUARTapb_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000001 receive_states_rx_idle=32'b00000000000000000000000000000000 receive_states_rx_data_bits=32'b00000000000000000000000000000001 receive_states_rx_stop_bit=32'b00000000000000000000000000000010 receive_states_rx_wait_state=32'b00000000000000000000000000000011 Generated name = UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s @N:CG179 : Rx_async.v(254) | Removing redundant assignment. @N:CG179 : Rx_async.v(280) | Removing redundant assignment. @W:CL177 : Rx_async.v(501) | Sharing sequential element clear_framing_error_en. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : Rx_async.v(501) | Optimizing register bit receive_full_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : Rx_async.v(501) | Pruning unused register receive_full_int. Make sure that there are no unused intermediate registers. @N:CG364 : CoreUART.v(31) | Synthesizing module UART_top_CoreUARTapb_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000001 RX_FIFO=32'b00000000000000000000000000000001 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s @N:CG179 : CoreUART.v(390) | Removing redundant assignment. @N:CG364 : fifo_256x8.v(233) | Synthesizing module UART_top_CoreUARTapb_0_ram16x8 in library work. @N:CL134 : fifo_256x8.v(269) | Found RAM memory, depth=16, width=8 @N:CG364 : fifo_256x8.v(71) | Synthesizing module UART_top_CoreUARTapb_0_fifo_ctrl_256 in library work. SYNC_RESET=32'b00000000000000000000000000000000 FIFO_DEPTH=32'b00000000000000000000000000010000 FIFO_BITS=32'b00000000000000000000000000000100 FIFO_WIDTH=32'b00000000000000000000000000001000 Generated name = UART_top_CoreUARTapb_0_fifo_ctrl_256_0s_16s_4s_8s @N:CG179 : fifo_256x8.v(223) | Removing redundant assignment. @A:CL282 : fifo_256x8.v(208) | Feedback mux created for signal data_out[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N:CG364 : fifo_256x8.v(31) | Synthesizing module UART_top_CoreUARTapb_0_fifo_256x8 in library work. SYNC_RESET=32'b00000000000000000000000000000000 LEVEL=8'b01000000 Generated name = UART_top_CoreUARTapb_0_fifo_256x8_0s_64s @W:CG133 : CoreUART.v(136) | Object data_ready is declared but not assigned. Either assign a value or remove the declaration. @W:CL169 : CoreUART.v(341) | Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers. @N:CG364 : CoreUARTapb.v(59) | Synthesizing module UART_top_CoreUARTapb_0_CoreUARTapb in library work. FAMILY=32'b00000000000000000000000000011000 TX_FIFO=32'b00000000000000000000000000000001 RX_FIFO=32'b00000000000000000000000000000001 BAUD_VALUE=32'b00000000000000000000000001101011 FIXEDMODE=32'b00000000000000000000000000000001 PRG_BIT8=32'b00000000000000000000000000000001 PRG_PARITY=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = UART_top_CoreUARTapb_0_CoreUARTapb_Z12 @N:CG179 : CoreUARTapb.v(254) | Removing redundant assignment. @N:CG179 : CoreUARTapb.v(275) | Removing redundant assignment. @W:CG133 : CoreUARTapb.v(158) | Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : UART_top.v(9) | Synthesizing module UART_top in library work. @N:CG364 : Top.v(9) | Synthesizing module Top in library work. @W:CL246 : CoreUARTapb.v(104) | Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : CoreUARTapb.v(158) | *Unassigned bits of controlReg3[2:0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : fifo_256x8.v(33) | Input RCLOCK is unused. @N:CL201 : CoreUART.v(293) | Trying to extract state machine for register rx_state. Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL190 : Rx_async.v(286) | Optimizing register bit overflow_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : Rx_async.v(286) | Pruning unused register overflow_int. Make sure that there are no unused intermediate registers. @W:CL190 : Rx_async.v(206) | Optimizing register bit overflow to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : Rx_async.v(206) | Pruning unused register overflow. Make sure that there are no unused intermediate registers. @N:CL201 : Rx_async.v(286) | Trying to extract state machine for register rx_state. Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : Rx_async.v(68) | Input read_rx_byte is unused. @N:CL201 : Tx_async.v(119) | Trying to extract state machine for register xmit_state. Extracted state machine for register xmit_state State machine has 7 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 00000000000000000000000000000110 @N:CL159 : Tx_async.v(42) | Input rst_tx_empty is unused. @N:CL159 : Tx_async.v(43) | Input tx_hold_reg is unused. @N:CL159 : Clock_gen.v(51) | Input BAUD_VAL_FRACTION is unused. @W:CL246 : coreapb3_iaddr_reg.v(39) | Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. @N:CL159 : ram256x16_rtl.v(23) | Input RESET is unused. @N:CL201 : coreabc.v(1031) | Trying to extract state machine for register ICYCLE. Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : coreabc.v(134) | Input PSLVERR_M is unused. @N:CL159 : coreabc.v(138) | Input INTREQ is unused. @N:CL159 : coreabc.v(141) | Input INITDATVAL is unused. @N:CL159 : coreabc.v(142) | Input INITDONE is unused. @N:CL159 : coreabc.v(143) | Input INITADDR is unused. @N:CL159 : coreabc.v(144) | Input INITDATA is unused. @N:CL159 : coreabc.v(148) | Input PSEL_S is unused. @N:CL159 : coreabc.v(149) | Input PENABLE_S is unused. @N:CL159 : coreabc.v(150) | Input PWRITE_S is unused. @N:CL159 : coreabc.v(151) | Input PADDR_S is unused. @N:CL159 : coreabc.v(152) | Input PWDATA_S is unused. @N:CL201 : APB_register_blk.v(55) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : APB_register_blk.v(21) | Input port bits 31 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : APB_register_blk.v(22) | Input port bits 15 to 2 of PWDATA[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL247 : my_hpms_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : my_hpms_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : my_hpms_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : my_hpms_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : my_hpms_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : my_hpms_FABOSC_0_OSC.v(14) | Input XTL is unused. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused. @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused. @N:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused. @N:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused. @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL201 : my_sysservice_state.v(76) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 14 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 @W:CL260 : my_sysservice_state.v(76) | Pruning register bit 1 of SERV_CMDBYTE_REQ[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL159 : CoreSysServices_AHBLMasterIF.v(72) | Input HCLK is unused. @N:CL159 : CoreSysServices_AHBLMasterIF.v(73) | Input HRESETN is unused. @W:CL190 : CoreSysServices_FSMCtrl.v(293) | Optimizing register bit fmhburst_d1[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : CoreSysServices_FSMCtrl.v(293) | Pruning unused register fmhburst_d1[0]. Make sure that there are no unused intermediate registers. @N:CL201 : CoreSysServices_FSMCtrl.v(326) | Trying to extract state machine for register curr_state. Extracted state machine for register curr_state State machine has 7 reachable states with original encodings of: 0000 0001 0010 0101 1000 1001 1011 @N:CL159 : CoreSysServices_FSMCtrl.v(162) | Input cfwr_req_d is unused. @N:CL159 : CoreSysServices_FSMCtrl.v(163) | Input cfrd_req_d is unused. @W:CL190 : CoreSysServices_CmdDec.v(997) | Optimizing register bit burstlen_memwr_data_r[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[16] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[17] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[18] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[19] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[20] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[21] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[22] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[23] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[24] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[25] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[26] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[27] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[28] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[29] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[30] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_rd_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : CoreSysServices_CmdDec.v(1096) | Pruning register bits 31 to 16 of cfburst_len_rd_d1[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : CoreSysServices_CmdDec.v(997) | Pruning register bit 31 of burstlen_memwr_data_r[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL177 : CoreSysServices_CmdDec.v(1924) | Sharing sequential element fcdataout_d1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : CoreSysServices_CmdDec.v(1096) | Optimizing register bit cfburst_len_wr_d1[31] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : CoreSysServices_CmdDec.v(1096) | Pruning register bit 31 of cfburst_len_wr_d1[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : CoreSysServices_CmdDec.v(3426) | Trying to extract state machine for register asynchevent_curr_state. Extracted state machine for register asynchevent_curr_state State machine has 2 reachable states with original encodings of: 0000 1001 @N:CL201 : CoreSysServices_CmdDec.v(3004) | Trying to extract state machine for register resp_curr_state. Extracted state machine for register resp_curr_state State machine has 31 reachable states with original encodings of: 000000 000001 000011 000101 000110 000111 001000 001001 001100 001101 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011011 100100 100101 100110 100111 101000 101001 101100 101110 101111 110000 @N:CL201 : CoreSysServices_CmdDec.v(1970) | Trying to extract state machine for register req_curr_state. Extracted state machine for register req_curr_state State machine has 37 reachable states with original encodings of: 000000 000001 000010 000011 000100 000101 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 100001 100010 100101 100110 101000 101001 101010 101011 101100 101101 101110 110000 110001 110010 110011 110100 @N:CL201 : CoreSysServices_CmdDec.v(1640) | Trying to extract state machine for register main_curr_state. Extracted state machine for register main_curr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL190 : CoreSysServices_CmdDec.v(1895) | Optimizing register bit cfrd_asyncevent_o to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : CoreSysServices_CmdDec.v(2889) | Pruning unused register resp_srcreg_addr_d1[30]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreSysServices_CmdDec.v(1895) | Pruning unused register cfrd_asyncevent_o. Make sure that there are no unused intermediate registers. @W:CL157 : CoreSysServices_CmdDec.v(372) | *Output cutrans_done_o has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : CoreSysServices_CmdDec.v(345) | Input ucdata_wvalid_i is unused. @N:CL159 : CoreSysServices_CmdDec.v(356) | Input fcpush_i is unused. @N:CL159 : CoreSysServices_CmdDec.v(360) | Input clr_req is unused. @N:CL135 : CoreSysServices_UserIF.v(772) | Found sequential shift zer_new_serv_d1 with address depth of 3 words and data bit width of 1. @N:CL159 : CoreSysServices_UserIF.v(257) | Input cutrans_done_i is unused. @N:CL159 : CoreSysServices_UserIF.v(262) | Input cutamper_detect_valid is unused. @N:CL159 : CoreSysServices_UserIF.v(263) | Input cutamper_fail_valid is unused. At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 127MB peak: 144MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime Process completed successfully. # Fri Mar 24 18:14:43 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 86MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 24 18:14:44 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime Process completed successfully. # Fri Mar 24 18:14:44 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File C:\Microsemi\Libero_SoC_v11.7\Synplify\bin64\syn_nfilter.exe changed - recompiling File D:\cases\11_7APPNOTE UPDATE\AC410\m2s_m2gl_ac410_cbc_mac_liberov11p7_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\synthesis\synwork\Top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 24 18:14:46 2017 ###########################################################] Pre-mapping Report # Fri Mar 24 18:14:46 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. Linked File: Top_scck.rpt Printing clock summary report in "C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\synthesis\Top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 148MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 148MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 148MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 148MB) @W:BN132 : my_sysservice_state.v(76) | Removing sequential instance Coresys_Ctrl_blk_0.my_sysservice_state_0.SERV_CRYPTO_NBLOCKS_1[0] because it is equivalent to instance Coresys_Ctrl_blk_0.my_sysservice_state_0.SERV_ENABLE_REQ. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : my_sysservice_state.v(76) | Removing sequential instance Coresys_Ctrl_blk_0.my_sysservice_state_0.SERV_CMDBYTE_REQ_1[0] because it is equivalent to instance Coresys_Ctrl_blk_0.my_sysservice_state_0.SERV_ENABLE_REQ. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z5_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z5_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z5_2(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(305) | Removing sequential instance clr_req (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : rx_async.v(286) | Removing sequential instance stop_strobe (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreabc.v(1031) | Removing sequential instance IO_OUT[0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_userif.v(416) | Removing sequential instance ucmd_error (in view: CORESYSSERVICES_LIB.CoreSysServices_UserIF_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : my_sysservice_state.v(76) | Removing sequential instance SERV_DATA_WVALID (in view: work.my_sysservice_state(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(838) | Removing sequential instance fmhsel_o (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z8(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_0(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist Top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 165MB peak: 166MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------- my_hpms_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 1971 my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 15 ================================================================================================================================= @W:MT530 : coresysservices_userif.v(807) | Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock which controls 1971 sequential elements including Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucvalid_cmd_o. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(912) | Found inferred clock my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\synthesis\Top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 161MB peak: 166MB) Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 Encoding state machine main_curr_state[2:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. Encoding state machine fsm_1[13:0] (in view: work.my_sysservice_state(verilog)) original code -> new code 0000 -> 00000000000001 0001 -> 00000000000010 0010 -> 00000000000100 0011 -> 00000000001000 0100 -> 00000000010000 0101 -> 00000000100000 0110 -> 00000001000000 0111 -> 00000010000000 1000 -> 00000100000000 1001 -> 00001000000000 1010 -> 00010000000000 1011 -> 00100000000000 1100 -> 01000000000000 1101 -> 10000000000000 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine fsm[3:0] (in view: work.APB_register_blk_16s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : apb_register_blk.v(55) | There are no possible illegal states for state machine fsm[3:0] (in view: work.APB_register_blk_16s_32s(verilog)); safe FSM implementation is not required. Encoding state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1031) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)); safe FSM implementation is not required. Encoding state machine xmit_state[6:0] (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 0000001 00000000000000000000000000000001 -> 0000010 00000000000000000000000000000010 -> 0000100 00000000000000000000000000000011 -> 0001000 00000000000000000000000000000100 -> 0010000 00000000000000000000000000000101 -> 0100000 00000000000000000000000000000110 -> 1000000 Encoding state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. Encoding state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreuart.v(293) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)); safe FSM implementation is not required. @N:BN362 : rx_async.v(377) | Removing sequential instance rx_shift[8] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. None None Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 183MB peak: 185MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 71MB peak: 185MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Fri Mar 24 18:14:49 2017 ###########################################################] Map & Optimize Report # Fri Mar 24 18:14:49 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 149MB) @N:MO111 : coresysservices_cmddec.v(372) | Tristate driver cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver cutrans_done_o_t (in view: CORESYSSERVICES_LIB.Coresys_Ctrl_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z3(verilog)) on net cutrans_done_o (in view: CORESYSSERVICES_LIB.Coresys_Ctrl_blk_CORESYSSERVICES_0_CORESYSSERVICES_Z3(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : my_hpms_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_hpms_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO160 : rx_async.v(421) | Register bit rx_parity_calc (in view view:work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance my_hpms_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance my_hpms_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(929) | Removing sequential instance my_hpms_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(856) | Removing sequential instance my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc_q1 because it is equivalent to instance my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance my_hpms_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @N:BN362 : coresysservices_cmddec.v(2889) | Removing sequential instance resp_srcreg_data_d1[7] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 152MB) @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[7] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[6] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[5] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[4] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[3] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(696) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.ucmdbyte_req_d1[2] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[7] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[6] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[5] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[4] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[3] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[2] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_mode_o[1] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[15] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[14] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[13] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[12] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[11] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[10] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[9] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[8] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[7] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[6] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[5] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[4] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[3] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[2] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_nblocks_o[1] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[255] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[254] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[253] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[252] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[251] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[250] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[249] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[248] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[247] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[246] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[245] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[244] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[243] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[242] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[241] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[240] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[239] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[238] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[237] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[236] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[235] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[234] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[233] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[232] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[231] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[230] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[229] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[228] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[227] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[226] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[225] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[224] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[223] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[222] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[221] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[220] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[219] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[218] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[217] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[216] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[215] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[214] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[213] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[212] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[211] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[210] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[209] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[208] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[207] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[206] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[205] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[204] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[203] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[202] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[201] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[200] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[199] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[198] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[197] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[196] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[195] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[194] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[193] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[192] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[191] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[190] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[189] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[188] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[187] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[186] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[185] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[184] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[183] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[182] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[181] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[180] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[179] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[178] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[177] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[176] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[175] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[174] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[173] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[172] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[171] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[170] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[169] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[168] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[167] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[166] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[165] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[164] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[163] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[162] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[161] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[160] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[159] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[158] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[157] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[156] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[155] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[154] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[153] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[152] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[151] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[150] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[149] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[148] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[147] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[146] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[145] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[144] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[143] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[142] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[141] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[140] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[139] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[138] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[137] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[136] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[135] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[134] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[133] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[132] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[131] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[130] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[129] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[128] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[127] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[126] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[123] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[122] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[121] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[120] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[119] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[118] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[115] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[114] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[113] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[111] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[110] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[107] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[106] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[104] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[103] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[102] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[99] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[98] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[95] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[94] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[91] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[89] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[88] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[87] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[86] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[83] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[81] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[79] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[78] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[75] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[72] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[71] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[70] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[67] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[63] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[62] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[58] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[57] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[56] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[55] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[54] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[50] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[49] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[47] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[44] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[43] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[42] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[41] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[39] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[36] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[35] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[34] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[32] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[31] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[28] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[27] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[26] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[23] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[20] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[19] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[17] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[16] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[15] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[12] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[11] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[9] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[7] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[4] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[3] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(980) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uccrypto_key_o[0] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[7] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[6] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[5] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[4] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[3] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_userif.v(653) | Register bit Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_UserIF.uclatchcmd_o[2] (in view view:work.Top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine resp_curr_state[30:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000001 000001 -> 0000000000000000000000000000010 000011 -> 0000000000000000000000000000100 000101 -> 0000000000000000000000000001000 000110 -> 0000000000000000000000000010000 000111 -> 0000000000000000000000000100000 001000 -> 0000000000000000000000001000000 001001 -> 0000000000000000000000010000000 001100 -> 0000000000000000000000100000000 001101 -> 0000000000000000000001000000000 010000 -> 0000000000000000000010000000000 010001 -> 0000000000000000000100000000000 010010 -> 0000000000000000001000000000000 010011 -> 0000000000000000010000000000000 010100 -> 0000000000000000100000000000000 010101 -> 0000000000000001000000000000000 010110 -> 0000000000000010000000000000000 010111 -> 0000000000000100000000000000000 011000 -> 0000000000001000000000000000000 011001 -> 0000000000010000000000000000000 011011 -> 0000000000100000000000000000000 100100 -> 0000000001000000000000000000000 100101 -> 0000000010000000000000000000000 100110 -> 0000000100000000000000000000000 100111 -> 0000001000000000000000000000000 101000 -> 0000010000000000000000000000000 101001 -> 0000100000000000000000000000000 101100 -> 0001000000000000000000000000000 101110 -> 0010000000000000000000000000000 101111 -> 0100000000000000000000000000000 110000 -> 1000000000000000000000000000000 Encoding state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 0000 -> 0 1001 -> 1 @N:MO225 : coresysservices_cmddec.v(3426) | There are no possible illegal states for state machine asynchevent_curr_state[1:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)); safe FSM implementation is not required. Encoding state machine req_curr_state[36:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 000000 -> 0000000000000000000000000000000000001 000001 -> 0000000000000000000000000000000000010 000010 -> 0000000000000000000000000000000000100 000011 -> 0000000000000000000000000000000001000 000100 -> 0000000000000000000000000000000010000 000101 -> 0000000000000000000000000000000100000 000111 -> 0000000000000000000000000000001000000 001000 -> 0000000000000000000000000000010000000 001001 -> 0000000000000000000000000000100000000 001010 -> 0000000000000000000000000001000000000 001011 -> 0000000000000000000000000010000000000 001100 -> 0000000000000000000000000100000000000 001101 -> 0000000000000000000000001000000000000 001110 -> 0000000000000000000000010000000000000 001111 -> 0000000000000000000000100000000000000 010000 -> 0000000000000000000001000000000000000 010001 -> 0000000000000000000010000000000000000 010010 -> 0000000000000000000100000000000000000 010011 -> 0000000000000000001000000000000000000 010100 -> 0000000000000000010000000000000000000 010101 -> 0000000000000000100000000000000000000 100001 -> 0000000000000001000000000000000000000 100010 -> 0000000000000010000000000000000000000 100101 -> 0000000000000100000000000000000000000 100110 -> 0000000000001000000000000000000000000 101000 -> 0000000000010000000000000000000000000 101001 -> 0000000000100000000000000000000000000 101010 -> 0000000001000000000000000000000000000 101011 -> 0000000010000000000000000000000000000 101100 -> 0000000100000000000000000000000000000 101101 -> 0000001000000000000000000000000000000 101110 -> 0000010000000000000000000000000000000 110000 -> 0000100000000000000000000000000000000 110001 -> 0001000000000000000000000000000000000 110010 -> 0010000000000000000000000000000000000 110011 -> 0100000000000000000000000000000000000 110100 -> 1000000000000000000000000000000000000 Encoding state machine main_curr_state[2:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MO231 : coresysservices_cmddec.v(2481) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog) instance desc_datasel_cntr[31:0] @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[16] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[14] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[12] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[4] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[3] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[2] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1924) | Register bit memwr_data_addr_r[0] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memrd_data_d1[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[30] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[29] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(997) | Register bit burstlen_memwr_data_r[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1303) | Register bit cfsrc_addr_d1[0] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[31] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[28] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[27] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[26] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[25] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[24] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[23] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[22] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[21] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[20] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[19] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[18] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[17] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[15] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[11] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[10] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[9] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[8] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[7] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[6] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[5] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[1] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coresysservices_cmddec.v(1255) | Register bit cfdst_addr_d1[0] (in view view:CORESYSSERVICES_LIB.CoreSysServices_CmdDec_Z2(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine curr_state[6:0] (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0101 -> 0001000 1000 -> 0010000 1001 -> 0100000 1011 -> 1000000 @N:BN362 : coresysservices_fsmctrl.v(612) | Removing sequential instance burstwrflag_last_n (in view: CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:MO231 : coresysservices_fsmctrl.v(760) | Found counter in view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog) instance word_count[31:0] @W:MO160 : coresysservices_fsmctrl.v(679) | Register bit cfrd_asyncevent_d1 (in view view:CORESYSSERVICES_LIB.CoreSysServices_FSMCtrl(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine fsm_1[13:0] (in view: work.my_sysservice_state(verilog)) original code -> new code 0000 -> 00000000000001 0001 -> 00000000000010 0010 -> 00000000000100 0011 -> 00000000001000 0100 -> 00000000010000 0101 -> 00000000100000 0110 -> 00000001000000 0111 -> 00000010000000 1000 -> 00000100000000 1001 -> 00001000000000 1010 -> 00010000000000 1011 -> 00100000000000 1100 -> 01000000000000 1101 -> 10000000000000 @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[31] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[30] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[27] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[23] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[15] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[14] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[11] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : my_sysservice_state.v(76) | Register bit SERV_DATA_W[7] (in view view:work.my_sysservice_state(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view: work.my_hpms(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] (in view view:work.my_hpms(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] (in view view:work.my_hpms(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] (in view view:work.my_hpms(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] (in view view:work.my_hpms(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] (in view view:work.my_hpms(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z6_1(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z8(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine fsm[3:0] (in view: work.APB_register_blk_16s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : apb_register_blk.v(55) | There are no possible illegal states for state machine fsm[3:0] (in view: work.APB_register_blk_16s_32s(verilog)); safe FSM implementation is not required. @W:MO160 : apb_register_blk.v(55) | Register bit PRDATA[15] (in view view:work.APB_register_blk_16s_32s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : apb_register_blk.v(55) | Register bit PRDATA[7] (in view view:work.APB_register_blk_16s_32s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1031) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.UART_top_COREABC_0_COREABC_Z9(verilog)); safe FSM implementation is not required. @W:FX107 : ram256x16_rtl.v(32) | RAM UG3\.UR32\.UR0.RAM[15:0] (in view: work.UART_top_COREABC_0_RAMBLOCKS_32s_24s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @W:FX107 : ram256x16_rtl.v(32) | RAM UG3\.UR_xhdl12.RAM[15:0] (in view: work.UART_top_COREABC_0_RAMBLOCKS_32s_24s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. Encoding state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreuart.v(293) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)); safe FSM implementation is not required. @N:FX403 : fifo_256x8.v(269) | Property "block_ram" or "no_rw_check" found for RAM genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory[7:0] with specified coding style. Inferring block RAM. @W:FX107 : fifo_256x8.v(269) | RAM genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory[7:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : fifo_256x8.v(269) | Property "block_ram" or "no_rw_check" found for RAM genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory[7:0] with specified coding style. Inferring block RAM. @W:FX107 : fifo_256x8.v(269) | RAM genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory[7:0] (in view: work.UART_top_CoreUARTapb_0_COREUART_1s_1s_0s_24s_0s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MO231 : clock_gen.v(283) | Found counter in view:work.UART_top_CoreUARTapb_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0] Encoding state machine xmit_state[6:0] (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 0000001 00000000000000000000000000000001 -> 0000010 00000000000000000000000000000010 -> 0000100 00000000000000000000000000000011 -> 0001000 00000000000000000000000000000100 -> 0010000 00000000000000000000000000000101 -> 0100000 00000000000000000000000000000110 -> 1000000 @W:MO160 : tx_async.v(119) | Register bit xmit_state[4] (in view view:work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : tx_async.v(339) | Removing sequential instance tx_parity (in view: work.UART_top_CoreUARTapb_0_Tx_async_0s_1s_0s_1s_2s_3s_4s_5s_6s(verilog)) because it does not drive other instances. Encoding state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. @W:MO161 : rx_async.v(261) | Register bit last_bit[3] (in view view:work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : rx_async.v(261) | Register bit last_bit[2] (in view view:work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : rx_async.v(261) | Register bit last_bit[1] (in view view:work.UART_top_CoreUARTapb_0_Rx_async_0s_1s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 167MB peak: 187MB) @N:BN362 : rx_async.v(447) | Removing sequential instance CoreUARTapb_0.uUART.make_RX.parity_err (in view: work.UART_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.INIT_DONE_int (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_fsmctrl.v(780) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_fsm_ctrl.fmhaddr_o[0] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[6] (in view: work.Top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 180MB peak: 187MB) @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[5] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[8] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[9] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[10] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[11] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[12] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[13] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[14] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memrd_data_d1[15] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[29] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[30] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[18] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[19] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[20] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[21] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[22] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[23] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[24] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[25] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[26] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[27] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_wr_d1[28] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[1] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] (in view: work.Top(verilog)) because it does not drive other instances. Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 177MB peak: 187MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 167MB peak: 187MB) @N:BN362 : rx_async.v(377) | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.make_RX.rx_shift[8] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(1096) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfburst_len_rd_d1[10] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9] (in view: work.Top(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 168MB peak: 187MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 168MB peak: 187MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 167MB peak: 187MB) @W:FA239 : coresysservices_cmddec.v(1466) | ROM Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[6:0] (in view: work.Top(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : coresysservices_cmddec.v(1466) | ROM Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.memrd_data_addr_cnst[6:0] (in view: work.Top(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : coresysservices_cmddec.v(1466) | Found ROM .delname. (in view: work.Top(verilog)) with 10 words by 7 bits. @N:MO106 : instructions.v(79) | Found ROM .delname. (in view: work.Top(verilog)) with 394 words by 58 bits. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1613) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled (in view: work.Top(verilog)) because it does not drive other instances. @A:BN291 : coreresetp.v(1613) | Boundary register my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled (in view: work.Top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled_q1 (in view: work.Top(verilog)) because it does not drive other instances. @A:BN291 : coreresetp.v(1646) | Boundary register my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled_q1 (in view: work.Top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : coreresetp.v(963) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(929) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.ddr_settled_clk_base (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[5] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[4] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[3] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[2] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[1] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_hpms_top_0.my_hpms_0.CORERESETP_0.sm0_state[0] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : instructions.v(79) | Removing sequential instance UART_top_0.COREABC_0.UROM\.UROM.doins_0_dreg[11] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[0] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[1] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[2] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[3] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[4] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[5] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[6] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[7] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[8] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[9] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[10] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[11] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[12] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[13] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[14] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[15] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[16] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[17] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[18] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[19] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[20] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[21] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[22] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[23] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[24] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[25] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[26] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[27] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[28] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[29] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[30] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coreapb3_iaddr_reg.v(51) | Removing sequential instance UART_top_0.CoreAPB3_0.g_iaddr_reg\.genblk18\.iaddr_reg.IADDR_REG[31] (in view: work.Top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 174MB peak: 187MB) Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 201MB peak: 204MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:09s -5.92ns 3194 / 1366 2 0h:00m:09s -4.81ns 2839 / 1366 3 0h:00m:09s -4.13ns 2839 / 1366 4 0h:00m:09s -3.52ns 2839 / 1366 5 0h:00m:09s -3.52ns 2839 / 1366 6 0h:00m:10s -3.52ns 2839 / 1366 7 0h:00m:11s -3.20ns 2846 / 1366 8 0h:00m:11s -2.82ns 2848 / 1366 9 0h:00m:11s -2.56ns 2834 / 1366 10 0h:00m:11s -2.56ns 2834 / 1366 @N:FX271 : ram256x16_rtl.v(32) | Replicating instance UART_top_0.COREABC_0.URAM\.UR.UG3\.UR_xhdl12.RD_ret_32 (in view: work.Top(verilog)) with 76 loads 3 times to improve timing. @N:FX271 : | Replicating instance UART_top_0.COREABC_0.SMADDR[5] (in view: work.Top(verilog)) with 79 loads 3 times to improve timing. @N:FX271 : | Replicating instance UART_top_0.COREABC_0.SMADDR[6] (in view: work.Top(verilog)) with 73 loads 3 times to improve timing. @N:FX271 : | Replicating instance UART_top_0.COREABC_0.SMADDR[2] (in view: work.Top(verilog)) with 62 loads 3 times to improve timing. Timing driven replication report Added 12 Registers via timing driven replication Added 12 LUTs via timing driven replication 11 0h:00m:12s -2.52ns 2844 / 1378 12 0h:00m:12s -2.43ns 2847 / 1378 @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[9] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[10] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[11] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[12] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[13] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[14] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[15] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[16] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[17] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[0] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[3] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[4] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[5] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[6] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[7] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[8] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : coresysservices_cmddec.v(997) | Removing sequential instance Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.burstlen_memwr_data_r[2] (in view: work.Top(verilog)) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[0] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[1] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[2] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[3] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[4] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[5] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[6] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk2\.tx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[7] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[0] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[1] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[2] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[3] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[4] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[5] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[6] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:BN362 : | Removing sequential instance UART_top_0.CoreUARTapb_0.uUART.genblk3\.rx_fifo.fifo_ctrl_256.ram16x8.memory_memory_0_0_R[7] (in view: work.Top(verilog)) of type view:ACG4.SLE(PRIM) because it does not drive other instances. @N:FP130 : | Promoting Net my_hpms_top_0_HPMS_READY on CLKINT I_1397 @N:FP130 : | Promoting Net UART_top_0.COREABC_0_PRESETN on CLKINT I_1398 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 206MB peak: 208MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 208MB peak: 209MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 1390 clock pin(s) of sequential element(s) 0 instances converted, 1390 sequential instances remain driven by gated/generated clocks ============================================================================================== Gated/Generated Clocks ============================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 my_hpms_top_0.my_hpms_0.CCC_0.CCC_INST CCC 1390 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ==================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 169MB peak: 209MB) Writing Analyst data base C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\synthesis\synwork\Top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 203MB peak: 209MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\AC410_11_8\m2s_m2gl_ac410_cbc_mac_liberov11p8_df\SF2_IGL2_cbc_mac_df\Libero\CBC_MAC_IGL2\synthesis\Top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 205MB peak: 209MB) Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 199MB peak: 209MB) @W:MT246 : my_hpms_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_hpms_top_0.my_hpms_0.CCC_0.GL0_net" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Mar 24 18:15:04 2017 # Top view: Top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.025 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 90.7 MHz 10.000 11.025 -1.025 inferred Inferred_clkgroup_0 my_hpms_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 ============================================================================================================================================================== @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_CCC_0_FCCC|GL0_net_inferred_clock my_hpms_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 -1.025 | No paths - | No paths - | No paths - ============================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: my_hpms_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 3.505 -1.025 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_RESP CoreAHBLite_0_AHBmslave16_HRESP 3.460 -0.633 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q m0s16DataSel 0.076 0.195 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[3] 0.094 0.235 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[5] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[5] 0.094 0.258 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[1] 0.094 0.269 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[8] 0.094 0.317 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[9] 0.094 0.323 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[7] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[7] 0.094 0.351 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[13] my_hpms_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[13] 0.094 0.365 ======================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[3] CoreAHBLite_0_AHBmslave16_HWDATA[3] 8.735 -1.025 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[1] CoreAHBLite_0_AHBmslave16_HWDATA[1] 8.660 -0.993 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[12] CoreAHBLite_0_AHBmslave16_HWDATA[12] 8.728 -0.900 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[4] CoreAHBLite_0_AHBmslave16_HWDATA[4] 8.736 -0.818 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[29] CoreAHBLite_0_AHBmslave16_HWDATA[29] 8.833 -0.817 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[7] CoreAHBLite_0_AHBmslave16_HWDATA[7] 8.703 -0.773 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[0] HWDATA_N_9_mux_i 8.796 -0.724 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[15] CoreAHBLite_0_AHBmslave16_HWDATA[15] 8.672 -0.072 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[2] CoreAHBLite_0_AHBmslave16_HWDATA[2] 9.044 -0.047 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST my_hpms_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_FM0_WDATA[25] CoreAHBLite_0_AHBmslave16_HWDATA[25] 8.737 -0.007 ==================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.265 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.735 - Propagation time: 9.760 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.025 Number of logic level(s): 5 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[3] The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.505 3.505 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.990 - 12 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 C In - 4.495 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 Y Out 0.182 4.677 - mchready_i Net - - 1.018 - 27 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 D In - 5.695 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 Y Out 0.250 5.945 - un2_cudata_wrdy_int_8_i Net - - 0.937 - 37 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 A In - 6.882 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 Y Out 0.076 6.958 - un2_cudata_wrdy_int_9_i_0_a2_0_a2_2_a2_1_a2_0 Net - - 0.783 - 14 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_i_a2_2[3] CFG4 D In - 7.741 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_i_a2_2[3] CFG4 Y Out 0.250 7.991 - N_12798 Net - - 0.548 - 2 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA[3] CFG4 D In - 8.539 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA[3] CFG4 Y Out 0.250 8.789 - CoreAHBLite_0_AHBmslave16_HWDATA[3] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_WDATA[3] In - 9.760 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 11.025 is 5.778(52.4%) logic and 5.247(47.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.340 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.660 - Propagation time: 9.653 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.993 Number of logic level(s): 5 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[1] The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.505 3.505 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.990 - 12 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 C In - 4.495 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 Y Out 0.182 4.677 - mchready_i Net - - 1.018 - 27 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 D In - 5.695 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 Y Out 0.250 5.945 - un2_cudata_wrdy_int_8_i Net - - 0.937 - 37 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 A In - 6.882 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 Y Out 0.076 6.958 - un2_cudata_wrdy_int_9_i_0_a2_0_a2_2_a2_1_a2_0 Net - - 0.783 - 14 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[1] CFG4 D In - 7.741 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[1] CFG4 Y Out 0.250 7.991 - N_12900 Net - - 0.548 - 2 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 B In - 8.539 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 Y Out 0.143 8.682 - CoreAHBLite_0_AHBmslave16_HWDATA[1] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_WDATA[1] In - 9.653 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 10.993 is 5.746(52.3%) logic and 5.247(47.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.340 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.660 - Propagation time: 9.593 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.933 Number of logic level(s): 5 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[1] The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.505 3.505 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.990 - 12 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 C In - 4.495 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 Y Out 0.182 4.677 - mchready_i Net - - 1.018 - 27 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o27_0_a2 CFG4 D In - 5.695 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o27_0_a2 CFG4 Y Out 0.250 5.945 - cfdatain_o27 Net - - 0.670 - 6 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz[7] CFG4 C In - 6.615 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz[7] CFG4 Y Out 0.182 6.797 - N_13226 Net - - 0.802 - 16 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[7] CFG4 C In - 7.599 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[7] CFG4 Y Out 0.182 7.782 - N_12169 Net - - 0.590 - 3 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 D In - 8.372 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 Y Out 0.250 8.622 - CoreAHBLite_0_AHBmslave16_HWDATA[1] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_WDATA[1] In - 9.593 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 10.933 is 5.892(53.9%) logic and 5.041(46.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.340 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.660 - Propagation time: 9.581 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.921 Number of logic level(s): 5 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[1] The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.505 3.505 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.990 - 12 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 C In - 4.495 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 Y Out 0.182 4.677 - mchready_i Net - - 1.018 - 27 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o26_0_a2 CFG4 D In - 5.695 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o26_0_a2 CFG4 Y Out 0.250 5.945 - cfdatain_o26 Net - - 0.590 - 3 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz[7] CFG4 D In - 6.535 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz[7] CFG4 Y Out 0.250 6.785 - N_13226 Net - - 0.802 - 16 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[7] CFG4 C In - 7.588 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2[7] CFG4 Y Out 0.182 7.770 - N_12169 Net - - 0.590 - 3 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 D In - 8.360 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.slavestage_16.HWDATA_0[1] CFG4 Y Out 0.250 8.610 - CoreAHBLite_0_AHBmslave16_HWDATA[1] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_WDATA[1] In - 9.581 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 10.921 is 5.960(54.6%) logic and 4.961(45.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.272 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.728 - Propagation time: 9.628 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.900 Number of logic level(s): 5 Starting point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST / F_FM0_WDATA[12] The start point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by my_hpms_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_READYOUT Out 3.505 3.505 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.990 - 12 my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 C In - 4.495 - my_hpms_top_0.my_hpms_0.CoreAHBLite_0.matrix4x16.masterstage_0.DEFSLAVEDATASEL_8_RNI1FFN1 CFG4 Y Out 0.182 4.677 - mchready_i Net - - 1.018 - 27 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 D In - 5.695 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_8 CFG4 Y Out 0.250 5.945 - un2_cudata_wrdy_int_8_i Net - - 0.937 - 37 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 A In - 6.882 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.un2_cudata_wrdy_int_6_i_a2_1_0_a2_RNIPQPD CFG2 Y Out 0.076 6.958 - un2_cudata_wrdy_int_9_i_0_a2_0_a2_2_a2_1_a2_0 Net - - 0.783 - 14 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz_RNIJOEA2[7] CFG4 D In - 7.741 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_6_s_tz_RNIJOEA2[7] CFG4 Y Out 0.250 7.991 - cfdatain_o_iv_0_0_7_1[12] Net - - 0.483 - 1 Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_0_RNIEQD73[12] CFG4 C In - 8.474 - Coresys_Ctrl_blk_0.CORESYSSERVICES_0.U_CmdDec.cfdatain_o_iv_0_0_a2_0_RNIEQD73[12] CFG4 Y Out 0.182 8.656 - CoreAHBLite_0_AHBmslave16_HWDATA[12] Net - - 0.971 - 1 my_hpms_top_0.my_hpms_0.my_hpms_HPMS_0.MSS_ADLIB_INST MSS_075 F_FM0_WDATA[12] In - 9.628 - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 10.900 is 5.717(52.5%) logic and 5.182(47.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 199MB peak: 209MB) Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 199MB peak: 209MB) --------------------------------------- Resource Usage Report for Top Mapping to part: m2gl090tsfbga484-1 Cell usage: CCC 1 use CLKINT 3 uses MSS_075 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 10 uses CFG2 550 uses CFG3 711 uses CFG4 1232 uses Carry cells: ARI1 168 uses - used for arithmetic functions ARI1 105 uses - used for Wide-Mux implementation Total ARI1 273 uses Sequential Cells: SLE 1361 uses DSP Blocks: 0 of 84 (0%) I/O ports: 15 I/O primitives: 14 INBUF 5 uses OUTBUF 9 uses Global Clock Buffers: 3 of 8 (37%) RAM/ROM usage summary Total Block RAMs (RAM64x18) : 10 of 112 (8%) Total LUTs: 2776 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 360; LUTs = 360; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 1361 + 360 + 0 + 0 = 1721; Total number of LUTs after P&R: 2776 + 360 + 0 + 0 = 3136; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 39MB peak: 209MB) Process took 0h:00m:15s realtime, 0h:00m:15s cputime # Fri Mar 24 18:15:04 2017 ###########################################################]