| Project Settings |
|---|
| Project Name | Top_syn | Implementation Name | synthesis |
| Top Module | Top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
58 |
39 |
0 |
- |
00m:01s |
- |
4/10/2017
3:45:06 PM |
| (premap) | Complete |
31 |
18 |
0 |
0m:00s |
0m:00s |
137MB |
4/10/2017
3:45:08 PM |
| (fpga_mapper) | Complete |
30 |
13 |
0 |
0m:01s |
0m:01s |
137MB |
4/10/2017
3:45:09 PM |
| Multi-srs Generator |
Complete | | | | | | | 4/10/2017
3:45:07 PM |
| Area Summary |
|---|
| |
| Carry Cells | 28 |
Sequential Cells | 37 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 6 |
| Global Clock Buffers | 1 |
LUTs
(total_luts) | 31 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 394.9 MHz | 7.468 |
| my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 1 |
| |
|