| Project Settings |
|---|
| Project Name | eSRAM_eNVM_access_top_syn | Implementation Name | synthesis |
| Top Module | eSRAM_eNVM_access_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
49 |
222 |
0 |
- |
0m:01s |
- |
2/19/2016
3:36:54 PM |
| (premap) | Complete |
43 |
12 |
0 |
0m:00s |
0m:00s |
147MB |
2/19/2016
3:36:56 PM |
| (fpga_mapper) | Complete |
40 |
42 |
0 |
0m:02s |
0m:02s |
156MB |
2/19/2016
3:36:59 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/19/2016
3:36:55 PM |
| Area Summary |
|---|
| |
| Carry Cells | 63 |
Sequential Cells | 328 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 10 |
| Global Clock Buffers | 2 |
Block Rams (RAM1K18)
(v_ram) | 1 |
| LUTs
(total_luts) | 412 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 135.1 MHz | 2.596 |
| eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|