`timescale 1 ns/100 ps
// Version: v11.7 11.7.0.119


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_010(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM(
       RD_c,
       eSRAM_eNVM_RW_0_ram_wdata,
       eSRAM_eNVM_RW_0_ram_waddr,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_RW_0_ram_wen
    );
output [7:0] RD_c;
input  [31:0] eSRAM_eNVM_RW_0_ram_wdata;
input  [4:0] eSRAM_eNVM_RW_0_ram_waddr;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  eSRAM_eNVM_RW_0_ram_wen;

    wire VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    RAM1K18 eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0 (.A_DOUT({nc0, 
        nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17}), .B_DOUT({nc18, nc19, nc20, 
        nc21, nc22, nc23, nc24, nc25, nc26, nc27, RD_c[7], RD_c[6], 
        RD_c[5], RD_c[4], RD_c[3], RD_c[2], RD_c[1], RD_c[0]}), .BUSY()
        , .A_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .A_DOUT_CLK(VCC_net_1)
        , .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        GND_net_1, VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, 
        eSRAM_eNVM_RW_0_ram_wdata[31], eSRAM_eNVM_RW_0_ram_wdata[30], 
        eSRAM_eNVM_RW_0_ram_wdata[29], eSRAM_eNVM_RW_0_ram_wdata[28], 
        eSRAM_eNVM_RW_0_ram_wdata[27], eSRAM_eNVM_RW_0_ram_wdata[26], 
        eSRAM_eNVM_RW_0_ram_wdata[25], eSRAM_eNVM_RW_0_ram_wdata[24], 
        GND_net_1, eSRAM_eNVM_RW_0_ram_wdata[23], 
        eSRAM_eNVM_RW_0_ram_wdata[22], eSRAM_eNVM_RW_0_ram_wdata[21], 
        eSRAM_eNVM_RW_0_ram_wdata[20], eSRAM_eNVM_RW_0_ram_wdata[19], 
        eSRAM_eNVM_RW_0_ram_wdata[18], eSRAM_eNVM_RW_0_ram_wdata[17], 
        eSRAM_eNVM_RW_0_ram_wdata[16]}), .A_ADDR({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .A_WEN({VCC_net_1, VCC_net_1}), .B_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        eSRAM_eNVM_RW_0_ram_wen, VCC_net_1, VCC_net_1}), 
        .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, eSRAM_eNVM_RW_0_ram_wdata[15], 
        eSRAM_eNVM_RW_0_ram_wdata[14], eSRAM_eNVM_RW_0_ram_wdata[13], 
        eSRAM_eNVM_RW_0_ram_wdata[12], eSRAM_eNVM_RW_0_ram_wdata[11], 
        eSRAM_eNVM_RW_0_ram_wdata[10], eSRAM_eNVM_RW_0_ram_wdata[9], 
        eSRAM_eNVM_RW_0_ram_wdata[8], GND_net_1, 
        eSRAM_eNVM_RW_0_ram_wdata[7], eSRAM_eNVM_RW_0_ram_wdata[6], 
        eSRAM_eNVM_RW_0_ram_wdata[5], eSRAM_eNVM_RW_0_ram_wdata[4], 
        eSRAM_eNVM_RW_0_ram_wdata[3], eSRAM_eNVM_RW_0_ram_wdata[2], 
        eSRAM_eNVM_RW_0_ram_wdata[1], eSRAM_eNVM_RW_0_ram_wdata[0]}), 
        .B_ADDR({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        eSRAM_eNVM_RW_0_ram_waddr[4], eSRAM_eNVM_RW_0_ram_waddr[3], 
        eSRAM_eNVM_RW_0_ram_waddr[2], eSRAM_eNVM_RW_0_ram_waddr[1], 
        eSRAM_eNVM_RW_0_ram_waddr[0], GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .B_WEN({VCC_net_1, VCC_net_1}), .A_EN(
        VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({VCC_net_1, 
        GND_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({VCC_net_1, GND_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module CoreResetP_Z6(
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       SYSRESET_POR,
       eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F,
       eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N
    );
output eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  SYSRESET_POR;
input  eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F;
input  eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N;

    wire MSS_HPMS_READY_int_net_1, mss_ready_select_net_1, VCC_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        GND_net_1, mss_ready_state_net_1, RESET_N_M2F_clk_base_net_1, 
        POWER_ON_RESET_N_q1_net_1, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, MSS_HPMS_READY_int_4_net_1;
    
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_clk_base_net_1));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        SYSRESET_POR), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1)
        , .LAT(GND_net_1), .Q(POWER_ON_RESET_N_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(mss_ready_select4_net_1), 
        .ALn(POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_select_net_1));
    CLKINT MSS_HPMS_READY_int_RNISI68 (.A(MSS_HPMS_READY_int_net_1), 
        .Y(eSRAM_eNVM_access_0_HPMS_READY));
    GND GND (.Y(GND_net_1));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(RESET_N_M2F_clk_base_net_1)
        , .ALn(POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    VCC VCC (.Y(VCC_net_1));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_q1_net_1));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FIC_2_APB_M_PRESET_N_clk_base_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        SYSRESET_POR), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1)
        , .LAT(GND_net_1), .Q(POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FIC_2_APB_M_PRESET_N_q1_net_1));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       masterDataInProg,
       ahb_fsm_current_state_ns,
       ahb_fsm_current_state_6,
       ahb_fsm_current_state_0,
       ahb_fsm_current_state_1,
       ahb_fsm_current_state_4,
       ahb_fsm_current_state_2,
       ahb_fsm_current_state_5,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       HREADY_M_iv_i_0,
       N_51_0_i_0,
       HWDATA_1_sqmuxa,
       N_147_mux_i_0,
       N_136_mux,
       N_101_i_1,
       N_101_i_0,
       HREADY_M_pre37,
       CoreAHBLite_0_AHBmslave16_HREADY,
       DEFSLAVEDATASEL_8,
       DEFSLAVEDATASEL_7,
       DEFSLAVEDATASEL_6,
       PREVDATASLAVEREADY_iv_i_0,
       DATAOUT_1_sqmuxa,
       N_145,
       N_140,
       N_541_i_0,
       N_143_mux_i_0,
       N_144_mux_i_0,
       N_148_mux_i_0,
       N_126_i_0
    );
input  [0:0] masterDataInProg;
output [0:0] ahb_fsm_current_state_ns;
input  ahb_fsm_current_state_6;
input  ahb_fsm_current_state_0;
input  ahb_fsm_current_state_1;
input  ahb_fsm_current_state_4;
input  ahb_fsm_current_state_2;
input  ahb_fsm_current_state_5;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output HREADY_M_iv_i_0;
output N_51_0_i_0;
output HWDATA_1_sqmuxa;
output N_147_mux_i_0;
input  N_136_mux;
input  N_101_i_1;
output N_101_i_0;
input  HREADY_M_pre37;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  DEFSLAVEDATASEL_8;
input  DEFSLAVEDATASEL_7;
input  DEFSLAVEDATASEL_6;
output PREVDATASLAVEREADY_iv_i_0;
output DATAOUT_1_sqmuxa;
input  N_145;
input  N_140;
output N_541_i_0;
output N_143_mux_i_0;
output N_144_mux_i_0;
output N_148_mux_i_0;
output N_126_i_0;

    wire defSlaveSMCurrentState_net_1, VCC_net_1, defSlaveSMNextState, 
        GND_net_1;
    
    SLE defSlaveSMCurrentState (.D(defSlaveSMNextState), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState_net_1));
    CFG3 #( .INIT(8'hAE) )  defSlaveSMNextState_0_a3_RNI0PHL5 (.A(
        ahb_fsm_current_state_4), .B(ahb_fsm_current_state_5), .C(
        HREADY_M_iv_i_0), .Y(N_143_mux_i_0));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hAC0C) )  defSlaveSMNextState_0_a3_RNINU8I6 (.A(
        N_136_mux), .B(HREADY_M_iv_i_0), .C(N_145), .D(N_140), .Y(
        ahb_fsm_current_state_ns[0]));
    CFG4 #( .INIT(16'hEAFF) )  defSlaveSMNextState_0_a3_RNI3DHM5 (.A(
        ahb_fsm_current_state_2), .B(ahb_fsm_current_state_5), .C(
        HREADY_M_iv_i_0), .D(N_140), .Y(N_148_mux_i_0));
    CFG3 #( .INIT(8'h0D) )  defSlaveSMNextState_0_a3_RNI7JN65 (.A(
        HREADY_M_pre37), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        defSlaveSMNextState), .Y(PREVDATASLAVEREADY_iv_i_0));
    CFG4 #( .INIT(16'h00D5) )  defSlaveSMNextState_0_a3_RNINUHK5 (.A(
        HREADY_M_pre37), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        masterDataInProg[0]), .D(defSlaveSMNextState), .Y(
        HREADY_M_iv_i_0));
    CFG3 #( .INIT(8'hF8) )  defSlaveSMNextState_0_a3_RNITLHL5 (.A(
        HREADY_M_iv_i_0), .B(ahb_fsm_current_state_6), .C(
        ahb_fsm_current_state_0), .Y(N_51_0_i_0));
    CFG4 #( .INIT(16'h505C) )  defSlaveSMNextState_0_a3_RNI0VOH6 (.A(
        N_136_mux), .B(HREADY_M_iv_i_0), .C(ahb_fsm_current_state_0), 
        .D(N_101_i_1), .Y(N_101_i_0));
    CFG4 #( .INIT(16'h5554) )  defSlaveSMNextState_0_a3 (.A(
        defSlaveSMCurrentState_net_1), .B(DEFSLAVEDATASEL_8), .C(
        DEFSLAVEDATASEL_7), .D(DEFSLAVEDATASEL_6), .Y(
        defSlaveSMNextState));
    CFG3 #( .INIT(8'h37) )  defSlaveSMNextState_0_a3_RNIUMHL5 (.A(
        ahb_fsm_current_state_2), .B(HREADY_M_iv_i_0), .C(
        ahb_fsm_current_state_5), .Y(N_126_i_0));
    CFG3 #( .INIT(8'hFE) )  defSlaveSMNextState_0_a3_RNIEF1M5 (.A(
        ahb_fsm_current_state_1), .B(HWDATA_1_sqmuxa), .C(
        ahb_fsm_current_state_4), .Y(N_147_mux_i_0));
    CFG2 #( .INIT(4'h8) )  defSlaveSMNextState_0_a3_RNIDT1L5 (.A(
        HREADY_M_iv_i_0), .B(ahb_fsm_current_state_6), .Y(
        DATAOUT_1_sqmuxa));
    CFG3 #( .INIT(8'hAE) )  defSlaveSMNextState_0_a3_RNIQIHL5 (.A(
        ahb_fsm_current_state_1), .B(ahb_fsm_current_state_2), .C(
        HREADY_M_iv_i_0), .Y(N_144_mux_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'hD) )  defSlaveSMNextState_0_a3_RNI7N1L5 (.A(
        HREADY_M_iv_i_0), .B(ahb_fsm_current_state_0), .Y(N_541_i_0));
    CFG2 #( .INIT(4'h8) )  defSlaveSMNextState_0_a3_RNI9P1L5 (.A(
        HREADY_M_iv_i_0), .B(ahb_fsm_current_state_2), .Y(
        HWDATA_1_sqmuxa));
    
endmodule


module COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0(
       AHB_IF_0_BIF_1_HADDR,
       PREGATEDHADDR,
       AHB_IF_0_BIF_1_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave16_HSIZE,
       CoreAHBLite_0_AHBmslave16_HADDR,
       masterDataInProg,
       ahb_fsm_current_state_ns,
       regHADDR_28,
       regHADDR_0,
       regHADDR_1,
       regHADDR_2,
       regHADDR_3,
       regHADDR_4,
       regHADDR_5,
       regHADDR_6,
       arbRegSMCurrentState_0,
       arbRegSMCurrentState_12,
       M0GATEDHADDR_2,
       M0GATEDHADDR_0,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       m0s16AddrSel,
       AHB_IF_0_BIF_1_HWRITE,
       masterRegAddrSel,
       MASTERADDRINPROG_i_a2_out,
       HREADY_M_pre37,
       s16m0AddrReady,
       HREADY_M_iv_i_0,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       N_55_0,
       N_152,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       m21_N_10_i_0,
       N_51_0_i_0,
       HWDATA_1_sqmuxa,
       N_147_mux_i_0,
       N_101_i_0,
       CoreAHBLite_0_AHBmslave16_HREADY,
       DATAOUT_1_sqmuxa,
       N_541_i_0,
       N_143_mux_i_0,
       N_144_mux_i_0,
       N_148_mux_i_0,
       N_126_i_0
    );
input  [31:2] AHB_IF_0_BIF_1_HADDR;
output [28:28] PREGATEDHADDR;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [6:0] ahb_fsm_current_state;
output [1:1] CoreAHBLite_0_AHBmslave16_HSIZE;
output [27:9] CoreAHBLite_0_AHBmslave16_HADDR;
input  [0:0] masterDataInProg;
output [0:0] ahb_fsm_current_state_ns;
output regHADDR_28;
output regHADDR_0;
output regHADDR_1;
output regHADDR_2;
output regHADDR_3;
output regHADDR_4;
output regHADDR_5;
output regHADDR_6;
input  arbRegSMCurrentState_0;
input  arbRegSMCurrentState_12;
output M0GATEDHADDR_2;
output M0GATEDHADDR_0;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output m0s16AddrSel;
input  AHB_IF_0_BIF_1_HWRITE;
output masterRegAddrSel;
input  MASTERADDRINPROG_i_a2_out;
output HREADY_M_pre37;
input  s16m0AddrReady;
output HREADY_M_iv_i_0;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;
output N_55_0;
input  N_152;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output m21_N_10_i_0;
output N_51_0_i_0;
output HWDATA_1_sqmuxa;
output N_147_mux_i_0;
output N_101_i_0;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output DATAOUT_1_sqmuxa;
output N_541_i_0;
output N_143_mux_i_0;
output N_144_mux_i_0;
output N_148_mux_i_0;
output N_126_i_0;

    wire \regHADDR[24]_net_1 , VCC_net_1, masterAddrClockEnable_net_1, 
        GND_net_1, \regHADDR[25]_net_1 , \regHADDR[26]_net_1 , 
        \regHADDR[27]_net_1 , \regHADDR[29]_net_1 , 
        \regHADDR[9]_net_1 , \regHADDR[10]_net_1 , 
        \regHADDR[11]_net_1 , \regHADDR[12]_net_1 , 
        \regHADDR[13]_net_1 , \regHADDR[14]_net_1 , 
        \regHADDR[15]_net_1 , \regHADDR[16]_net_1 , 
        \regHADDR[17]_net_1 , \regHADDR[18]_net_1 , 
        \regHADDR[19]_net_1 , \regHADDR[20]_net_1 , 
        \regHADDR[21]_net_1 , \regHADDR[22]_net_1 , 
        \regHADDR[23]_net_1 , \SDATASELInt[12]_net_1 , 
        \SADDRSEL[12]_net_1 , PREVDATASLAVEREADY_iv_i_0, 
        \SDATASELInt[13]_net_1 , \SADDRSEL[13]_net_1 , 
        \SDATASELInt[14]_net_1 , \SADDRSEL[14]_net_1 , 
        \SDATASELInt[15]_net_1 , \SADDRSEL[15]_net_1 , m0s16DataSel, 
        \SDATASELInt[1]_net_1 , \SADDRSEL[1]_net_1 , 
        \SDATASELInt[3]_net_1 , \SADDRSEL[3]_net_1 , 
        \SDATASELInt[5]_net_1 , \SADDRSEL[5]_net_1 , 
        \SDATASELInt[7]_net_1 , \SADDRSEL[7]_net_1 , 
        \SDATASELInt[8]_net_1 , \SADDRSEL[8]_net_1 , 
        \SDATASELInt[9]_net_1 , \SADDRSEL[9]_net_1 , 
        \SDATASELInt[10]_net_1 , \SADDRSEL[10]_net_1 , 
        \SDATASELInt[11]_net_1 , \SADDRSEL[11]_net_1 , regHWRITE_net_1, 
        regHTRANS_net_1, d_masterRegAddrSel_net_1, m21_N_12, N_3_0, 
        m7_e_1, m7_e_7, m7_e_8, N_101_i_1_net_1, N_140, 
        \SADDRSEL_2[3] , N_145, DEFSLAVEDATASEL_8_net_1, 
        DEFSLAVEDATASEL_7_net_1, DEFSLAVEDATASEL_6_net_1, N_136_mux, 
        \SADDRSEL_1[5]_net_1 , \SADDRSEL_1[7] , m21_m7_i_0, m21_N_13, 
        \SADDRSEL_3[9] ;
    
    CFG4 #( .INIT(16'h0400) )  \SADDRSEL[12]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[5]_net_1 ), .Y(
        \SADDRSEL[12]_net_1 ));
    CFG2 #( .INIT(4'h1) )  N_101_i_1 (.A(ahb_fsm_current_state[2]), .B(
        ahb_fsm_current_state[5]), .Y(N_101_i_1_net_1));
    SLE \regHADDR[21]  (.D(AHB_IF_0_BIF_1_HADDR[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[21]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \SADDRSEL_1[3]  (.A(N_3_0), .B(
        M0GATEDHADDR_0), .Y(\SADDRSEL_1[7] ));
    CFG2 #( .INIT(4'h4) )  \PREGATEDHADDR[31]  (.A(masterRegAddrSel), 
        .B(AHB_IF_0_BIF_1_HADDR[31]), .Y(M0GATEDHADDR_2));
    CFG2 #( .INIT(4'h1) )  \SADDRSEL_2[1]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        \SADDRSEL_2[3] ));
    SLE \regHADDR[15]  (.D(AHB_IF_0_BIF_1_HADDR[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[15]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  \SADDRSEL[13]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[5]_net_1 ), .Y(
        \SADDRSEL[13]_net_1 ));
    SLE \regHADDR[30]  (.D(AHB_IF_0_BIF_1_HADDR[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_28));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIB1CE1[10]  (.A(
        AHB_IF_0_BIF_1_HADDR[10]), .B(\regHADDR[10]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[10]));
    SLE \regHADDR[7]  (.D(AHB_IF_0_BIF_1_HADDR[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_5));
    CFG4 #( .INIT(16'h2000) )  \SADDRSEL[1]  (.A(
        AHB_IF_0_BIF_1_HTRANS[1]), .B(AHB_IF_0_BIF_1_HADDR[29]), .C(
        \SADDRSEL_2[3] ), .D(PREGATEDHADDR[28]), .Y(
        \SADDRSEL[1]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIJBEE1[23]  (.A(
        AHB_IF_0_BIF_1_HADDR[23]), .B(\regHADDR[23]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[23]));
    CFG2 #( .INIT(4'h8) )  \SADDRSEL[9]  (.A(\SADDRSEL_3[9] ), .B(
        PREGATEDHADDR[28]), .Y(\SADDRSEL[9]_net_1 ));
    CFG4 #( .INIT(16'h000D) )  \SADDRSEL[16]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(masterRegAddrSel), .C(N_3_0), .D(
        M0GATEDHADDR_2), .Y(m0s16AddrSel));
    CFG3 #( .INIT(8'hC4) )  regHTRANS_RNID4R51 (.A(masterRegAddrSel), 
        .B(N_152), .C(regHTRANS_net_1), .Y(
        CoreAHBLite_0_AHBmslave16_HSIZE[1]));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNILBCE1[15]  (.A(
        AHB_IF_0_BIF_1_HADDR[15]), .B(\regHADDR[15]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[15]));
    SLE \regHADDR[9]  (.D(AHB_IF_0_BIF_1_HADDR[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[9]_net_1 ));
    CFG4 #( .INIT(16'h4000) )  \SADDRSEL[11]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[7] ), .Y(
        \SADDRSEL[11]_net_1 ));
    SLE masterRegAddrSel_inst_1 (.D(d_masterRegAddrSel_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        masterRegAddrSel));
    CFG2 #( .INIT(4'h1) )  m47_0 (.A(ahb_fsm_current_state[1]), .B(
        ahb_fsm_current_state[4]), .Y(N_140));
    SLE regHTRANS (.D(VCC_net_1), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .EN(masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        regHTRANS_net_1));
    CFG4 #( .INIT(16'h0100) )  \SDATASELInt_RNIB9PD1[11]  (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[11]_net_1 ), .C(
        \SDATASELInt[8]_net_1 ), .D(m0s16DataSel), .Y(m7_e_1));
    VCC VCC (.Y(VCC_net_1));
    SLE \regHADDR[29]  (.D(AHB_IF_0_BIF_1_HADDR[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[29]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  \SADDRSEL[15]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[7] ), .Y(
        \SADDRSEL[15]_net_1 ));
    SLE \regHADDR[24]  (.D(AHB_IF_0_BIF_1_HADDR[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[24]_net_1 ));
    CFG4 #( .INIT(16'hCEDF) )  regHTRANS_RNIPMUJ1 (.A(masterRegAddrSel)
        , .B(m21_N_12), .C(regHTRANS_net_1), .D(
        AHB_IF_0_BIF_1_HTRANS[1]), .Y(m21_m7_i_0));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIJ9CE1[14]  (.A(
        AHB_IF_0_BIF_1_HADDR[14]), .B(\regHADDR[14]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[14]));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIRFQ41[9]  (.A(
        AHB_IF_0_BIF_1_HADDR[9]), .B(\regHADDR[9]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[9]));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_7 (.A(
        \SDATASELInt[7]_net_1 ), .B(\SDATASELInt[5]_net_1 ), .C(
        \SDATASELInt[3]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        DEFSLAVEDATASEL_7_net_1));
    SLE \regHADDR[10]  (.D(AHB_IF_0_BIF_1_HADDR[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[10]_net_1 ));
    SLE \regHADDR[13]  (.D(AHB_IF_0_BIF_1_HADDR[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[13]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNID5EE1[20]  (.A(
        AHB_IF_0_BIF_1_HADDR[20]), .B(\regHADDR[20]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[20]));
    SLE \regHADDR[12]  (.D(AHB_IF_0_BIF_1_HADDR[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[12]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIPHEE1[26]  (.A(
        AHB_IF_0_BIF_1_HADDR[26]), .B(\regHADDR[26]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[26]));
    SLE \regHADDR[5]  (.D(AHB_IF_0_BIF_1_HADDR[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_3));
    CFG2 #( .INIT(4'h2) )  \SADDRSEL[8]  (.A(\SADDRSEL_3[9] ), .B(
        PREGATEDHADDR[28]), .Y(\SADDRSEL[8]_net_1 ));
    SLE \regHADDR[2]  (.D(AHB_IF_0_BIF_1_HADDR[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_0));
    SLE \SDATASELInt[15]  (.D(\SADDRSEL[15]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[15]_net_1 ));
    CFG4 #( .INIT(16'h0400) )  \SADDRSEL[10]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[7] ), .Y(
        \SADDRSEL[10]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNID3CE1[11]  (.A(
        AHB_IF_0_BIF_1_HADDR[11]), .B(\regHADDR[11]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[11]));
    CFG2 #( .INIT(4'h4) )  \PREGATEDHADDR[28]  (.A(masterRegAddrSel), 
        .B(AHB_IF_0_BIF_1_HADDR[28]), .Y(PREGATEDHADDR[28]));
    SLE \SDATASELInt[14]  (.D(\SADDRSEL[14]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[14]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNIP02H1[13]  (.A(
        \SDATASELInt[14]_net_1 ), .B(\SDATASELInt[13]_net_1 ), .C(
        \SDATASELInt[9]_net_1 ), .D(\SDATASELInt[3]_net_1 ), .Y(m7_e_7)
        );
    SLE \regHADDR[8]  (.D(AHB_IF_0_BIF_1_HADDR[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_6));
    SLE \regHADDR[25]  (.D(AHB_IF_0_BIF_1_HADDR[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[25]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNINFEE1[25]  (.A(
        AHB_IF_0_BIF_1_HADDR[25]), .B(\regHADDR[25]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[25]));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNINDCE1[16]  (.A(
        AHB_IF_0_BIF_1_HADDR[16]), .B(\regHADDR[16]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[16]));
    SLE \regHADDR[17]  (.D(AHB_IF_0_BIF_1_HADDR[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[17]_net_1 ));
    CFG4 #( .INIT(16'h0054) )  \SDATASELInt_RNISP6E8[16]  (.A(m21_N_13)
        , .B(m0s16DataSel), .C(PREVDATASLAVEREADY_iv_i_0), .D(
        m21_m7_i_0), .Y(m21_N_10_i_0));
    CFG4 #( .INIT(16'h2000) )  \SADDRSEL[7]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        \SADDRSEL_1[7] ), .D(PREGATEDHADDR[28]), .Y(
        \SADDRSEL[7]_net_1 ));
    CFG3 #( .INIT(8'h04) )  masterAddrClockEnable (.A(s16m0AddrReady), 
        .B(HREADY_M_iv_i_0), .C(masterRegAddrSel), .Y(
        masterAddrClockEnable_net_1));
    SLE \regHADDR[6]  (.D(AHB_IF_0_BIF_1_HADDR[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_4));
    SLE \regHADDR[16]  (.D(AHB_IF_0_BIF_1_HADDR[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[16]_net_1 ));
    SLE \SDATASELInt[13]  (.D(\SADDRSEL[13]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[13]_net_1 ));
    CFG4 #( .INIT(16'h0040) )  \SADDRSEL_3[8]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(AHB_IF_0_BIF_1_HTRANS[1]), .C(
        M0GATEDHADDR_2), .D(M0GATEDHADDR_0), .Y(\SADDRSEL_3[9] ));
    SLE regHWRITE (.D(AHB_IF_0_BIF_1_HWRITE), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        regHWRITE_net_1));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_6 (.A(
        \SDATASELInt[11]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[9]_net_1 ), .D(\SDATASELInt[8]_net_1 ), .Y(
        DEFSLAVEDATASEL_6_net_1));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIF5CE1[12]  (.A(
        AHB_IF_0_BIF_1_HADDR[12]), .B(\regHADDR[12]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[12]));
    CFG3 #( .INIT(8'h54) )  d_masterRegAddrSel (.A(s16m0AddrReady), .B(
        HREADY_M_iv_i_0), .C(masterRegAddrSel), .Y(
        d_masterRegAddrSel_net_1));
    SLE \SDATASELInt[9]  (.D(\SADDRSEL[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[9]_net_1 ));
    SLE \SDATASELInt[1]  (.D(\SADDRSEL[1]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[1]_net_1 ));
    SLE \SDATASELInt[12]  (.D(\SADDRSEL[12]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[12]_net_1 ));
    SLE \regHADDR[11]  (.D(AHB_IF_0_BIF_1_HADDR[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[11]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  \SADDRSEL[5]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        \SADDRSEL_1[5]_net_1 ), .D(PREGATEDHADDR[28]), .Y(
        \SADDRSEL[5]_net_1 ));
    SLE \SDATASELInt[5]  (.D(\SADDRSEL[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[5]_net_1 ));
    SLE \regHADDR[3]  (.D(AHB_IF_0_BIF_1_HADDR[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_1));
    CFG4 #( .INIT(16'h0800) )  \SADDRSEL[14]  (.A(
        AHB_IF_0_BIF_1_HADDR[30]), .B(M0GATEDHADDR_2), .C(
        PREGATEDHADDR[28]), .D(\SADDRSEL_1[7] ), .Y(
        \SADDRSEL[14]_net_1 ));
    CFG3 #( .INIT(8'h10) )  m21_m7_i_a5 (.A(arbRegSMCurrentState_0), 
        .B(arbRegSMCurrentState_12), .C(MASTERADDRINPROG_i_a2_out), .Y(
        m21_N_12));
    SLE \SDATASELInt[3]  (.D(\SADDRSEL[3]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[3]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNITJCE1[19]  (.A(
        AHB_IF_0_BIF_1_HADDR[19]), .B(\regHADDR[19]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[19]));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIRHCE1[18]  (.A(
        AHB_IF_0_BIF_1_HADDR[18]), .B(\regHADDR[18]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[18]));
    SLE \regHADDR[20]  (.D(AHB_IF_0_BIF_1_HADDR[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[20]_net_1 ));
    CFG4 #( .INIT(16'h0E00) )  masterRegAddrSel_RNIKAS81 (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        masterRegAddrSel), .D(MASTERADDRINPROG_i_a2_out), .Y(m21_N_13));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIH9EE1[22]  (.A(
        AHB_IF_0_BIF_1_HADDR[22]), .B(\regHADDR[22]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[22]));
    SLE \regHADDR[23]  (.D(AHB_IF_0_BIF_1_HADDR[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[23]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  m60 (.A(eSRAM_eNVM_RW_0_WRITE), .B(
        eSRAM_eNVM_RW_0_READ), .C(ahb_fsm_current_state[2]), .D(
        ahb_fsm_current_state[5]), .Y(N_136_mux));
    SLE \regHADDR[22]  (.D(AHB_IF_0_BIF_1_HADDR[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[22]_net_1 ));
    SLE \SDATASELInt[7]  (.D(\SADDRSEL[7]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[7]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIRJEE1[27]  (.A(
        AHB_IF_0_BIF_1_HADDR[27]), .B(\regHADDR[27]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[27]));
    CFG4 #( .INIT(16'h3120) )  \SADDRSEL_1[5]  (.A(masterRegAddrSel), 
        .B(N_3_0), .C(regHADDR_28), .D(AHB_IF_0_BIF_1_HADDR[30]), .Y(
        \SADDRSEL_1[5]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_8 (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[14]_net_1 ), .C(
        \SDATASELInt[13]_net_1 ), .D(\SDATASELInt[12]_net_1 ), .Y(
        DEFSLAVEDATASEL_8_net_1));
    CFG4 #( .INIT(16'h2000) )  \SDATASELInt_RNIAUPT4[10]  (.A(m7_e_1), 
        .B(\SDATASELInt[10]_net_1 ), .C(m7_e_7), .D(m7_e_8), .Y(
        HREADY_M_pre37));
    CFG3 #( .INIT(8'hD8) )  \PREGATEDHADDR[29]  (.A(masterRegAddrSel), 
        .B(\regHADDR[29]_net_1 ), .C(AHB_IF_0_BIF_1_HADDR[29]), .Y(
        M0GATEDHADDR_0));
    CFG2 #( .INIT(4'h1) )  m69_e (.A(ahb_fsm_current_state[6]), .B(
        ahb_fsm_current_state[3]), .Y(N_145));
    CFG4 #( .INIT(16'hE0EF) )  m54 (.A(eSRAM_eNVM_RW_0_READ), .B(
        eSRAM_eNVM_RW_0_WRITE), .C(ahb_fsm_current_state[0]), .D(N_145)
        , .Y(N_55_0));
    SLE \regHADDR[19]  (.D(AHB_IF_0_BIF_1_HADDR[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[19]_net_1 ));
    SLE \regHADDR[14]  (.D(AHB_IF_0_BIF_1_HADDR[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[14]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIF7EE1[21]  (.A(
        AHB_IF_0_BIF_1_HADDR[21]), .B(\regHADDR[21]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[21]));
    SLE \regHADDR[27]  (.D(AHB_IF_0_BIF_1_HADDR[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[27]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNI4LAK1[12]  (.A(
        \SDATASELInt[12]_net_1 ), .B(\SDATASELInt[7]_net_1 ), .C(
        \SDATASELInt[5]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(m7_e_8)
        );
    SLE \SDATASELInt[16]  (.D(m0s16AddrSel), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(m0s16DataSel));
    CFG3 #( .INIT(8'h80) )  \SADDRSEL[3]  (.A(\SADDRSEL_1[7] ), .B(
        \SADDRSEL_2[3] ), .C(PREGATEDHADDR[28]), .Y(
        \SADDRSEL[3]_net_1 ));
    SLE \regHADDR[18]  (.D(AHB_IF_0_BIF_1_HADDR[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[18]_net_1 ));
    SLE \SDATASELInt[11]  (.D(\SADDRSEL[11]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[11]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIH7CE1[13]  (.A(
        AHB_IF_0_BIF_1_HADDR[13]), .B(\regHADDR[13]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[13]));
    SLE \SDATASELInt[8]  (.D(\SADDRSEL[8]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[8]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  regHWRITE_RNIPN891 (.A(
        AHB_IF_0_BIF_1_HWRITE), .B(regHWRITE_net_1), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HWRITE));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNILDEE1[24]  (.A(
        AHB_IF_0_BIF_1_HADDR[24]), .B(\regHADDR[24]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[24]));
    SLE \regHADDR[4]  (.D(AHB_IF_0_BIF_1_HADDR[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_2));
    SLE \regHADDR[26]  (.D(AHB_IF_0_BIF_1_HADDR[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        masterAddrClockEnable_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[26]_net_1 ));
    SLE \SDATASELInt[10]  (.D(\SADDRSEL[10]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[10]_net_1 ));
    CFG3 #( .INIT(8'h27) )  regHTRANS_RNIG5VV (.A(masterRegAddrSel), 
        .B(regHTRANS_net_1), .C(AHB_IF_0_BIF_1_HTRANS[1]), .Y(N_3_0));
    CFG4 #( .INIT(16'hC0A0) )  \regHADDR_RNIPFCE1[17]  (.A(
        AHB_IF_0_BIF_1_HADDR[17]), .B(\regHADDR[17]_net_1 ), .C(N_152), 
        .D(masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[17]));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (
        .masterDataInProg({masterDataInProg[0]}), 
        .ahb_fsm_current_state_ns({ahb_fsm_current_state_ns[0]}), 
        .ahb_fsm_current_state_6(ahb_fsm_current_state[6]), 
        .ahb_fsm_current_state_0(ahb_fsm_current_state[0]), 
        .ahb_fsm_current_state_1(ahb_fsm_current_state[1]), 
        .ahb_fsm_current_state_4(ahb_fsm_current_state[4]), 
        .ahb_fsm_current_state_2(ahb_fsm_current_state[2]), 
        .ahb_fsm_current_state_5(ahb_fsm_current_state[5]), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .HREADY_M_iv_i_0(HREADY_M_iv_i_0), .N_51_0_i_0(N_51_0_i_0), 
        .HWDATA_1_sqmuxa(HWDATA_1_sqmuxa), .N_147_mux_i_0(
        N_147_mux_i_0), .N_136_mux(N_136_mux), .N_101_i_1(
        N_101_i_1_net_1), .N_101_i_0(N_101_i_0), .HREADY_M_pre37(
        HREADY_M_pre37), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .DEFSLAVEDATASEL_8(
        DEFSLAVEDATASEL_8_net_1), .DEFSLAVEDATASEL_7(
        DEFSLAVEDATASEL_7_net_1), .DEFSLAVEDATASEL_6(
        DEFSLAVEDATASEL_6_net_1), .PREVDATASLAVEREADY_iv_i_0(
        PREVDATASLAVEREADY_iv_i_0), .DATAOUT_1_sqmuxa(DATAOUT_1_sqmuxa)
        , .N_145(N_145), .N_140(N_140), .N_541_i_0(N_541_i_0), 
        .N_143_mux_i_0(N_143_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), 
        .N_148_mux_i_0(N_148_mux_i_0), .N_126_i_0(N_126_i_0));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z4_1(
       arbRegSMCurrentState_1,
       arbRegSMCurrentState_13,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       m0s16AddrSel,
       CoreAHBLite_0_AHBmslave16_HREADY,
       MASTERADDRINPROG_i_a2_out,
       N_156,
       N_152,
       s16m0AddrReady
    );
output arbRegSMCurrentState_1;
output arbRegSMCurrentState_13;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  m0s16AddrSel;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output MASTERADDRINPROG_i_a2_out;
output N_156;
output N_152;
output s16m0AddrReady;

    wire \arbRegSMCurrentState[0]_net_1 , VCC_net_1, N_104_i_0, 
        GND_net_1, N_106_i_0, \arbRegSMCurrentState[2]_net_1 , 
        N_108_i_0, \arbRegSMCurrentState[3]_net_1 , N_110_i_0, 
        N_106_i_1;
    
    CFG3 #( .INIT(8'h73) )  \MASTERADDRINPROG_i_a2[0]  (.A(N_156), .B(
        MASTERADDRINPROG_i_a2_out), .C(m0s16AddrSel), .Y(N_152));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[2]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_108_i_0));
    CFG4 #( .INIT(16'hFEF2) )  \arbRegSMCurrentState_RNO[1]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_106_i_1), .C(
        \arbRegSMCurrentState[2]_net_1 ), .D(arbRegSMCurrentState_1), 
        .Y(N_106_i_0));
    CFG2 #( .INIT(4'h1) )  \MASTERADDRINPROG_i_a2_s[0]  (.A(
        \arbRegSMCurrentState[0]_net_1 ), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(MASTERADDRINPROG_i_a2_out)
        );
    GND GND (.Y(GND_net_1));
    SLE \arbRegSMCurrentState[1]  (.D(N_106_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_1));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[3]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_110_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h1) )  \arbRegSMCurrentState_ns_i_a2_0[0]  (.A(
        arbRegSMCurrentState_1), .B(arbRegSMCurrentState_13), .Y(N_156)
        );
    SLE \arbRegSMCurrentState[13]  (.D(GND_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(m0s16AddrSel), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_13));
    CFG4 #( .INIT(16'h3032) )  \arbRegSMCurrentState_RNO[0]  (.A(
        m0s16AddrSel), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        \arbRegSMCurrentState[0]_net_1 ), .D(N_156), .Y(N_104_i_0));
    SLE \arbRegSMCurrentState[3]  (.D(N_110_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[3]_net_1 ));
    SLE \arbRegSMCurrentState[2]  (.D(N_108_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[2]_net_1 ));
    CFG4 #( .INIT(16'h5DDD) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIGLU31[0]  (.A(m0s16AddrSel), 
        .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(N_156), .D(
        MASTERADDRINPROG_i_a2_out), .Y(s16m0AddrReady));
    SLE \arbRegSMCurrentState[0]  (.D(N_104_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[0]_net_1 ));
    CFG4 #( .INIT(16'h115D) )  \arbRegSMCurrentState_RNO_0[1]  (.A(
        m0s16AddrSel), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        arbRegSMCurrentState_13), .D(\arbRegSMCurrentState[0]_net_1 ), 
        .Y(N_106_i_1));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_0(
       masterDataInProg,
       PREGATEDHADDR,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       M0GATEDHADDR_0,
       M0GATEDHADDR_2,
       AHB_IF_0_BIF_1_HADDR_1,
       AHB_IF_0_BIF_1_HADDR_2,
       AHB_IF_0_BIF_1_HADDR_3,
       AHB_IF_0_BIF_1_HADDR_4,
       AHB_IF_0_BIF_1_HADDR_5,
       AHB_IF_0_BIF_1_HADDR_6,
       AHB_IF_0_BIF_1_HADDR_28,
       AHB_IF_0_BIF_1_HADDR_0,
       regHADDR_1,
       regHADDR_2,
       regHADDR_3,
       regHADDR_4,
       regHADDR_5,
       regHADDR_6,
       regHADDR_28,
       regHADDR_0,
       CoreAHBLite_0_AHBmslave16_HADDR_27,
       CoreAHBLite_0_AHBmslave16_HADDR_29,
       CoreAHBLite_0_AHBmslave16_HADDR_26,
       CoreAHBLite_0_AHBmslave16_HADDR_1,
       CoreAHBLite_0_AHBmslave16_HADDR_2,
       CoreAHBLite_0_AHBmslave16_HADDR_3,
       CoreAHBLite_0_AHBmslave16_HADDR_4,
       CoreAHBLite_0_AHBmslave16_HADDR_5,
       CoreAHBLite_0_AHBmslave16_HADDR_6,
       CoreAHBLite_0_AHBmslave16_HADDR_28,
       CoreAHBLite_0_AHBmslave16_HADDR_0,
       arbRegSMCurrentState_0,
       arbRegSMCurrentState_12,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       N_152,
       CoreAHBLite_0_AHBmslave16_HREADY,
       m0s16AddrSel,
       MASTERADDRINPROG_i_a2_out,
       masterRegAddrSel,
       s16m0AddrReady
    );
output [0:0] masterDataInProg;
input  [28:28] PREGATEDHADDR;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  M0GATEDHADDR_0;
input  M0GATEDHADDR_2;
input  AHB_IF_0_BIF_1_HADDR_1;
input  AHB_IF_0_BIF_1_HADDR_2;
input  AHB_IF_0_BIF_1_HADDR_3;
input  AHB_IF_0_BIF_1_HADDR_4;
input  AHB_IF_0_BIF_1_HADDR_5;
input  AHB_IF_0_BIF_1_HADDR_6;
input  AHB_IF_0_BIF_1_HADDR_28;
input  AHB_IF_0_BIF_1_HADDR_0;
input  regHADDR_1;
input  regHADDR_2;
input  regHADDR_3;
input  regHADDR_4;
input  regHADDR_5;
input  regHADDR_6;
input  regHADDR_28;
input  regHADDR_0;
output CoreAHBLite_0_AHBmslave16_HADDR_27;
output CoreAHBLite_0_AHBmslave16_HADDR_29;
output CoreAHBLite_0_AHBmslave16_HADDR_26;
output CoreAHBLite_0_AHBmslave16_HADDR_1;
output CoreAHBLite_0_AHBmslave16_HADDR_2;
output CoreAHBLite_0_AHBmslave16_HADDR_3;
output CoreAHBLite_0_AHBmslave16_HADDR_4;
output CoreAHBLite_0_AHBmslave16_HADDR_5;
output CoreAHBLite_0_AHBmslave16_HADDR_6;
output CoreAHBLite_0_AHBmslave16_HADDR_28;
output CoreAHBLite_0_AHBmslave16_HADDR_0;
output arbRegSMCurrentState_0;
output arbRegSMCurrentState_12;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output N_152;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  m0s16AddrSel;
output MASTERADDRINPROG_i_a2_out;
input  masterRegAddrSel;
output s16m0AddrReady;

    wire VCC_net_1, GND_net_1, N_156;
    
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[4]  (.A(AHB_IF_0_BIF_1_HADDR_2), 
        .B(regHADDR_2), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_2));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[5]  (.A(AHB_IF_0_BIF_1_HADDR_3), 
        .B(regHADDR_3), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_3));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[30]  (.A(AHB_IF_0_BIF_1_HADDR_28)
        , .B(regHADDR_28), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_28));
    CFG2 #( .INIT(4'h8) )  \HWDATA[22]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[22]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[22]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[20]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[20]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[20]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[23]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[23]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[23]));
    CFG4 #( .INIT(16'h08AA) )  \HADDR[31]  (.A(M0GATEDHADDR_2), .B(
        m0s16AddrSel), .C(N_156), .D(MASTERADDRINPROG_i_a2_out), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_29));
    CFG2 #( .INIT(4'h8) )  \HWDATA[12]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[12]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[12]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[29]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[29]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[29]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[10]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[10]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[10]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[31]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[31]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[31]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[13]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[13]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[13]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[0]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[0]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[0]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[4]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[4]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[4]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[28]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[28]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[28]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[19]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[19]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[19]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[25]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[25]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[25]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[24]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[24]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[24]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[27]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[27]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[27]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[18]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[18]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[18]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[3]  (.A(AHB_IF_0_BIF_1_HADDR_1), 
        .B(regHADDR_1), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_1));
    GND GND (.Y(GND_net_1));
    SLE \masterDataInProg[0]  (.D(N_152), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        CoreAHBLite_0_AHBmslave16_HREADY), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        masterDataInProg[0]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[15]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[15]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[15]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[14]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[14]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[14]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[8]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[8]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[8]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[6]  (.A(AHB_IF_0_BIF_1_HADDR_4), 
        .B(regHADDR_4), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_4));
    CFG2 #( .INIT(4'h8) )  \HWDATA[3]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[3]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[3]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[17]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[17]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[17]));
    CFG4 #( .INIT(16'h08AA) )  \HADDR[29]  (.A(M0GATEDHADDR_0), .B(
        m0s16AddrSel), .C(N_156), .D(MASTERADDRINPROG_i_a2_out), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_27));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[7]  (.A(AHB_IF_0_BIF_1_HADDR_5), 
        .B(regHADDR_5), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_5));
    CFG2 #( .INIT(4'h8) )  \HWDATA[5]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[5]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[5]));
    CFG4 #( .INIT(16'h08AA) )  \HADDR[28]  (.A(PREGATEDHADDR[28]), .B(
        m0s16AddrSel), .C(N_156), .D(MASTERADDRINPROG_i_a2_out), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_26));
    CFG2 #( .INIT(4'h8) )  \HWDATA[30]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[30]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[30]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[9]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[9]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[9]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[7]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[7]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[7]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[1]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[1]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[1]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[6]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[6]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[6]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[8]  (.A(AHB_IF_0_BIF_1_HADDR_6), 
        .B(regHADDR_6), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_6));
    COREAHBLITE_SLAVEARBITER_Z4_1 slave_arbiter (
        .arbRegSMCurrentState_1(arbRegSMCurrentState_0), 
        .arbRegSMCurrentState_13(arbRegSMCurrentState_12), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .m0s16AddrSel(m0s16AddrSel), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .MASTERADDRINPROG_i_a2_out(
        MASTERADDRINPROG_i_a2_out), .N_156(N_156), .N_152(N_152), 
        .s16m0AddrReady(s16m0AddrReady));
    CFG2 #( .INIT(4'h8) )  \HWDATA[21]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[21]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[21]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[26]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[26]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[26]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[2]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[2]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[2]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[11]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[11]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[11]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[16]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[16]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[16]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR[2]  (.A(AHB_IF_0_BIF_1_HADDR_0), 
        .B(regHADDR_0), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR_0));
    
endmodule


module COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave16_HSIZE,
       ahb_fsm_current_state_ns,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_pre37,
       HREADY_M_iv_i_0,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       N_55_0,
       N_152,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       m21_N_10_i_0,
       N_51_0_i_0,
       HWDATA_1_sqmuxa,
       N_147_mux_i_0,
       N_101_i_0,
       CoreAHBLite_0_AHBmslave16_HREADY,
       DATAOUT_1_sqmuxa,
       N_541_i_0,
       N_143_mux_i_0,
       N_144_mux_i_0,
       N_148_mux_i_0,
       N_126_i_0
    );
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [6:0] ahb_fsm_current_state;
output [1:1] CoreAHBLite_0_AHBmslave16_HSIZE;
output [0:0] ahb_fsm_current_state_ns;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [31:2] CoreAHBLite_0_AHBmslave16_HADDR;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  AHB_IF_0_BIF_1_HWRITE;
output HREADY_M_pre37;
output HREADY_M_iv_i_0;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;
output N_55_0;
output N_152;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output m21_N_10_i_0;
output N_51_0_i_0;
output HWDATA_1_sqmuxa;
output N_147_mux_i_0;
output N_101_i_0;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output DATAOUT_1_sqmuxa;
output N_541_i_0;
output N_143_mux_i_0;
output N_144_mux_i_0;
output N_148_mux_i_0;
output N_126_i_0;

    wire \regHADDR[30] , \regHADDR[2] , \regHADDR[3] , \regHADDR[4] , 
        \regHADDR[5] , \regHADDR[6] , \regHADDR[7] , \regHADDR[8] , 
        \arbRegSMCurrentState[1] , \arbRegSMCurrentState[13] , 
        \PREGATEDHADDR[28] , \M0GATEDHADDR[31] , \M0GATEDHADDR[29] , 
        \masterDataInProg[0] , m0s16AddrSel, masterRegAddrSel, 
        MASTERADDRINPROG_i_a2_out, s16m0AddrReady, GND_net_1, 
        VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 masterstage_0 (
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .PREGATEDHADDR({\PREGATEDHADDR[28] })
        , .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .ahb_fsm_current_state({ahb_fsm_current_state[6], 
        ahb_fsm_current_state[5], ahb_fsm_current_state[4], 
        ahb_fsm_current_state[3], ahb_fsm_current_state[2], 
        ahb_fsm_current_state[1], ahb_fsm_current_state[0]}), 
        .CoreAHBLite_0_AHBmslave16_HSIZE({
        CoreAHBLite_0_AHBmslave16_HSIZE[1]}), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9]}), .masterDataInProg({
        \masterDataInProg[0] }), .ahb_fsm_current_state_ns({
        ahb_fsm_current_state_ns[0]}), .regHADDR_28(\regHADDR[30] ), 
        .regHADDR_0(\regHADDR[2] ), .regHADDR_1(\regHADDR[3] ), 
        .regHADDR_2(\regHADDR[4] ), .regHADDR_3(\regHADDR[5] ), 
        .regHADDR_4(\regHADDR[6] ), .regHADDR_5(\regHADDR[7] ), 
        .regHADDR_6(\regHADDR[8] ), .arbRegSMCurrentState_0(
        \arbRegSMCurrentState[1] ), .arbRegSMCurrentState_12(
        \arbRegSMCurrentState[13] ), .M0GATEDHADDR_2(
        \M0GATEDHADDR[31] ), .M0GATEDHADDR_0(\M0GATEDHADDR[29] ), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .m0s16AddrSel(m0s16AddrSel), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .masterRegAddrSel(masterRegAddrSel), 
        .MASTERADDRINPROG_i_a2_out(MASTERADDRINPROG_i_a2_out), 
        .HREADY_M_pre37(HREADY_M_pre37), .s16m0AddrReady(
        s16m0AddrReady), .HREADY_M_iv_i_0(HREADY_M_iv_i_0), 
        .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE), 
        .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ), .N_55_0(N_55_0), 
        .N_152(N_152), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .m21_N_10_i_0(m21_N_10_i_0), 
        .N_51_0_i_0(N_51_0_i_0), .HWDATA_1_sqmuxa(HWDATA_1_sqmuxa), 
        .N_147_mux_i_0(N_147_mux_i_0), .N_101_i_0(N_101_i_0), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .DATAOUT_1_sqmuxa(
        DATAOUT_1_sqmuxa), .N_541_i_0(N_541_i_0), .N_143_mux_i_0(
        N_143_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), .N_148_mux_i_0(
        N_148_mux_i_0), .N_126_i_0(N_126_i_0));
    COREAHBLITE_SLAVESTAGE_0s_0_0_0 slavestage_16 (.masterDataInProg({
        \masterDataInProg[0] }), .PREGATEDHADDR({\PREGATEDHADDR[28] }), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[31], 
        AHB_IF_0_BIF_1_HWDATA[30], AHB_IF_0_BIF_1_HWDATA[29], 
        AHB_IF_0_BIF_1_HWDATA[28], AHB_IF_0_BIF_1_HWDATA[27], 
        AHB_IF_0_BIF_1_HWDATA[26], AHB_IF_0_BIF_1_HWDATA[25], 
        AHB_IF_0_BIF_1_HWDATA[24], AHB_IF_0_BIF_1_HWDATA[23], 
        AHB_IF_0_BIF_1_HWDATA[22], AHB_IF_0_BIF_1_HWDATA[21], 
        AHB_IF_0_BIF_1_HWDATA[20], AHB_IF_0_BIF_1_HWDATA[19], 
        AHB_IF_0_BIF_1_HWDATA[18], AHB_IF_0_BIF_1_HWDATA[17], 
        AHB_IF_0_BIF_1_HWDATA[16], AHB_IF_0_BIF_1_HWDATA[15], 
        AHB_IF_0_BIF_1_HWDATA[14], AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .M0GATEDHADDR_0(
        \M0GATEDHADDR[29] ), .M0GATEDHADDR_2(\M0GATEDHADDR[31] ), 
        .AHB_IF_0_BIF_1_HADDR_1(AHB_IF_0_BIF_1_HADDR[3]), 
        .AHB_IF_0_BIF_1_HADDR_2(AHB_IF_0_BIF_1_HADDR[4]), 
        .AHB_IF_0_BIF_1_HADDR_3(AHB_IF_0_BIF_1_HADDR[5]), 
        .AHB_IF_0_BIF_1_HADDR_4(AHB_IF_0_BIF_1_HADDR[6]), 
        .AHB_IF_0_BIF_1_HADDR_5(AHB_IF_0_BIF_1_HADDR[7]), 
        .AHB_IF_0_BIF_1_HADDR_6(AHB_IF_0_BIF_1_HADDR[8]), 
        .AHB_IF_0_BIF_1_HADDR_28(AHB_IF_0_BIF_1_HADDR[30]), 
        .AHB_IF_0_BIF_1_HADDR_0(AHB_IF_0_BIF_1_HADDR[2]), .regHADDR_1(
        \regHADDR[3] ), .regHADDR_2(\regHADDR[4] ), .regHADDR_3(
        \regHADDR[5] ), .regHADDR_4(\regHADDR[6] ), .regHADDR_5(
        \regHADDR[7] ), .regHADDR_6(\regHADDR[8] ), .regHADDR_28(
        \regHADDR[30] ), .regHADDR_0(\regHADDR[2] ), 
        .CoreAHBLite_0_AHBmslave16_HADDR_27(
        CoreAHBLite_0_AHBmslave16_HADDR[29]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_29(
        CoreAHBLite_0_AHBmslave16_HADDR[31]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_26(
        CoreAHBLite_0_AHBmslave16_HADDR[28]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_1(
        CoreAHBLite_0_AHBmslave16_HADDR[3]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_2(
        CoreAHBLite_0_AHBmslave16_HADDR[4]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_3(
        CoreAHBLite_0_AHBmslave16_HADDR[5]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_4(
        CoreAHBLite_0_AHBmslave16_HADDR[6]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_5(
        CoreAHBLite_0_AHBmslave16_HADDR[7]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_6(
        CoreAHBLite_0_AHBmslave16_HADDR[8]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_28(
        CoreAHBLite_0_AHBmslave16_HADDR[30]), 
        .CoreAHBLite_0_AHBmslave16_HADDR_0(
        CoreAHBLite_0_AHBmslave16_HADDR[2]), .arbRegSMCurrentState_0(
        \arbRegSMCurrentState[1] ), .arbRegSMCurrentState_12(
        \arbRegSMCurrentState[13] ), .eSRAM_eNVM_access_0_HPMS_READY(
        eSRAM_eNVM_access_0_HPMS_READY), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .N_152(N_152), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .m0s16AddrSel(m0s16AddrSel), 
        .MASTERADDRINPROG_i_a2_out(MASTERADDRINPROG_i_a2_out), 
        .masterRegAddrSel(masterRegAddrSel), .s16m0AddrReady(
        s16m0AddrReady));
    
endmodule


module CoreAHBLite_Z5(
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HTRANS,
       ahb_fsm_current_state,
       CoreAHBLite_0_AHBmslave16_HSIZE,
       ahb_fsm_current_state_ns,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_pre37,
       HREADY_M_iv_i_0,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       N_55_0,
       N_152,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       m21_N_10_i_0,
       N_51_0_i_0,
       HWDATA_1_sqmuxa,
       N_147_mux_i_0,
       N_101_i_0,
       CoreAHBLite_0_AHBmslave16_HREADY,
       DATAOUT_1_sqmuxa,
       N_541_i_0,
       N_143_mux_i_0,
       N_144_mux_i_0,
       N_148_mux_i_0,
       N_126_i_0
    );
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [6:0] ahb_fsm_current_state;
output [1:1] CoreAHBLite_0_AHBmslave16_HSIZE;
output [0:0] ahb_fsm_current_state_ns;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [31:2] CoreAHBLite_0_AHBmslave16_HADDR;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  AHB_IF_0_BIF_1_HWRITE;
output HREADY_M_pre37;
output HREADY_M_iv_i_0;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;
output N_55_0;
output N_152;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output m21_N_10_i_0;
output N_51_0_i_0;
output HWDATA_1_sqmuxa;
output N_147_mux_i_0;
output N_101_i_0;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output DATAOUT_1_sqmuxa;
output N_541_i_0;
output N_143_mux_i_0;
output N_144_mux_i_0;
output N_148_mux_i_0;
output N_126_i_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s matrix4x16 (
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .AHB_IF_0_BIF_1_HTRANS({
        AHB_IF_0_BIF_1_HTRANS[1]}), .ahb_fsm_current_state({
        ahb_fsm_current_state[6], ahb_fsm_current_state[5], 
        ahb_fsm_current_state[4], ahb_fsm_current_state[3], 
        ahb_fsm_current_state[2], ahb_fsm_current_state[1], 
        ahb_fsm_current_state[0]}), .CoreAHBLite_0_AHBmslave16_HSIZE({
        CoreAHBLite_0_AHBmslave16_HSIZE[1]}), 
        .ahb_fsm_current_state_ns({ahb_fsm_current_state_ns[0]}), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[31], 
        AHB_IF_0_BIF_1_HWDATA[30], AHB_IF_0_BIF_1_HWDATA[29], 
        AHB_IF_0_BIF_1_HWDATA[28], AHB_IF_0_BIF_1_HWDATA[27], 
        AHB_IF_0_BIF_1_HWDATA[26], AHB_IF_0_BIF_1_HWDATA[25], 
        AHB_IF_0_BIF_1_HWDATA[24], AHB_IF_0_BIF_1_HWDATA[23], 
        AHB_IF_0_BIF_1_HWDATA[22], AHB_IF_0_BIF_1_HWDATA[21], 
        AHB_IF_0_BIF_1_HWDATA[20], AHB_IF_0_BIF_1_HWDATA[19], 
        AHB_IF_0_BIF_1_HWDATA[18], AHB_IF_0_BIF_1_HWDATA[17], 
        AHB_IF_0_BIF_1_HWDATA[16], AHB_IF_0_BIF_1_HWDATA[15], 
        AHB_IF_0_BIF_1_HWDATA[14], AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[31], 
        CoreAHBLite_0_AHBmslave16_HADDR[30], 
        CoreAHBLite_0_AHBmslave16_HADDR[29], 
        CoreAHBLite_0_AHBmslave16_HADDR[28], 
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9], 
        CoreAHBLite_0_AHBmslave16_HADDR[8], 
        CoreAHBLite_0_AHBmslave16_HADDR[7], 
        CoreAHBLite_0_AHBmslave16_HADDR[6], 
        CoreAHBLite_0_AHBmslave16_HADDR[5], 
        CoreAHBLite_0_AHBmslave16_HADDR[4], 
        CoreAHBLite_0_AHBmslave16_HADDR[3], 
        CoreAHBLite_0_AHBmslave16_HADDR[2]}), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), 
        .HREADY_M_pre37(HREADY_M_pre37), .HREADY_M_iv_i_0(
        HREADY_M_iv_i_0), .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE)
        , .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ), .N_55_0(N_55_0), 
        .N_152(N_152), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .m21_N_10_i_0(m21_N_10_i_0), 
        .N_51_0_i_0(N_51_0_i_0), .HWDATA_1_sqmuxa(HWDATA_1_sqmuxa), 
        .N_147_mux_i_0(N_147_mux_i_0), .N_101_i_0(N_101_i_0), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .DATAOUT_1_sqmuxa(
        DATAOUT_1_sqmuxa), .N_541_i_0(N_541_i_0), .N_143_mux_i_0(
        N_143_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), .N_148_mux_i_0(
        N_148_mux_i_0), .N_126_i_0(N_126_i_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_CCC_0_FCCC(
       eSRAM_eNVM_access_0_FIC_0_CLK,
       LOCK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output eSRAM_eNVM_access_0_FIC_0_CLK;
output LOCK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST (.A(GL0_net), .Y(eSRAM_eNVM_access_0_FIC_0_CLK));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6318C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(LOCK), 
        .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), .CLK2(VCC_net_1), 
        .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), .NGMUX1_SEL(
        GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(GND_net_1), 
        .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(VCC_net_1), 
        .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(VCC_net_1), 
        .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(VCC_net_1), 
        .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(VCC_net_1), 
        .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(VCC_net_1), 
        .PLL_POWERDOWN_N(VCC_net_1), .GPD0_ARST_N(VCC_net_1), 
        .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(VCC_net_1), .GPD3_ARST_N(
        VCC_net_1), .PRESET_N(GND_net_1), .PCLK(VCC_net_1), .PSEL(
        VCC_net_1), .PENABLE(VCC_net_1), .PWRITE(VCC_net_1), .PADDR({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .CLK0_PAD(GND_net_1), .CLK1_PAD(GND_net_1), .CLK2_PAD(
        GND_net_1), .CLK3_PAD(GND_net_1), .GL0(GL0_net), .GL1(), .GL2()
        , .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_HPMS(
       AHB_IF_0_BIF_1_HRDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       CoreAHBLite_0_AHBmslave16_HSIZE,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       HREADY_M_pre37,
       eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N,
       CoreAHBLite_0_AHBmslave16_HREADY,
       eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F,
       N_152,
       m21_N_10_i_0,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       LOCK,
       eSRAM_eNVM_access_0_FIC_0_CLK
    );
output [31:0] AHB_IF_0_BIF_1_HRDATA;
input  [31:2] CoreAHBLite_0_AHBmslave16_HADDR;
input  [1:1] CoreAHBLite_0_AHBmslave16_HSIZE;
input  [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  HREADY_M_pre37;
output eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N;
inout  CoreAHBLite_0_AHBmslave16_HREADY;
output eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F;
input  N_152;
input  m21_N_10_i_0;
input  CoreAHBLite_0_AHBmslave16_HWRITE;
input  LOCK;
input  eSRAM_eNVM_access_0_FIC_0_CLK;

    wire \CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] , VCC_net_1, GND_net_1;
    
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_4 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[5]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_25 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[26]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_28 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[29]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_21 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[22]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_5 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[6]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_15 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[16]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_18 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[19]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_11 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[12]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_20 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[21]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_27 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[28]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_9 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[10] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[10]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_2 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[3]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_30 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[31] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[31]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_7 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[8]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_29 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[30]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_23 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[24]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_10 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[11]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_17 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[18]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_3 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[4]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[0]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_26 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[27]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_1 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[2]));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_19 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[20]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_13 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[14]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_24 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[25]));
    MSS_010 #( .INIT(1438'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE400000000000010000000000F11C000001FEDFFC010842108421000001FE34001FF8000000000000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(0.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(), .CAN_TX_EBL_MGPIO4A_H2F_A(), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(), .CLK_CONFIG_APB(), .COMMS_INT(), 
        .CONFIG_PRESET_N(
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .EDAC_ERROR({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), 
        .F_FM0_RDATA({\CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] }), .F_FM0_READYOUT(
        CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_RESP(), .F_HM0_ADDR({
        nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, 
        nc19, nc20, nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, 
        nc29, nc30, nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, 
        nc39}), .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc40, nc41})
        , .F_HM0_TRANS1(), .F_HM0_WDATA({nc42, nc43, nc44, nc45, nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63, nc64, nc65, nc66, 
        nc67, nc68, nc69, nc70, nc71, nc72, nc73}), .F_HM0_WRITE(), 
        .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc74, nc75}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc76, nc77, nc78, nc79}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc80, nc81}), 
        .FAB_XDATAOUT({nc82, nc83, nc84, nc85, nc86, nc87, nc88, nc89})
        , .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc90, nc91}), 
        .FIC32_1_MASTER({nc92, nc93}), .FPGA_RESET_N(
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), 
        .H2F_INTERRUPT({nc94, nc95, nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103, nc104, nc105, nc106, nc107, nc108, nc109})
        , .H2F_NMI(), .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({nc110, nc111, nc112, nc113, nc114, nc115, 
        nc116, nc117, nc118, nc119, nc120, nc121, nc122, nc123}), 
        .PER2_FABRIC_PENABLE(), .PER2_FABRIC_PSEL(), 
        .PER2_FABRIC_PWDATA({nc124, nc125, nc126, nc127, nc128, nc129, 
        nc130, nc131, nc132, nc133, nc134, nc135, nc136, nc137, nc138, 
        nc139, nc140, nc141, nc142, nc143, nc144, nc145, nc146, nc147, 
        nc148, nc149, nc150, nc151, nc152, nc153, nc154, nc155}), 
        .PER2_FABRIC_PWRITE(), .RTC_MATCH(), .SLEEPDEEP(), 
        .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), .SMBALERT_NO1(), 
        .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc156, nc157, nc158, nc159, 
        nc160, nc161, nc162, nc163, nc164, nc165}), .TRACECLK(), 
        .TRACEDATA({nc166, nc167, nc168, nc169}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc170, nc171, nc172, 
        nc173}), .TXDF({nc174, nc175, nc176, nc177, nc178, nc179, 
        nc180, nc181}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        ), .F_AWREADY_HREADYOUT0(), .F_BID({nc182, nc183, nc184, nc185})
        , .F_BRESP_HRESP0({nc186, nc187}), .F_BVALID(), 
        .F_RDATA_HRDATA01({nc188, nc189, nc190, nc191, nc192, nc193, 
        nc194, nc195, nc196, nc197, nc198, nc199, nc200, nc201, nc202, 
        nc203, nc204, nc205, nc206, nc207, nc208, nc209, nc210, nc211, 
        nc212, nc213, nc214, nc215, nc216, nc217, nc218, nc219, nc220, 
        nc221, nc222, nc223, nc224, nc225, nc226, nc227, nc228, nc229, 
        nc230, nc231, nc232, nc233, nc234, nc235, nc236, nc237, nc238, 
        nc239, nc240, nc241, nc242, nc243, nc244, nc245, nc246, nc247, 
        nc248, nc249, nc250, nc251}), .F_RID({nc252, nc253, nc254, 
        nc255}), .F_RLAST(), .F_RRESP_HRESP1({nc256, nc257}), 
        .F_RVALID(), .F_WREADY(), .MDDR_FABRIC_PRDATA({nc258, nc259, 
        nc260, nc261, nc262, nc263, nc264, nc265, nc266, nc267, nc268, 
        nc269, nc270, nc271, nc272, nc273}), .MDDR_FABRIC_PREADY(), 
        .MDDR_FABRIC_PSLVERR(), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[31], 
        CoreAHBLite_0_AHBmslave16_HADDR[30], 
        CoreAHBLite_0_AHBmslave16_HADDR[29], 
        CoreAHBLite_0_AHBmslave16_HADDR[28], 
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], 
        CoreAHBLite_0_AHBmslave16_HADDR[11], 
        CoreAHBLite_0_AHBmslave16_HADDR[10], 
        CoreAHBLite_0_AHBmslave16_HADDR[9], 
        CoreAHBLite_0_AHBmslave16_HADDR[8], 
        CoreAHBLite_0_AHBmslave16_HADDR[7], 
        CoreAHBLite_0_AHBmslave16_HADDR[6], 
        CoreAHBLite_0_AHBmslave16_HADDR[5], 
        CoreAHBLite_0_AHBmslave16_HADDR[4], 
        CoreAHBLite_0_AHBmslave16_HADDR[3], 
        CoreAHBLite_0_AHBmslave16_HADDR[2], GND_net_1, GND_net_1}), 
        .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(GND_net_1), 
        .F_FM0_READY(CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_SEL(
        N_152), .F_FM0_SIZE({CoreAHBLite_0_AHBmslave16_HSIZE[1], 
        GND_net_1}), .F_FM0_TRANS1(m21_N_10_i_0), .F_FM0_WDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .F_FM0_WRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .F_HM0_RDATA({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_HM0_READY(VCC_net_1), .F_HM0_RESP(GND_net_1), 
        .FAB_AVALID(VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(
        VCC_net_1), .FAB_LINESTATE({VCC_net_1, VCC_net_1}), 
        .FAB_M3_RESET_N(GND_net_1), .FAB_PLL_LOCK(LOCK), .FAB_RXACTIVE(
        VCC_net_1), .FAB_RXERROR(VCC_net_1), .FAB_RXVALID(VCC_net_1), 
        .FAB_RXVALIDH(GND_net_1), .FAB_SESSEND(VCC_net_1), 
        .FAB_TXREADY(VCC_net_1), .FAB_VBUSVALID(VCC_net_1), 
        .FAB_VSTATUS({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .FAB_XDATAIN({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .GTX_CLKPF(VCC_net_1), 
        .I2C0_BCLK(VCC_net_1), .I2C0_SCL_F2H_SCP(VCC_net_1), 
        .I2C0_SDA_F2H_SCP(VCC_net_1), .I2C1_BCLK(VCC_net_1), 
        .I2C1_SCL_F2H_SCP(VCC_net_1), .I2C1_SDA_F2H_SCP(VCC_net_1), 
        .MDIF(VCC_net_1), .MGPIO0A_F2H_GPIN(VCC_net_1), 
        .MGPIO10A_F2H_GPIN(VCC_net_1), .MGPIO11A_F2H_GPIN(VCC_net_1), 
        .MGPIO11B_F2H_GPIN(VCC_net_1), .MGPIO12A_F2H_GPIN(VCC_net_1), 
        .MGPIO13A_F2H_GPIN(VCC_net_1), .MGPIO14A_F2H_GPIN(VCC_net_1), 
        .MGPIO15A_F2H_GPIN(VCC_net_1), .MGPIO16A_F2H_GPIN(VCC_net_1), 
        .MGPIO17B_F2H_GPIN(VCC_net_1), .MGPIO18B_F2H_GPIN(VCC_net_1), 
        .MGPIO19B_F2H_GPIN(VCC_net_1), .MGPIO1A_F2H_GPIN(VCC_net_1), 
        .MGPIO20B_F2H_GPIN(VCC_net_1), .MGPIO21B_F2H_GPIN(VCC_net_1), 
        .MGPIO22B_F2H_GPIN(VCC_net_1), .MGPIO24B_F2H_GPIN(VCC_net_1), 
        .MGPIO25B_F2H_GPIN(VCC_net_1), .MGPIO26B_F2H_GPIN(VCC_net_1), 
        .MGPIO27B_F2H_GPIN(VCC_net_1), .MGPIO28B_F2H_GPIN(VCC_net_1), 
        .MGPIO29B_F2H_GPIN(VCC_net_1), .MGPIO2A_F2H_GPIN(VCC_net_1), 
        .MGPIO30B_F2H_GPIN(VCC_net_1), .MGPIO31B_F2H_GPIN(VCC_net_1), 
        .MGPIO3A_F2H_GPIN(VCC_net_1), .MGPIO4A_F2H_GPIN(VCC_net_1), 
        .MGPIO5A_F2H_GPIN(VCC_net_1), .MGPIO6A_F2H_GPIN(VCC_net_1), 
        .MGPIO7A_F2H_GPIN(VCC_net_1), .MGPIO8A_F2H_GPIN(VCC_net_1), 
        .MGPIO9A_F2H_GPIN(VCC_net_1), .MMUART0_CTS_F2H_SCP(VCC_net_1), 
        .MMUART0_DCD_F2H_SCP(VCC_net_1), .MMUART0_DSR_F2H_SCP(
        VCC_net_1), .MMUART0_DTR_F2H_SCP(VCC_net_1), 
        .MMUART0_RI_F2H_SCP(VCC_net_1), .MMUART0_RTS_F2H_SCP(VCC_net_1)
        , .MMUART0_RXD_F2H_SCP(VCC_net_1), .MMUART0_SCK_F2H_SCP(
        VCC_net_1), .MMUART0_TXD_F2H_SCP(VCC_net_1), 
        .MMUART1_CTS_F2H_SCP(VCC_net_1), .MMUART1_DCD_F2H_SCP(
        VCC_net_1), .MMUART1_DSR_F2H_SCP(VCC_net_1), 
        .MMUART1_RI_F2H_SCP(VCC_net_1), .MMUART1_RTS_F2H_SCP(VCC_net_1)
        , .MMUART1_RXD_F2H_SCP(VCC_net_1), .MMUART1_SCK_F2H_SCP(
        VCC_net_1), .MMUART1_TXD_F2H_SCP(VCC_net_1), 
        .PER2_FABRIC_PRDATA({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .PER2_FABRIC_PREADY(VCC_net_1), .PER2_FABRIC_PSLVERR(GND_net_1)
        , .RCGF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .RX_CLKPF(VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), 
        .RX_EV(VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .SLEEPHOLDREQ(GND_net_1), .SMBALERT_NI0(VCC_net_1), 
        .SMBALERT_NI1(VCC_net_1), .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(
        VCC_net_1), .SPI0_CLK_IN(VCC_net_1), .SPI0_SDI_F2H_SCP(
        VCC_net_1), .SPI0_SDO_F2H_SCP(VCC_net_1), .SPI0_SS0_F2H_SCP(
        VCC_net_1), .SPI0_SS1_F2H_SCP(VCC_net_1), .SPI0_SS2_F2H_SCP(
        VCC_net_1), .SPI0_SS3_F2H_SCP(VCC_net_1), .SPI1_CLK_IN(
        VCC_net_1), .SPI1_SDI_F2H_SCP(VCC_net_1), .SPI1_SDO_F2H_SCP(
        VCC_net_1), .SPI1_SS0_F2H_SCP(VCC_net_1), .SPI1_SS1_F2H_SCP(
        VCC_net_1), .SPI1_SS2_F2H_SCP(VCC_net_1), .SPI1_SS3_F2H_SCP(
        VCC_net_1), .TX_CLKPF(VCC_net_1), .USER_MSS_GPIO_RESET_N(
        VCC_net_1), .USER_MSS_RESET_N(VCC_net_1), .XCLK_FAB(VCC_net_1), 
        .CLK_BASE(eSRAM_eNVM_access_0_FIC_0_CLK), .CLK_MDDR_APB(
        VCC_net_1), .F_ARADDR_HADDR1({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .F_ARBURST_HTRANS1({GND_net_1, GND_net_1}), .F_ARID_HSEL1({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_ARLEN_HBURST1({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLOCK_HMASTLOCK1({GND_net_1, GND_net_1}), .F_ARSIZE_HSIZE1({
        GND_net_1, GND_net_1}), .F_ARVALID_HWRITE1(GND_net_1), 
        .F_AWADDR_HADDR0({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .F_AWBURST_HTRANS0({
        GND_net_1, GND_net_1}), .F_AWID_HSEL0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLEN_HBURST0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLOCK_HMASTLOCK0({GND_net_1, 
        GND_net_1}), .F_AWSIZE_HSIZE0({GND_net_1, GND_net_1}), 
        .F_AWVALID_HWRITE0(GND_net_1), .F_BREADY(GND_net_1), 
        .F_RMW_AXI(GND_net_1), .F_RREADY(GND_net_1), .F_WDATA_HWDATA01({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .F_WID_HREADY01({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_WLAST(
        GND_net_1), .F_WSTRB({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_WVALID(GND_net_1), .FPGA_MDDR_ARESET_N(VCC_net_1), 
        .MDDR_FABRIC_PADDR({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .MDDR_FABRIC_PENABLE(VCC_net_1), .MDDR_FABRIC_PSEL(VCC_net_1), 
        .MDDR_FABRIC_PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .MDDR_FABRIC_PWRITE(
        VCC_net_1), .PRESET_N(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1}), 
        .DRAM_FIFO_WE_IN({GND_net_1, GND_net_1}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND_net_1), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), .SPI1_SCK_IN(
        GND_net_1), .SPI1_SDI_MGPIO11A_IN(GND_net_1), 
        .SPI1_SDO_MGPIO12A_IN(GND_net_1), .SPI1_SS0_MGPIO13A_IN(
        GND_net_1), .SPI1_SS1_MGPIO14A_IN(GND_net_1), 
        .SPI1_SS2_MGPIO15A_IN(GND_net_1), .SPI1_SS3_MGPIO16A_IN(
        GND_net_1), .SPI1_SS4_MGPIO17A_IN(GND_net_1), 
        .SPI1_SS5_MGPIO18A_IN(GND_net_1), .SPI1_SS6_MGPIO23A_IN(
        GND_net_1), .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(
        GND_net_1), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({nc274, nc275, 
        nc276, nc277, nc278, nc279, nc280, nc281, nc282, nc283, nc284, 
        nc285, nc286, nc287, nc288, nc289}), .DRAM_BA({nc290, nc291, 
        nc292}), .DRAM_CASN(), .DRAM_CKE(), .DRAM_CLK(), .DRAM_CSN(), 
        .DRAM_DM_RDQS_OUT({nc293, nc294, nc295}), .DRAM_DQ_OUT({nc296, 
        nc297, nc298, nc299, nc300, nc301, nc302, nc303, nc304, nc305, 
        nc306, nc307, nc308, nc309, nc310, nc311, nc312, nc313}), 
        .DRAM_DQS_OUT({nc314, nc315, nc316}), .DRAM_FIFO_WE_OUT({nc317, 
        nc318}), .DRAM_ODT(), .DRAM_RASN(), .DRAM_RSTN(), .DRAM_WEN(), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc319, nc320, 
        nc321}), .DRAM_DQ_OE({nc322, nc323, nc324, nc325, nc326, nc327, 
        nc328, nc329, nc330, nc331, nc332, nc333, nc334, nc335, nc336, 
        nc337, nc338, nc339}), .DRAM_DQS_OE({nc340, nc341, nc342}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI1_SCK_OE(), 
        .SPI1_SDI_MGPIO11A_OE(), .SPI1_SDO_MGPIO12A_OE(), 
        .SPI1_SS0_MGPIO13A_OE(), .SPI1_SS1_MGPIO14A_OE(), 
        .SPI1_SS2_MGPIO15A_OE(), .SPI1_SS3_MGPIO16A_OE(), 
        .SPI1_SS4_MGPIO17A_OE(), .SPI1_SS5_MGPIO18A_OE(), 
        .SPI1_SS6_MGPIO23A_OE(), .SPI1_SS7_MGPIO24A_OE(), 
        .USBC_XCLK_OE());
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_16 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[17]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_22 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[23]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_14 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[15]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_12 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] ), .B(HREADY_M_pre37), 
        .Y(AHB_IF_0_BIF_1_HRDATA[13]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_8 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[9]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_0 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[1]));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNI2TT05_6 (.A(
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] ), .B(HREADY_M_pre37), .Y(
        AHB_IF_0_BIF_1_HRDATA[7]));
    
endmodule


module eSRAM_eNVM_access(
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HTRANS,
       ahb_fsm_current_state,
       ahb_fsm_current_state_ns,
       AHB_IF_0_BIF_1_HWDATA,
       AHB_IF_0_BIF_1_HRDATA,
       DEVRST_N,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_access_0_HPMS_READY,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_iv_i_0,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       N_55_0,
       N_51_0_i_0,
       HWDATA_1_sqmuxa,
       N_147_mux_i_0,
       N_101_i_0,
       DATAOUT_1_sqmuxa,
       N_541_i_0,
       N_143_mux_i_0,
       N_144_mux_i_0,
       N_148_mux_i_0,
       N_126_i_0
    );
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [6:0] ahb_fsm_current_state;
output [0:0] ahb_fsm_current_state_ns;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] AHB_IF_0_BIF_1_HRDATA;
input  DEVRST_N;
output eSRAM_eNVM_access_0_FIC_0_CLK;
output eSRAM_eNVM_access_0_HPMS_READY;
input  AHB_IF_0_BIF_1_HWRITE;
output HREADY_M_iv_i_0;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;
output N_55_0;
output N_51_0_i_0;
output HWDATA_1_sqmuxa;
output N_147_mux_i_0;
output N_101_i_0;
output DATAOUT_1_sqmuxa;
output N_541_i_0;
output N_143_mux_i_0;
output N_144_mux_i_0;
output N_148_mux_i_0;
output N_126_i_0;

    wire SYSRESET_POR_net_1, LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        \CoreAHBLite_0_AHBmslave16_HSIZE[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[28] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[29] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[30] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[31] , HREADY_M_pre37, N_152, 
        CoreAHBLite_0_AHBmslave16_HWRITE, m21_N_10_i_0, 
        CoreAHBLite_0_AHBmslave16_HREADY, 
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F, 
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N, GND_net_1, 
        VCC_net_1;
    
    eSRAM_eNVM_access_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z6 CORERESETP_0 (.eSRAM_eNVM_access_0_HPMS_READY(
        eSRAM_eNVM_access_0_HPMS_READY), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .SYSRESET_POR(SYSRESET_POR_net_1), 
        .eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F(
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F), 
        .eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N(
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N));
    CoreAHBLite_Z5 CoreAHBLite_0 (.AHB_IF_0_BIF_1_HADDR({
        AHB_IF_0_BIF_1_HADDR[31], AHB_IF_0_BIF_1_HADDR[30], 
        AHB_IF_0_BIF_1_HADDR[29], AHB_IF_0_BIF_1_HADDR[28], 
        AHB_IF_0_BIF_1_HADDR[27], AHB_IF_0_BIF_1_HADDR[26], 
        AHB_IF_0_BIF_1_HADDR[25], AHB_IF_0_BIF_1_HADDR[24], 
        AHB_IF_0_BIF_1_HADDR[23], AHB_IF_0_BIF_1_HADDR[22], 
        AHB_IF_0_BIF_1_HADDR[21], AHB_IF_0_BIF_1_HADDR[20], 
        AHB_IF_0_BIF_1_HADDR[19], AHB_IF_0_BIF_1_HADDR[18], 
        AHB_IF_0_BIF_1_HADDR[17], AHB_IF_0_BIF_1_HADDR[16], 
        AHB_IF_0_BIF_1_HADDR[15], AHB_IF_0_BIF_1_HADDR[14], 
        AHB_IF_0_BIF_1_HADDR[13], AHB_IF_0_BIF_1_HADDR[12], 
        AHB_IF_0_BIF_1_HADDR[11], AHB_IF_0_BIF_1_HADDR[10], 
        AHB_IF_0_BIF_1_HADDR[9], AHB_IF_0_BIF_1_HADDR[8], 
        AHB_IF_0_BIF_1_HADDR[7], AHB_IF_0_BIF_1_HADDR[6], 
        AHB_IF_0_BIF_1_HADDR[5], AHB_IF_0_BIF_1_HADDR[4], 
        AHB_IF_0_BIF_1_HADDR[3], AHB_IF_0_BIF_1_HADDR[2]}), 
        .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .ahb_fsm_current_state({ahb_fsm_current_state[6], 
        ahb_fsm_current_state[5], ahb_fsm_current_state[4], 
        ahb_fsm_current_state[3], ahb_fsm_current_state[2], 
        ahb_fsm_current_state[1], ahb_fsm_current_state[0]}), 
        .CoreAHBLite_0_AHBmslave16_HSIZE({
        \CoreAHBLite_0_AHBmslave16_HSIZE[1] }), 
        .ahb_fsm_current_state_ns({ahb_fsm_current_state_ns[0]}), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[31], 
        AHB_IF_0_BIF_1_HWDATA[30], AHB_IF_0_BIF_1_HWDATA[29], 
        AHB_IF_0_BIF_1_HWDATA[28], AHB_IF_0_BIF_1_HWDATA[27], 
        AHB_IF_0_BIF_1_HWDATA[26], AHB_IF_0_BIF_1_HWDATA[25], 
        AHB_IF_0_BIF_1_HWDATA[24], AHB_IF_0_BIF_1_HWDATA[23], 
        AHB_IF_0_BIF_1_HWDATA[22], AHB_IF_0_BIF_1_HWDATA[21], 
        AHB_IF_0_BIF_1_HWDATA[20], AHB_IF_0_BIF_1_HWDATA[19], 
        AHB_IF_0_BIF_1_HWDATA[18], AHB_IF_0_BIF_1_HWDATA[17], 
        AHB_IF_0_BIF_1_HWDATA[16], AHB_IF_0_BIF_1_HWDATA[15], 
        AHB_IF_0_BIF_1_HWDATA[14], AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[31] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[30] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[29] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[28] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] }), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), 
        .HREADY_M_pre37(HREADY_M_pre37), .HREADY_M_iv_i_0(
        HREADY_M_iv_i_0), .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE)
        , .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ), .N_55_0(N_55_0), 
        .N_152(N_152), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .m21_N_10_i_0(m21_N_10_i_0), 
        .N_51_0_i_0(N_51_0_i_0), .HWDATA_1_sqmuxa(HWDATA_1_sqmuxa), 
        .N_147_mux_i_0(N_147_mux_i_0), .N_101_i_0(N_101_i_0), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .DATAOUT_1_sqmuxa(
        DATAOUT_1_sqmuxa), .N_541_i_0(N_541_i_0), .N_143_mux_i_0(
        N_143_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), .N_148_mux_i_0(
        N_148_mux_i_0), .N_126_i_0(N_126_i_0));
    VCC VCC (.Y(VCC_net_1));
    eSRAM_eNVM_access_CCC_0_FCCC CCC_0 (.eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .LOCK(LOCK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    GND GND (.Y(GND_net_1));
    eSRAM_eNVM_access_HPMS eSRAM_eNVM_access_HPMS_0 (
        .AHB_IF_0_BIF_1_HRDATA({AHB_IF_0_BIF_1_HRDATA[31], 
        AHB_IF_0_BIF_1_HRDATA[30], AHB_IF_0_BIF_1_HRDATA[29], 
        AHB_IF_0_BIF_1_HRDATA[28], AHB_IF_0_BIF_1_HRDATA[27], 
        AHB_IF_0_BIF_1_HRDATA[26], AHB_IF_0_BIF_1_HRDATA[25], 
        AHB_IF_0_BIF_1_HRDATA[24], AHB_IF_0_BIF_1_HRDATA[23], 
        AHB_IF_0_BIF_1_HRDATA[22], AHB_IF_0_BIF_1_HRDATA[21], 
        AHB_IF_0_BIF_1_HRDATA[20], AHB_IF_0_BIF_1_HRDATA[19], 
        AHB_IF_0_BIF_1_HRDATA[18], AHB_IF_0_BIF_1_HRDATA[17], 
        AHB_IF_0_BIF_1_HRDATA[16], AHB_IF_0_BIF_1_HRDATA[15], 
        AHB_IF_0_BIF_1_HRDATA[14], AHB_IF_0_BIF_1_HRDATA[13], 
        AHB_IF_0_BIF_1_HRDATA[12], AHB_IF_0_BIF_1_HRDATA[11], 
        AHB_IF_0_BIF_1_HRDATA[10], AHB_IF_0_BIF_1_HRDATA[9], 
        AHB_IF_0_BIF_1_HRDATA[8], AHB_IF_0_BIF_1_HRDATA[7], 
        AHB_IF_0_BIF_1_HRDATA[6], AHB_IF_0_BIF_1_HRDATA[5], 
        AHB_IF_0_BIF_1_HRDATA[4], AHB_IF_0_BIF_1_HRDATA[3], 
        AHB_IF_0_BIF_1_HRDATA[2], AHB_IF_0_BIF_1_HRDATA[1], 
        AHB_IF_0_BIF_1_HRDATA[0]}), .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[31] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[30] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[29] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[28] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[11] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[10] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[9] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[8] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[7] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[6] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[5] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[4] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[3] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[2] }), 
        .CoreAHBLite_0_AHBmslave16_HSIZE({
        \CoreAHBLite_0_AHBmslave16_HSIZE[1] }), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), .HREADY_M_pre37(
        HREADY_M_pre37), 
        .eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N(
        eSRAM_eNVM_access_HPMS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), 
        .eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F(
        eSRAM_eNVM_access_HPMS_TMP_0_MSS_RESET_N_M2F), .N_152(N_152), 
        .m21_N_10_i_0(m21_N_10_i_0), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .LOCK(LOCK), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(SYSRESET_POR_net_1), 
        .DEVRST_N(DEVRST_N));
    
endmodule


module eSRAM_eNVM_RW(
       eSRAM_eNVM_RW_0_ram_waddr,
       eSRAM_eNVM_RW_0_ram_wdata,
       AHB_IF_0_DATAOUT,
       eSRAM_eNVM_RW_0_ADDR,
       eSRAM_eNVM_RW_0_DATAOUT,
       eSRAM_eNVM_access_0_HPMS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       eSRAM_eNVM_RW_0_ram_wen,
       start_envm_c,
       start_esram_c,
       AHB_IF_0_VALID,
       AHB_IF_0_AHB_BUSY
    );
output [4:0] eSRAM_eNVM_RW_0_ram_waddr;
output [31:0] eSRAM_eNVM_RW_0_ram_wdata;
input  [31:0] AHB_IF_0_DATAOUT;
output [31:2] eSRAM_eNVM_RW_0_ADDR;
output [31:0] eSRAM_eNVM_RW_0_DATAOUT;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output eSRAM_eNVM_RW_0_WRITE;
output eSRAM_eNVM_RW_0_READ;
output eSRAM_eNVM_RW_0_ram_wen;
input  start_envm_c;
input  start_esram_c;
input  AHB_IF_0_VALID;
input  AHB_IF_0_AHB_BUSY;

    wire VCC_net_1, N_248_i_0, ram_waddre, GND_net_1, N_251_i_0, 
        N_243_i_0, N_246_i_0, \data_cnt[3]_net_1 , N_199_i_0, 
        data_cnte, \data_cnt[4]_net_1 , N_200_i_0, N_9_i_0, 
        \data_cnt[0]_net_1 , N_315, \data_cnt[1]_net_1 , N_197_i_0, 
        \data_cnt[2]_net_1 , N_198_i_0, N_87_i_0, N_792_i_0, N_392_i_0, 
        N_378_i_0, N_390_i_0, envm_release_reg_net_1, 
        \current_state[9]_net_1 , un40_0_0_0_net_1, N_244, N_387_i_0, 
        \current_state[6]_net_1 , N_330_i_0, \current_state[7]_net_1 , 
        \current_state_ns[7] , \current_state[8]_net_1 , 
        \current_state_ns[8] , \current_state_ns[9] , \data_13[31] , 
        \current_state_ns[10] , \current_state[11]_net_1 , N_336_i_0, 
        \current_state[12]_net_1 , \current_state_ns[12] , 
        \current_state[13]_net_1 , N_60, \current_state[14]_net_1 , 
        N_341_i_0, \current_state[15]_net_1 , \current_state_ns[15] , 
        \current_state[16]_net_1 , \current_state_ns[16] , 
        \current_state[0]_net_1 , \current_state_ns[0] , 
        \current_state[1]_net_1 , N_50, \current_state[2]_net_1 , 
        \current_state_ns[2] , \current_state[3]_net_1 , 
        \current_state_ns[3] , \current_state[4]_net_1 , N_83, 
        \current_state[5]_net_1 , \current_state_ns[5] , 
        start_envm_reg_net_1, start_esram_reg_net_1, 
        start_envm_reg1_net_1, start_esram_reg1_net_1, 
        start_envm_reg2_net_1, start_esram_reg2_net_1, 
        \addr_temp_lm[2] , N_35_i_0, \addr_temp_lm[3] , 
        \addr_temp_lm[4] , \addr_temp_lm[5] , \addr_temp_lm[6] , 
        \addr_temp_lm[7] , \addr_temp_lm[8] , \addr_temp_lm[9] , 
        \addr_temp_lm[10] , \addr_temp_lm[11] , \addr_temp_lm[12] , 
        \addr_temp_lm[13] , \addr_temp_lm[14] , \addr_temp_lm[15] , 
        \addr_temp_lm[16] , \addr_temp_lm[17] , \addr_temp_lm[18] , 
        \addr_temp_lm[19] , \addr_temp_lm[20] , \addr_temp_lm[21] , 
        \addr_temp_lm[22] , \addr_temp_lm[23] , \addr_temp_lm[24] , 
        \addr_temp_lm[25] , \addr_temp_lm[26] , \addr_temp_lm[27] , 
        \addr_temp_lm[28] , \addr_temp_lm[29] , \addr_temp_lm[30] , 
        \addr_temp_lm[31] , \data_s[0] , N_18_i_0, \data_s[1] , 
        \data_s[2] , \data_s[3] , \data_s[4] , \data_s[5] , 
        \data_s[6] , \data_s[7] , \data_s[8] , \data_s[9] , 
        \data_s[10] , \data_s[11] , \data_s[12] , \data_s[13] , 
        \data_s[14] , \data_s[15] , \data_s[16] , \data_s[17] , 
        \data_s[18] , \data_s[19] , \data_s[20] , \data_s[21] , 
        \data_s[22] , \data_s[23] , \data_s[24] , \data_s[25] , 
        \data_s[26] , \data_s[27] , \data_s[28] , \data_s[29] , 
        \data_s[30] , \data_s[31]_net_1 , data_cry_cy, 
        \data_cry_cy_Y[0] , un1_READ6_3_0_0_1_1, N_187, N_201, N_267, 
        \data_cry[0]_net_1 , N_75, \data_cry[1]_net_1 , 
        \data_cry[2]_net_1 , \data_cry[3]_net_1 , \data_cry[4]_net_1 , 
        N_220, \data_cry[5]_net_1 , \data_cry[6]_net_1 , 
        \data_cry[7]_net_1 , N_46_i, \data_cry[8]_net_1 , 
        \data_cry[9]_net_1 , \data_cry[10]_net_1 , 
        \data_cry[11]_net_1 , \data_cry[12]_net_1 , 
        \data_cry[13]_net_1 , \data_cry[14]_net_1 , 
        \data_cry[15]_net_1 , \data_cry[16]_net_1 , 
        \data_cry[17]_net_1 , \data_cry[18]_net_1 , 
        \data_cry[19]_net_1 , \data_cry[20]_net_1 , 
        \data_cry[21]_net_1 , \data_cry[22]_net_1 , 
        \data_cry[23]_net_1 , \data_cry[24]_net_1 , 
        \data_cry[25]_net_1 , \data_cry[26]_net_1 , 
        \data_cry[27]_net_1 , \data_cry[28]_net_1 , 
        \data_cry[29]_net_1 , \data_cry[30]_net_1 , addr_temp_s_15_FCO, 
        \addr_temp_cry[3]_net_1 , \addr_temp_s[3] , 
        \addr_temp_cry[4]_net_1 , \addr_temp_s[4] , 
        \addr_temp_cry[5]_net_1 , \addr_temp_s[5] , 
        \addr_temp_cry[6]_net_1 , \addr_temp_s[6] , 
        \addr_temp_cry[7]_net_1 , \addr_temp_s[7] , 
        \addr_temp_cry[8]_net_1 , \addr_temp_s[8] , 
        \addr_temp_cry[9]_net_1 , \addr_temp_s[9] , 
        \addr_temp_cry[10]_net_1 , \addr_temp_s[10] , 
        \addr_temp_cry[11]_net_1 , \addr_temp_s[11] , 
        \addr_temp_cry[12]_net_1 , \addr_temp_s[12] , 
        \addr_temp_cry[13]_net_1 , \addr_temp_s[13] , 
        \addr_temp_cry[14]_net_1 , \addr_temp_s[14] , 
        \addr_temp_cry[15]_net_1 , \addr_temp_s[15] , 
        \addr_temp_cry[16]_net_1 , \addr_temp_s[16] , 
        \addr_temp_cry[17]_net_1 , \addr_temp_s[17] , 
        \addr_temp_cry[18]_net_1 , \addr_temp_s[18] , 
        \addr_temp_cry[19]_net_1 , \addr_temp_s[19] , 
        \addr_temp_cry[20]_net_1 , \addr_temp_s[20] , 
        \addr_temp_cry[21]_net_1 , \addr_temp_s[21] , 
        \addr_temp_cry[22]_net_1 , \addr_temp_s[22] , 
        \addr_temp_cry[23]_net_1 , \addr_temp_s[23] , 
        \addr_temp_cry[24]_net_1 , \addr_temp_s[24] , 
        \addr_temp_cry[25]_net_1 , \addr_temp_s[25] , 
        \addr_temp_cry[26]_net_1 , \addr_temp_s[26] , 
        \addr_temp_cry[27]_net_1 , \addr_temp_s[27] , 
        \addr_temp_cry[28]_net_1 , \addr_temp_s[28] , 
        \addr_temp_cry[29]_net_1 , \addr_temp_s[29] , 
        \addr_temp_s[31]_net_1 , \addr_temp_cry[30]_net_1 , 
        \addr_temp_s[30] , N_214, N_181, N_364, N_175, 
        \addr_temp_cnst_i_a2_0_0_0_1[8]_net_1 , 
        \addr_temp_cnst_i_a2_0_0_0[8]_net_1 , N_272, N_222, N_383, 
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1, esram_select_net_1, 
        N_340, N_202, N_194, N_203, N_213, N_238, N_342, N_218, N_190, 
        N_352, ram_wdata_0_sqmuxa_i_0_a3_4_net_1, 
        ram_wdata_0_sqmuxa_i_0_a3_3_net_1, 
        un1_current_state_16_0_0_i_0_0_a3_2_2, 
        un1_addr_temp_8_sqmuxa_5_0_1_a3_0, 
        un1_current_state_16_0_0_i_0_0_a3_1_1, 
        un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1, 
        ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1, N_253, N_356, N_308, 
        N_365, N_373, N_374, N_575, N_302, N_217, N_376, N_230, 
        un1_current_state_20_i_0_0_a3_1_net_1, 
        un1_current_state_16_0_0_i_0_0_a3_2_3, 
        un1_current_state_16_0_0_i_0_0_a3_0, 
        ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1, 
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1, N_333, N_331, N_283, 
        N_369_i_i_0_a3_0_1, N_188, N_306, N_233, N_349, N_378, 
        N_369_i_i_0_a3_0, ram_wdata_0_sqmuxa_i_0_1_net_1, 
        un1_current_state_16_0_0_i_0_0_0, 
        un1_current_state_19_i_0_0_0_net_1, 
        un1_current_state_20_i_0_0_a3_2_net_1, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2, 
        un1_current_state_19_i_0_0_a3_0_2_net_1, 
        un1_READ_1_sqmuxa_2_i_0_0_0_net_1, N_277, N_303, N_307, N_301, 
        \addr_temp_cnst_i_a2_0_i[6]_net_1 , N_219, N_355, N_310, 
        N_268_2, un1_current_state_20_i_0_0_0_net_1, N_369_i_i_0_0, 
        N_282, N_370, N_268, un1_current_state_16_0_0_i_0_0_2, N_269, 
        ram_wdata_0_sqmuxa_i_0_o3_RNI3424_net_1, 
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1, N_82;
    
    CFG2 #( .INIT(4'h7) )  ram_waddr_n2_0_o2 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[0]), .B(eSRAM_eNVM_RW_0_ram_waddr[1])
        , .Y(N_203));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[24]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[24]), .FCI(\data_cry[23]_net_1 ), .S(
        \data_s[24] ), .Y(), .FCO(\data_cry[24]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \current_state_ns_0_0[9]  (.A(
        \current_state[8]_net_1 ), .B(\current_state[9]_net_1 ), .C(
        AHB_IF_0_DATAOUT[0]), .D(N_190), .Y(\current_state_ns[9] ));
    CFG4 #( .INIT(16'hCA0A) )  \addr_temp_lm_0[4]  (.A(
        \addr_temp_s[4] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_201), .Y(
        \addr_temp_lm[4] ));
    CFG4 #( .INIT(16'h7F70) )  un1_current_state_19_i_0_0_o2 (.A(
        AHB_IF_0_DATAOUT[2]), .B(AHB_IF_0_DATAOUT[1]), .C(
        \current_state[4]_net_1 ), .D(N_181), .Y(N_188));
    CFG4 #( .INIT(16'hEAC0) )  \current_state_ns_0_0[7]  (.A(
        \current_state[6]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_370), .Y(\current_state_ns[7] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[26]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[26]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[25]_net_1 ), .S(\addr_temp_s[26] ), .Y(), .FCO(
        \addr_temp_cry[26]_net_1 ));
    CFG4 #( .INIT(16'h0007) )  ram_wdata_0_sqmuxa_i_0_a3_RNIFTN31 (.A(
        ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1), .B(N_364), .C(N_282), .D(
        ram_wdata_0_sqmuxa_i_0_1_net_1), .Y(N_87_i_0));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[12]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[12]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[11]_net_1 ), .S(\addr_temp_s[12] ), .Y(), .FCO(
        \addr_temp_cry[12]_net_1 ));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[16]  (.A(
        \addr_temp_s[16] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_220), .Y(
        \addr_temp_lm[16] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[20]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[20]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[19]_net_1 ), .S(\addr_temp_s[20] ), .Y(), .FCO(
        \addr_temp_cry[20]_net_1 ));
    CFG3 #( .INIT(8'h20) )  un1_READ_1_sqmuxa_2_i_0_a3_0 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[1]), .B(eSRAM_eNVM_RW_0_ram_waddr[0])
        , .C(un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1), .Y(N_272));
    SLE \data[5]  (.D(\data_s[5] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[5]));
    SLE \addr_temp[25]  (.D(\addr_temp_lm[25] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[25]));
    SLE \ram_wdata[9]  (.D(AHB_IF_0_DATAOUT[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[9]));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[4]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[4]), 
        .C(N_233), .D(N_383), .Y(N_251_i_0));
    CFG4 #( .INIT(16'h0800) )  \current_state_RNIQCEP1[1]  (.A(N_364), 
        .B(N_349), .C(\current_state[1]_net_1 ), .D(N_175), .Y(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2));
    CFG4 #( .INIT(16'h0B00) )  \current_state_ns_0_0_a3_0[0]  (.A(
        start_envm_reg1_net_1), .B(start_envm_reg2_net_1), .C(
        esram_select_net_1), .D(\current_state[0]_net_1 ), .Y(N_333));
    CFG4 #( .INIT(16'h88F0) )  \addr_temp_lm_0[10]  (.A(
        eSRAM_eNVM_access_0_HPMS_READY), .B(\current_state[9]_net_1 ), 
        .C(\addr_temp_s[10] ), .D(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .Y(
        \addr_temp_lm[10] ));
    SLE \addr_temp[16]  (.D(\addr_temp_lm[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[16]));
    CFG2 #( .INIT(4'h7) )  envm_release_reg_RNIPKA7 (.A(
        \current_state[16]_net_1 ), .B(envm_release_reg_net_1), .Y(
        N_175));
    ARI1 #( .INIT(20'h4E200) )  \data_cry[0]  (.A(VCC_net_1), .B(N_75), 
        .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[0]), .FCI(
        data_cry_cy), .S(\data_s[0] ), .Y(), .FCO(\data_cry[0]_net_1 ));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[29]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[29]), .FCI(\data_cry[28]_net_1 ), .S(
        \data_s[29] ), .Y(), .FCO(\data_cry[29]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[28]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[28]), .D(
        GND_net_1), .FCI(\data_cry[27]_net_1 ), .S(\data_s[28] ), .Y(), 
        .FCO(\data_cry[28]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \addr_temp_lm_0[3]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[3] ), .C(N_82), .Y(\addr_temp_lm[3] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[3]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[3]), .C(GND_net_1), .D(GND_net_1), .FCI(
        addr_temp_s_15_FCO), .S(\addr_temp_s[3] ), .Y(), .FCO(
        \addr_temp_cry[3]_net_1 ));
    SLE \current_state[2]  (.D(\current_state_ns[2] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[2]_net_1 ));
    CFG4 #( .INIT(16'h00DF) )  WRITE_RNO (.A(\data_cnt[4]_net_1 ), .B(
        N_214), .C(un1_current_state_16_0_0_i_0_0_a3_2_3), .D(
        un1_current_state_16_0_0_i_0_0_2), .Y(N_792_i_0));
    ARI1 #( .INIT(20'h40002) )  \data_cry_cy[0]  (.A(
        un1_READ6_3_0_0_1_1), .B(N_187), .C(N_201), .D(N_267), .FCI(
        VCC_net_1), .S(), .Y(\data_cry_cy_Y[0] ), .FCO(data_cry_cy));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[15]  (.A(
        \addr_temp_s[15] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_220), .Y(
        \addr_temp_lm[15] ));
    SLE \ram_wdata[23]  (.D(AHB_IF_0_DATAOUT[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[23]));
    CFG3 #( .INIT(8'hA8) )  \addr_temp_cnst_i_a2_0_i_a3[5]  (.A(
        eSRAM_eNVM_access_0_HPMS_READY), .B(N_201), .C(
        \current_state[1]_net_1 ), .Y(N_301));
    SLE \data[9]  (.D(\data_s[9] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[9]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[27]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[27]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[26]_net_1 ), .S(\addr_temp_s[27] ), .Y(), .FCO(
        \addr_temp_cry[27]_net_1 ));
    SLE \addr_temp[26]  (.D(\addr_temp_lm[26] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[26]));
    CFG3 #( .INIT(8'h57) )  \data_cnst_i_i_0[0]  (.A(N_220), .B(
        \current_state[4]_net_1 ), .C(N_181), .Y(N_75));
    SLE \data[10]  (.D(\data_s[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[10]));
    SLE \addr_temp[3]  (.D(\addr_temp_lm[3] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[3]));
    CFG3 #( .INIT(8'h20) )  un1_current_state_20_i_0_0_a3_0 (.A(N_378), 
        .B(\current_state[14]_net_1 ), .C(N_352), .Y(N_310));
    SLE \current_state[6]  (.D(N_330_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[6]_net_1 ));
    SLE \addr_temp[13]  (.D(\addr_temp_lm[13] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[13]));
    SLE \data_cnt[2]  (.D(N_198_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[2]_net_1 ));
    CFG2 #( .INIT(4'h1) )  un1_READ_1_sqmuxa_2_i_0_a3_1_0 (.A(
        \current_state[12]_net_1 ), .B(AHB_IF_0_VALID), .Y(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1));
    SLE \ram_wdata[17]  (.D(AHB_IF_0_DATAOUT[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[17]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[24]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[24]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[23]_net_1 ), .S(\addr_temp_s[24] ), .Y(), .FCO(
        \addr_temp_cry[24]_net_1 ));
    SLE \data[13]  (.D(\data_s[13] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[13]));
    SLE \ram_wdata[8]  (.D(AHB_IF_0_DATAOUT[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[8]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[12]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[12] ), .Y(\addr_temp_lm[12] ));
    SLE \addr_temp[6]  (.D(\addr_temp_lm[6] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[6]));
    SLE start_envm_reg (.D(start_envm_c), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg_net_1));
    SLE \addr_temp[23]  (.D(\addr_temp_lm[23] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[23]));
    CFG3 #( .INIT(8'h01) )  \current_state_RNI7BUF[13]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        \current_state[9]_net_1 ), .Y(N_364));
    CFG4 #( .INIT(16'hCE0A) )  \current_state_ns_i_i_0[4]  (.A(
        \current_state[3]_net_1 ), .B(\current_state[4]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_253), .Y(N_83));
    CFG4 #( .INIT(16'hEE2E) )  \addr_temp_lm_0[30]  (.A(
        \addr_temp_s[30] ), .B(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .C(
        eSRAM_eNVM_access_0_HPMS_READY), .D(N_374), .Y(
        \addr_temp_lm[30] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[16]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[16]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[15]_net_1 ), .S(\addr_temp_s[16] ), .Y(), .FCO(
        \addr_temp_cry[16]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_cnst_i_a2_0_i_a3_0[7]  (.A(N_238)
        , .B(\current_state[5]_net_1 ), .Y(N_308));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[10]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[10]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[9]_net_1 ), .S(\addr_temp_s[10] ), .Y(), .FCO(
        \addr_temp_cry[10]_net_1 ));
    SLE \addr_temp[7]  (.D(\addr_temp_lm[7] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[7]));
    CFG4 #( .INIT(16'h0004) )  \current_state_ns_i_0_0_a2_RNISPHK[6]  
        (.A(\data_13[31] ), .B(N_340), .C(\current_state[11]_net_1 ), 
        .D(\current_state[7]_net_1 ), .Y(N_349));
    CFG4 #( .INIT(16'h0010) )  un1_READ_1_sqmuxa_2_i_0_a3_0_RNITTFR6 (
        .A(ram_wdata_0_sqmuxa_i_0_o3_RNI3424_net_1), .B(N_269), .C(
        eSRAM_eNVM_access_0_HPMS_READY), .D(N_268), .Y(N_35_i_0));
    CFG3 #( .INIT(8'h40) )  ram_wdata_0_sqmuxa_i_0_a3_0 (.A(N_218), .B(
        ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1), .C(N_340), .Y(N_283));
    SLE \data[4]  (.D(\data_s[4] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[4]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_cnst_i_a2_0_0_a3_0[8]  (.A(N_201)
        , .B(N_352), .Y(N_306));
    SLE start_esram_reg1 (.D(start_esram_reg_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg1_net_1));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[17]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[17]), .FCI(\data_cry[16]_net_1 ), .S(
        \data_s[17] ), .Y(), .FCO(\data_cry[17]_net_1 ));
    SLE \data[11]  (.D(\data_s[11] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[11]));
    CFG4 #( .INIT(16'h0002) )  envm_release_reg_RNIPUH21 (.A(
        \current_state[16]_net_1 ), .B(envm_release_reg_net_1), .C(
        \current_state[4]_net_1 ), .D(\current_state[2]_net_1 ), .Y(
        N_373));
    CFG2 #( .INIT(4'hB) )  \current_state_ns_i_i_0_o2[13]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[12]_net_1 ), .Y(N_202));
    CFG2 #( .INIT(4'hB) )  un1_addr_temp_8_sqmuxa_5_0_1_o3 (.A(
        AHB_IF_0_AHB_BUSY), .B(eSRAM_eNVM_access_0_HPMS_READY), .Y(
        N_238));
    SLE \ram_waddr[4]  (.D(N_251_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[4]));
    CFG2 #( .INIT(4'h4) )  ram_wdata_0_sqmuxa_i_0_o2_RNIDIA2 (.A(N_190)
        , .B(N_218), .Y(N_244));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[2]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[2]), 
        .C(N_203), .D(N_383), .Y(N_246_i_0));
    ARI1 #( .INIT(20'h4B8BB) )  \data_cry[9]  (.A(N_220), .B(
        eSRAM_eNVM_RW_0_DATAOUT[9]), .C(\data_cry_cy_Y[0] ), .D(
        \data_13[31] ), .FCI(\data_cry[8]_net_1 ), .S(\data_s[9] ), .Y(
        ), .FCO(\data_cry[9]_net_1 ));
    GND GND (.Y(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[17]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[17]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[16]_net_1 ), .S(\addr_temp_s[17] ), .Y(), .FCO(
        \addr_temp_cry[17]_net_1 ));
    SLE \ram_wdata[4]  (.D(AHB_IF_0_DATAOUT[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[4]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[7]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[7]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[6]_net_1 ), .S(\addr_temp_s[7] ), .Y(), .FCO(
        \addr_temp_cry[7]_net_1 ));
    CFG4 #( .INIT(16'hFF7F) )  \current_state_RNIKDK11[4]  (.A(
        AHB_IF_0_DATAOUT[1]), .B(AHB_IF_0_DATAOUT[2]), .C(
        \current_state[4]_net_1 ), .D(AHB_IF_0_DATAOUT[0]), .Y(N_220));
    CFG4 #( .INIT(16'hF2FA) )  \current_state_ns_0_0[0]  (.A(
        \current_state[16]_net_1 ), .B(envm_release_reg_net_1), .C(
        N_333), .D(AHB_IF_0_AHB_BUSY), .Y(\current_state_ns[0] ));
    CFG4 #( .INIT(16'h7333) )  \addr_temp_cnst_i_a2_0_0_0[8]  (.A(
        \current_state[7]_net_1 ), .B(eSRAM_eNVM_access_0_HPMS_READY), 
        .C(N_175), .D(\addr_temp_cnst_i_a2_0_0_0_1[8]_net_1 ), .Y(
        \addr_temp_cnst_i_a2_0_0_0[8]_net_1 ));
    CFG3 #( .INIT(8'h41) )  \data_cnt_RNO[2]  (.A(N_575), .B(
        \data_cnt[2]_net_1 ), .C(N_194), .Y(N_198_i_0));
    SLE \data_cnt[4]  (.D(N_200_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[4]_net_1 ));
    SLE \current_state[5]  (.D(\current_state_ns[5] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[14]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[14]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[13]_net_1 ), .S(\addr_temp_s[14] ), .Y(), .FCO(
        \addr_temp_cry[14]_net_1 ));
    CFG4 #( .INIT(16'h0311) )  \addr_temp_cnst_i_a2_0_0_0_1[8]  (.A(
        \current_state[8]_net_1 ), .B(\current_state[1]_net_1 ), .C(
        \current_state[2]_net_1 ), .D(AHB_IF_0_DATAOUT[0]), .Y(
        \addr_temp_cnst_i_a2_0_0_0_1[8]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[24]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[24] ), .Y(\addr_temp_lm[24] ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[9]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[9] ), .Y(\addr_temp_lm[9] ));
    CFG4 #( .INIT(16'h8A00) )  ram_wdata_0_sqmuxa_i_0_a3 (.A(
        ram_wdata_0_sqmuxa_i_0_a3_4_net_1), .B(N_272), .C(
        \current_state[14]_net_1 ), .D(
        ram_wdata_0_sqmuxa_i_0_a3_3_net_1), .Y(N_282));
    CFG4 #( .INIT(16'h00CE) )  \current_state_RNO[14]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[14]_net_1 ), .C(
        N_190), .D(N_272), .Y(N_341_i_0));
    CFG4 #( .INIT(16'hCC08) )  \addr_temp_cnst_i_a2_0_i[6]  (.A(
        \current_state[7]_net_1 ), .B(eSRAM_eNVM_access_0_HPMS_READY), 
        .C(AHB_IF_0_AHB_BUSY), .D(N_201), .Y(
        \addr_temp_cnst_i_a2_0_i[6]_net_1 ));
    SLE \data_cnt[1]  (.D(N_197_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[1]_net_1 ));
    SLE \ram_wdata[11]  (.D(AHB_IF_0_DATAOUT[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[11]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[16]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[16]), .D(
        GND_net_1), .FCI(\data_cry[15]_net_1 ), .S(\data_s[16] ), .Y(), 
        .FCO(\data_cry[16]_net_1 ));
    SLE \data[24]  (.D(\data_s[24] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[24]));
    CFG4 #( .INIT(16'h0037) )  READ_RNO_0 (.A(N_356), .B(
        un1_current_state_20_i_0_0_a3_2_net_1), .C(N_355), .D(
        un1_current_state_20_i_0_0_0_net_1), .Y(N_390_i_0));
    SLE \ram_wdata[31]  (.D(AHB_IF_0_DATAOUT[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[31]));
    SLE \addr_temp[30]  (.D(\addr_temp_lm[30] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[30]));
    SLE \data[30]  (.D(\data_s[30] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[30]));
    SLE \ram_wdata[6]  (.D(AHB_IF_0_DATAOUT[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[6]));
    ARI1 #( .INIT(20'h4BB8B) )  \data_cry[10]  (.A(N_46_i), .B(
        eSRAM_eNVM_RW_0_DATAOUT[10]), .C(\data_cry_cy_Y[0] ), .D(N_220)
        , .FCI(\data_cry[9]_net_1 ), .S(\data_s[10] ), .Y(), .FCO(
        \data_cry[10]_net_1 ));
    CFG4 #( .INIT(16'hCACE) )  \current_state_ns_0_0[2]  (.A(
        \current_state[1]_net_1 ), .B(\current_state[2]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(AHB_IF_0_DATAOUT[0]), .Y(
        \current_state_ns[2] ));
    SLE start_esram_reg2 (.D(start_esram_reg1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg2_net_1));
    ARI1 #( .INIT(20'h4E200) )  \data_cry[27]  (.A(VCC_net_1), .B(
        N_46_i), .C(\data_cry_cy_Y[0] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[27]), .FCI(\data_cry[26]_net_1 ), .S(
        \data_s[27] ), .Y(), .FCO(\data_cry[27]_net_1 ));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[6]  (.A(VCC_net_1), .B(N_220)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[6]), .FCI(
        \data_cry[5]_net_1 ), .S(\data_s[6] ), .Y(), .FCO(
        \data_cry[6]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \current_state_ns_i_0_0_a2[6]  (.A(
        \current_state[5]_net_1 ), .B(\current_state[6]_net_1 ), .Y(
        N_340));
    CFG4 #( .INIT(16'h7FFF) )  data_cnt_n3_i_o2 (.A(
        \data_cnt[3]_net_1 ), .B(\data_cnt[1]_net_1 ), .C(
        \data_cnt[2]_net_1 ), .D(\data_cnt[0]_net_1 ), .Y(N_214));
    CFG2 #( .INIT(4'h8) )  \current_state_RNIVC5B1[2]  (.A(N_365), .B(
        N_342), .Y(N_378));
    CFG4 #( .INIT(16'h353A) )  \ram_waddr_RNO[1]  (.A(
        eSRAM_eNVM_RW_0_ram_waddr[1]), .B(\current_state[0]_net_1 ), 
        .C(N_383), .D(eSRAM_eNVM_RW_0_ram_waddr[0]), .Y(N_243_i_0));
    CFG4 #( .INIT(16'hF0F1) )  \ram_waddr_RNO[0]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[0]), 
        .C(N_222), .D(N_272), .Y(N_9_i_0));
    SLE \data[1]  (.D(\data_s[1] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[1]));
    CFG3 #( .INIT(8'h10) )  WRITE_RNO_5 (.A(\current_state[16]_net_1 ), 
        .B(\current_state[4]_net_1 ), .C(N_181), .Y(
        un1_current_state_16_0_0_i_0_0_a3_0));
    SLE \current_state[16]  (.D(\current_state_ns[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[16]_net_1 ));
    SLE \data[6]  (.D(\data_s[6] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[6]));
    SLE \addr_temp[31]  (.D(\addr_temp_lm[31] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[31]));
    SLE \data[25]  (.D(\data_s[25] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[25]));
    CFG3 #( .INIT(8'hD5) )  \current_state_ns_0_0[5]  (.A(N_220), .B(
        \current_state[5]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns[5] ));
    SLE \ram_wdata[5]  (.D(AHB_IF_0_DATAOUT[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[5]));
    SLE start_envm_reg2 (.D(start_envm_reg1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg2_net_1));
    CFG3 #( .INIT(8'hC8) )  \data_cry_cy_RNO_0[0]  (.A(
        \current_state[4]_net_1 ), .B(\current_state[16]_net_1 ), .C(
        \current_state[2]_net_1 ), .Y(N_267));
    CFG4 #( .INIT(16'hECA0) )  \current_state_ns_0_0[12]  (.A(
        \current_state[11]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        N_370), .D(AHB_IF_0_AHB_BUSY), .Y(\current_state_ns[12] ));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[17]  (.A(
        \addr_temp_s[17] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_220), .Y(
        \addr_temp_lm[17] ));
    CFG4 #( .INIT(16'h08CC) )  \addr_temp_cnst_i_a2_0_i[3]  (.A(
        \current_state[7]_net_1 ), .B(eSRAM_eNVM_access_0_HPMS_READY), 
        .C(AHB_IF_0_AHB_BUSY), .D(N_268_2), .Y(N_82));
    ARI1 #( .INIT(20'h4B8BB) )  \data_cry[8]  (.A(N_220), .B(
        eSRAM_eNVM_RW_0_DATAOUT[8]), .C(\data_cry_cy_Y[0] ), .D(
        \data_13[31] ), .FCI(\data_cry[7]_net_1 ), .S(\data_s[8] ), .Y(
        ), .FCO(\data_cry[8]_net_1 ));
    SLE start_esram_reg (.D(start_esram_c), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg_net_1));
    CFG3 #( .INIT(8'h04) )  \current_state_ns_i_0_0_a2_0[6]  (.A(N_214)
        , .B(\data_cnt[4]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(N_370));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[18]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[18] ), .Y(\addr_temp_lm[18] ));
    SLE \ram_wdata[14]  (.D(AHB_IF_0_DATAOUT[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[14]));
    CFG4 #( .INIT(16'hFEAA) )  WRITE_RNO_2 (.A(
        un1_current_state_16_0_0_i_0_0_0), .B(
        un1_current_state_16_0_0_i_0_0_a3_0), .C(
        un1_current_state_16_0_0_i_0_0_a3_1_1), .D(N_349), .Y(
        un1_current_state_16_0_0_i_0_0_2));
    VCC VCC (.Y(VCC_net_1));
    SLE \data[31]  (.D(\data_s[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[31]));
    SLE \ram_wdata[28]  (.D(AHB_IF_0_DATAOUT[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[28]));
    SLE \data[8]  (.D(\data_s[8] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[8]));
    SLE \data[26]  (.D(\data_s[26] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[26]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[26]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[26]), .D(
        GND_net_1), .FCI(\data_cry[25]_net_1 ), .S(\data_s[26] ), .Y(), 
        .FCO(\data_cry[26]_net_1 ));
    CFG4 #( .INIT(16'hFCAC) )  \addr_temp_lm_0[7]  (.A(N_308), .B(
        \addr_temp_s[7] ), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_307), .Y(
        \addr_temp_lm[7] ));
    CFG2 #( .INIT(4'h2) )  \current_state_RNI1LPH[1]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[1]_net_1 ), .Y(N_352));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[29]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[29]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[28]_net_1 ), .S(\addr_temp_s[29] ), .Y(), .FCO(
        \addr_temp_cry[29]_net_1 ));
    CFG4 #( .INIT(16'hA0E0) )  ram_wdata_0_sqmuxa_i_0_o3_RNI3424 (.A(
        \current_state[13]_net_1 ), .B(\current_state[14]_net_1 ), .C(
        N_190), .D(N_272), .Y(ram_wdata_0_sqmuxa_i_0_o3_RNI3424_net_1));
    CFG4 #( .INIT(16'h0100) )  WRITE_RNO_1 (.A(
        \current_state[5]_net_1 ), .B(\current_state[16]_net_1 ), .C(
        \current_state[7]_net_1 ), .D(
        un1_current_state_16_0_0_i_0_0_a3_2_2), .Y(
        un1_current_state_16_0_0_i_0_0_a3_2_3));
    CFG4 #( .INIT(16'h0001) )  WRITE_RNO_3 (.A(
        \current_state[2]_net_1 ), .B(\current_state[11]_net_1 ), .C(
        \data_13[31] ), .D(\current_state[4]_net_1 ), .Y(
        un1_current_state_16_0_0_i_0_0_a3_2_2));
    SLE \ram_wdata[12]  (.D(AHB_IF_0_DATAOUT[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[12]));
    SLE \ram_waddr[1]  (.D(N_243_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[1]));
    SLE \current_state[13]  (.D(N_60), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[13]_net_1 ));
    CFG4 #( .INIT(16'hAFCF) )  \current_state_ns_i_i_0[13]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[9]_net_1 ), .C(
        N_202), .D(N_190), .Y(N_60));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[20]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[20]), .FCI(\data_cry[19]_net_1 ), .S(
        \data_s[20] ), .Y(), .FCO(\data_cry[20]_net_1 ));
    CFG4 #( .INIT(16'hFCF4) )  un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U (
        .A(\current_state[14]_net_1 ), .B(
        un1_addr_temp_8_sqmuxa_5_0_1_a3_0), .C(N_238), .D(N_272), .Y(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1));
    CFG4 #( .INIT(16'hFA3A) )  \addr_temp_lm_0[29]  (.A(
        \addr_temp_s[29] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_220), .Y(
        \addr_temp_lm[29] ));
    SLE \ram_wdata[26]  (.D(AHB_IF_0_DATAOUT[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[26]));
    CFG3 #( .INIT(8'h06) )  \data_cnt_RNO[1]  (.A(\data_cnt[1]_net_1 ), 
        .B(\data_cnt[0]_net_1 ), .C(N_575), .Y(N_197_i_0));
    CFG2 #( .INIT(4'hE) )  ram_wdata_0_sqmuxa_i_0_o2 (.A(
        \current_state[14]_net_1 ), .B(\current_state[15]_net_1 ), .Y(
        N_218));
    CFG2 #( .INIT(4'h1) )  data_cnt_n0_i_a3 (.A(N_575), .B(
        \data_cnt[0]_net_1 ), .Y(N_315));
    CFG4 #( .INIT(16'h08F8) )  \current_state_ns_0_0[16]  (.A(
        AHB_IF_0_VALID), .B(\current_state[15]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_175), .Y(\current_state_ns[16] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[4]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[4]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[3]_net_1 ), .S(\addr_temp_s[4] ), .Y(), .FCO(
        \addr_temp_cry[4]_net_1 ));
    SLE \addr_temp[2]  (.D(\addr_temp_lm[2] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[2]));
    CFG4 #( .INIT(16'h0004) )  \current_state_RNIMG5G1[2]  (.A(
        \current_state[4]_net_1 ), .B(N_175), .C(
        \current_state[2]_net_1 ), .D(\current_state[0]_net_1 ), .Y(
        N_369_i_i_0_a3_0_1));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[4]  (.A(VCC_net_1), .B(N_220)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[4]), .FCI(
        \data_cry[3]_net_1 ), .S(\data_s[4] ), .Y(), .FCO(
        \data_cry[4]_net_1 ));
    SLE \data[7]  (.D(\data_s[7] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[7]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[25]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[25]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[24]_net_1 ), .S(\addr_temp_s[25] ), .Y(), .FCO(
        \addr_temp_cry[25]_net_1 ));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[3]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[3]), 
        .C(N_217), .D(N_383), .Y(N_248_i_0));
    SLE \data[14]  (.D(\data_s[14] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[14]));
    SLE \data[0]  (.D(\data_s[0] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[0]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[9]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[9]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[8]_net_1 ), .S(\addr_temp_s[9] ), .Y(), .FCO(
        \addr_temp_cry[9]_net_1 ));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[5]  (.A(VCC_net_1), .B(N_220)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[5]), .FCI(
        \data_cry[4]_net_1 ), .S(\data_s[5] ), .Y(), .FCO(
        \data_cry[5]_net_1 ));
    CFG2 #( .INIT(4'hE) )  \current_state_RNIM2PE[12]  (.A(
        \current_state[9]_net_1 ), .B(\current_state[12]_net_1 ), .Y(
        N_222));
    CFG2 #( .INIT(4'h1) )  \addr_temp_cnst_i_a2_0_i_a3_0[5]  (.A(N_213)
        , .B(N_238), .Y(N_302));
    SLE \ram_waddr[3]  (.D(N_248_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[3]));
    CFG4 #( .INIT(16'hFF0E) )  \current_state_RNI6JBF1[6]  (.A(
        \current_state[6]_net_1 ), .B(\current_state[11]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_575), .Y(data_cnte));
    CFG2 #( .INIT(4'h7) )  data_cnt_n1_i_o2 (.A(\data_cnt[0]_net_1 ), 
        .B(\data_cnt[1]_net_1 ), .Y(N_194));
    SLE \data_cnt[3]  (.D(N_199_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[3]_net_1 ));
    CFG4 #( .INIT(16'h88F0) )  \addr_temp_lm_0[11]  (.A(
        eSRAM_eNVM_access_0_HPMS_READY), .B(\current_state[9]_net_1 ), 
        .C(\addr_temp_s[11] ), .D(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .Y(
        \addr_temp_lm[11] ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[26]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[26] ), .Y(\addr_temp_lm[26] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[19]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[19]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[18]_net_1 ), .S(\addr_temp_s[19] ), .Y(), .FCO(
        \addr_temp_cry[19]_net_1 ));
    SLE \ram_wdata[13]  (.D(AHB_IF_0_DATAOUT[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[13]));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_3 (.A(
        \current_state[11]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        \current_state[15]_net_1 ), .D(\current_state[5]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_3_net_1));
    SLE \ram_wdata[3]  (.D(AHB_IF_0_DATAOUT[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[3]));
    SLE \data_cnt[0]  (.D(N_315), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .EN(data_cnte), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\data_cnt[0]_net_1 ));
    SLE \current_state[12]  (.D(\current_state_ns[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[6]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[6]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[5]_net_1 ), .S(\addr_temp_s[6] ), .Y(), .FCO(
        \addr_temp_cry[6]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_1_1 (.A(
        \data_13[31] ), .B(N_218), .C(\current_state[8]_net_1 ), .D(
        \current_state[11]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1));
    SLE \data[15]  (.D(\data_s[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[15]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[13]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[13] ), .Y(\addr_temp_lm[13] ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[20]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[20] ), .Y(\addr_temp_lm[20] ));
    CFG4 #( .INIT(16'h0004) )  un1_READ_1_sqmuxa_2_i_0_0_a3_1 (.A(
        \current_state[14]_net_1 ), .B(N_213), .C(
        \current_state[3]_net_1 ), .D(\current_state[1]_net_1 ), .Y(
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1));
    SLE \ram_wdata[25]  (.D(AHB_IF_0_DATAOUT[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[25]));
    SLE \data[29]  (.D(\data_s[29] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[29]));
    CFG3 #( .INIT(8'h10) )  un1_current_state_20_i_0_0_a2_1 (.A(
        \current_state[2]_net_1 ), .B(\current_state[4]_net_1 ), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1), .Y(N_356));
    ARI1 #( .INIT(20'h4BB8B) )  \data_cry[7]  (.A(N_46_i), .B(
        eSRAM_eNVM_RW_0_DATAOUT[7]), .C(\data_cry_cy_Y[0] ), .D(N_220), 
        .FCI(\data_cry[6]_net_1 ), .S(\data_s[7] ), .Y(), .FCO(
        \data_cry[7]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \current_state_ns_0_0_o2[3]  (.A(
        AHB_IF_0_DATAOUT[0]), .B(\current_state[2]_net_1 ), .Y(N_181));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[25]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[25] ), .Y(\addr_temp_lm[25] ));
    ARI1 #( .INIT(20'h4BB8B) )  \data_cry[11]  (.A(N_46_i), .B(
        eSRAM_eNVM_RW_0_DATAOUT[11]), .C(\data_cry_cy_Y[0] ), .D(N_220)
        , .FCI(\data_cry[10]_net_1 ), .S(\data_s[11] ), .Y(), .FCO(
        \data_cry[11]_net_1 ));
    SLE \data[16]  (.D(\data_s[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[16]));
    SLE \ram_wdata[20]  (.D(AHB_IF_0_DATAOUT[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[20]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[15]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[15]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[14]_net_1 ), .S(\addr_temp_s[15] ), .Y(), .FCO(
        \addr_temp_cry[15]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[31]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[31]_net_1 ), .Y(\addr_temp_lm[31] ));
    CFG3 #( .INIT(8'h01) )  un1_READ_1_sqmuxa_2_i_0_a2_1 (.A(
        \current_state[8]_net_1 ), .B(\current_state[1]_net_1 ), .C(
        \current_state[3]_net_1 ), .Y(N_376));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[8]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[8]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[7]_net_1 ), .S(\addr_temp_s[8] ), .Y(), .FCO(
        \addr_temp_cry[8]_net_1 ));
    CFG4 #( .INIT(16'hA020) )  un1_READ_1_sqmuxa_2_i_0_a3_0_RNITQ1O3 (
        .A(N_219), .B(\current_state[14]_net_1 ), .C(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2), .D(N_272), .Y(N_269));
    SLE \ram_wdata[29]  (.D(AHB_IF_0_DATAOUT[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[29]));
    CFG4 #( .INIT(16'hFE30) )  un1_current_state_19_i_0_0_0 (.A(
        \current_state[4]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        N_373), .D(AHB_IF_0_DATAOUT[0]), .Y(
        un1_current_state_19_i_0_0_0_net_1));
    CFG3 #( .INIT(8'hFE) )  \current_state_RNIHICS[12]  (.A(
        \current_state[12]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        \current_state[0]_net_1 ), .Y(N_575));
    CFG4 #( .INIT(16'hFFFE) )  \data_cry_cy_RNO[0]  (.A(
        \current_state[0]_net_1 ), .B(\data_13[31] ), .C(
        \current_state[5]_net_1 ), .D(\current_state[7]_net_1 ), .Y(
        un1_READ6_3_0_0_1_1));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[22]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[22] ), .Y(\addr_temp_lm[22] ));
    CFG4 #( .INIT(16'h2000) )  un1_current_state_19_i_0_0_a3_0_2 (.A(
        N_376), .B(\current_state[12]_net_1 ), .C(N_349), .D(N_342), 
        .Y(un1_current_state_19_i_0_0_a3_0_2_net_1));
    SLE start_envm_reg1 (.D(start_envm_reg_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg1_net_1));
    CFG2 #( .INIT(4'hB) )  ram_waddr_n3_0_o2 (.A(N_203), .B(
        eSRAM_eNVM_RW_0_ram_waddr[2]), .Y(N_217));
    SLE \addr_temp[14]  (.D(\addr_temp_lm[14] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[14]));
    SLE \current_state[7]  (.D(\current_state_ns[7] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[7]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[13]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[13]), .D(
        GND_net_1), .FCI(\data_cry[12]_net_1 ), .S(\data_s[13] ), .Y(), 
        .FCO(\data_cry[13]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  \current_state_RNI1C5N2[9]  (.A(
        \data_13[31] ), .B(\current_state[9]_net_1 ), .C(N_352), .D(
        N_268_2), .Y(N_268));
    CFG3 #( .INIT(8'h40) )  \addr_temp_cnst_0_a2_0_0_a3[19]  (.A(
        \current_state[9]_net_1 ), .B(N_374), .C(N_220), .Y(N_303));
    CFG3 #( .INIT(8'hFE) )  un1_ram_wen_0_sqmuxa_i_0_0_0 (.A(N_272), 
        .B(\current_state[0]_net_1 ), .C(N_222), .Y(N_383));
    CFG4 #( .INIT(16'hFEF0) )  un1_current_state_20_i_0_0_0 (.A(
        \current_state[4]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        N_310), .D(AHB_IF_0_DATAOUT[0]), .Y(
        un1_current_state_20_i_0_0_0_net_1));
    SLE READ (.D(N_378_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_390_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_READ));
    CFG2 #( .INIT(4'hB) )  un1_READ_1_sqmuxa_2_i_0_0_o2 (.A(
        AHB_IF_0_DATAOUT[0]), .B(\current_state[8]_net_1 ), .Y(N_213));
    SLE \addr_temp[24]  (.D(\addr_temp_lm[24] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[24]));
    SLE \data[2]  (.D(\data_s[2] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[2]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[2]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[2]), .D(
        GND_net_1), .FCI(\data_cry[1]_net_1 ), .S(\data_s[2] ), .Y(), 
        .FCO(\data_cry[2]_net_1 ));
    SLE ram_wen (.D(N_244), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_387_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_ram_wen));
    SLE \addr_temp[4]  (.D(\addr_temp_lm[4] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[4]));
    CFG4 #( .INIT(16'hFFFE) )  un1_READ_1_sqmuxa_2_i_0_a3_0_RNIPF9V (
        .A(N_244), .B(N_272), .C(\current_state[0]_net_1 ), .D(N_222), 
        .Y(ram_waddre));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[21]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[21]), .FCI(\data_cry[20]_net_1 ), .S(
        \data_s[21] ), .Y(), .FCO(\data_cry[21]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \current_state_RNIHTOE[16]  (.A(
        \current_state[0]_net_1 ), .B(\current_state[16]_net_1 ), .Y(
        N_342));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[23]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[23]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[22]_net_1 ), .S(\addr_temp_s[23] ), .Y(), .FCO(
        \addr_temp_cry[23]_net_1 ));
    SLE \data[27]  (.D(\data_s[27] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[27]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_s[31]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[31]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[30]_net_1 ), .S(\addr_temp_s[31]_net_1 ), .Y(), 
        .FCO());
    SLE \ram_wdata[27]  (.D(AHB_IF_0_DATAOUT[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[27]));
    SLE \data[28]  (.D(\data_s[28] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[28]));
    CFG2 #( .INIT(4'h2) )  \addr_temp_cnst_0_a2_0_0_a2[30]  (.A(N_202), 
        .B(\data_13[31] ), .Y(N_374));
    ARI1 #( .INIT(20'h48800) )  \data_cry[3]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[3]), .D(
        GND_net_1), .FCI(\data_cry[2]_net_1 ), .S(\data_s[3] ), .Y(), 
        .FCO(\data_cry[3]_net_1 ));
    CFG2 #( .INIT(4'h4) )  esram_select (.A(start_esram_reg1_net_1), 
        .B(start_esram_reg2_net_1), .Y(esram_select_net_1));
    CFG3 #( .INIT(8'hB3) )  envm_release_reg_RNINV5J (.A(
        \current_state[16]_net_1 ), .B(N_181), .C(
        envm_release_reg_net_1), .Y(N_201));
    CFG4 #( .INIT(16'h0C2E) )  \current_state_RNO[11]  (.A(
        \current_state[11]_net_1 ), .B(\data_13[31] ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_370), .Y(N_336_i_0));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[12]  (.A(VCC_net_1), .B(
        N_220), .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[12])
        , .FCI(\data_cry[11]_net_1 ), .S(\data_s[12] ), .Y(), .FCO(
        \data_cry[12]_net_1 ));
    CFG2 #( .INIT(4'hB) )  ram_waddr_n4_0_o2 (.A(N_217), .B(
        eSRAM_eNVM_RW_0_ram_waddr[3]), .Y(N_233));
    SLE envm_release_reg (.D(\current_state[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(un40_0_0_0_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        envm_release_reg_net_1));
    CFG4 #( .INIT(16'h0C55) )  \addr_temp_lm_0[2]  (.A(
        eSRAM_eNVM_RW_0_ADDR[2]), .B(eSRAM_eNVM_access_0_HPMS_READY), 
        .C(N_268_2), .D(un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), 
        .Y(\addr_temp_lm[2] ));
    SLE \data[19]  (.D(\data_s[19] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[19]));
    SLE \ram_waddr[0]  (.D(N_9_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[0]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[23]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[23]), .FCI(\data_cry[22]_net_1 ), .S(
        \data_s[23] ), .Y(), .FCO(\data_cry[23]_net_1 ));
    SLE \current_state[4]  (.D(N_83), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[4]_net_1 ));
    SLE \data[22]  (.D(\data_s[22] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[22]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[30]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[30]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[29]_net_1 ), .S(\addr_temp_s[30] ), .Y(), .FCO(
        \addr_temp_cry[30]_net_1 ));
    CFG3 #( .INIT(8'hA8) )  \addr_temp_cnst_i_a2_0_i_a3[7]  (.A(
        eSRAM_eNVM_access_0_HPMS_READY), .B(\current_state[9]_net_1 ), 
        .C(N_201), .Y(N_307));
    CFG4 #( .INIT(16'h8000) )  un1_READ_1_sqmuxa_2_i_0_a3_0_3 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[3]), .B(eSRAM_eNVM_RW_0_ram_waddr[2])
        , .C(\current_state[14]_net_1 ), .D(
        eSRAM_eNVM_RW_0_ram_waddr[4]), .Y(
        un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1));
    SLE \addr_temp[10]  (.D(\addr_temp_lm[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[10]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[15]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[15]), .FCI(\data_cry[14]_net_1 ), .S(
        \data_s[15] ), .Y(), .FCO(\data_cry[15]_net_1 ));
    SLE \ram_waddr[2]  (.D(N_246_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[2]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[14]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[14] ), .Y(\addr_temp_lm[14] ));
    SLE \addr_temp[8]  (.D(\addr_temp_lm[8] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[8]));
    ARI1 #( .INIT(20'h4E400) )  \data_s[31]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[31]), .FCI(\data_cry[30]_net_1 ), .S(
        \data_s[31]_net_1 ), .Y(), .FCO());
    CFG4 #( .INIT(16'h0151) )  \current_state_RNO[6]  (.A(N_340), .B(
        N_370), .C(\current_state[5]_net_1 ), .D(AHB_IF_0_AHB_BUSY), 
        .Y(N_330_i_0));
    SLE \current_state[10]  (.D(\current_state_ns[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\data_13[31] ));
    SLE \current_state[0]  (.D(\current_state_ns[0] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[0]_net_1 ));
    CFG3 #( .INIT(8'h20) )  un1_current_state_19_i_0_0_a3_2 (.A(N_378), 
        .B(\current_state[12]_net_1 ), .C(N_352), .Y(N_277));
    SLE \ram_wdata[18]  (.D(AHB_IF_0_DATAOUT[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[18]));
    SLE \addr_temp[9]  (.D(\addr_temp_lm[9] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[9]));
    SLE \ram_wdata[7]  (.D(AHB_IF_0_DATAOUT[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[7]));
    SLE \addr_temp[20]  (.D(\addr_temp_lm[20] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[20]));
    SLE \addr_temp[17]  (.D(\addr_temp_lm[17] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[17]));
    CFG3 #( .INIT(8'hFB) )  ram_wdata_0_sqmuxa_i_0_1 (.A(N_283), .B(
        eSRAM_eNVM_access_0_HPMS_READY), .C(N_190), .Y(
        ram_wdata_0_sqmuxa_i_0_1_net_1));
    CFG4 #( .INIT(16'h1BBB) )  \current_state_RNIKDK11_0[4]  (.A(
        \current_state[4]_net_1 ), .B(AHB_IF_0_DATAOUT[0]), .C(
        AHB_IF_0_DATAOUT[2]), .D(AHB_IF_0_DATAOUT[1]), .Y(N_230));
    SLE \addr_temp[5]  (.D(\addr_temp_lm[5] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[5]));
    CFG2 #( .INIT(4'h8) )  \current_state_RNI5BDG1[4]  (.A(N_230), .B(
        N_342), .Y(N_369_i_i_0_a3_0));
    CFG4 #( .INIT(16'hF4F0) )  \current_state_ns_i_i_0[1]  (.A(
        \current_state[0]_net_1 ), .B(\current_state[1]_net_1 ), .C(
        N_331), .D(AHB_IF_0_AHB_BUSY), .Y(N_50));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[13]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[13]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[12]_net_1 ), .S(\addr_temp_s[13] ), .Y(), .FCO(
        \addr_temp_cry[13]_net_1 ));
    SLE \addr_temp[11]  (.D(\addr_temp_lm[11] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[11]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[28]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[28]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[27]_net_1 ), .S(\addr_temp_s[28] ), .Y(), .FCO(
        \addr_temp_cry[28]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[1]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[1]), .D(
        GND_net_1), .FCI(\data_cry[0]_net_1 ), .S(\data_s[1] ), .Y(), 
        .FCO(\data_cry[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[27]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[27] ), .Y(\addr_temp_lm[27] ));
    SLE \ram_wdata[2]  (.D(AHB_IF_0_DATAOUT[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[2]));
    CFG3 #( .INIT(8'h40) )  un1_current_state_20_i_0_0_a3_1 (.A(
        \current_state[14]_net_1 ), .B(N_376), .C(N_342), .Y(
        un1_current_state_20_i_0_0_a3_1_net_1));
    CFG2 #( .INIT(4'h8) )  un1_current_state_20_i_0_0_a2_0 (.A(N_188), 
        .B(N_364), .Y(N_355));
    SLE \addr_temp[27]  (.D(\addr_temp_lm[27] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[27]));
    SLE \ram_wdata[16]  (.D(AHB_IF_0_DATAOUT[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[16]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[28]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[28] ), .Y(\addr_temp_lm[28] ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[22]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[22]), .D(
        GND_net_1), .FCI(\data_cry[21]_net_1 ), .S(\data_s[22] ), .Y(), 
        .FCO(\data_cry[22]_net_1 ));
    CFG3 #( .INIT(8'h01) )  \current_state_RNIEFCS[2]  (.A(
        \current_state[2]_net_1 ), .B(\current_state[4]_net_1 ), .C(
        \data_13[31] ), .Y(N_365));
    CFG4 #( .INIT(16'h0400) )  \current_state_ns_i_i_0_a3_0[1]  (.A(
        start_envm_reg1_net_1), .B(start_envm_reg2_net_1), .C(
        esram_select_net_1), .D(\current_state[0]_net_1 ), .Y(N_331));
    CFG2 #( .INIT(4'hD) )  \current_state_ns_0_0[8]  (.A(N_213), .B(
        N_46_i), .Y(\current_state_ns[8] ));
    CFG4 #( .INIT(16'h0133) )  \current_state_RNIACPO5[2]  (.A(
        N_369_i_i_0_a3_0), .B(N_369_i_i_0_0), .C(N_369_i_i_0_a3_0_1), 
        .D(N_349), .Y(N_18_i_0));
    SLE \addr_temp[21]  (.D(\addr_temp_lm[21] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[21]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[5]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[5]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[4]_net_1 ), .S(\addr_temp_s[5] ), .Y(), .FCO(
        \addr_temp_cry[5]_net_1 ));
    SLE \current_state[14]  (.D(N_341_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[14]_net_1 ));
    SLE \addr_temp[19]  (.D(\addr_temp_lm[19] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[19]));
    SLE \ram_wdata[21]  (.D(AHB_IF_0_DATAOUT[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[21]));
    SLE \current_state[11]  (.D(N_336_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[11]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \addr_temp_lm_0[6]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[6] ), .C(\addr_temp_cnst_i_a2_0_i[6]_net_1 ), .Y(
        \addr_temp_lm[6] ));
    CFG4 #( .INIT(16'h0111) )  WRITE_RNO_6 (.A(
        \current_state[16]_net_1 ), .B(\current_state[2]_net_1 ), .C(
        AHB_IF_0_DATAOUT[2]), .D(AHB_IF_0_DATAOUT[1]), .Y(
        un1_current_state_16_0_0_i_0_0_a3_1_1));
    CFG4 #( .INIT(16'h0008) )  un1_current_state_20_i_0_0_a3_2 (.A(
        N_340), .B(un1_current_state_20_i_0_0_a3_1_net_1), .C(
        \current_state[11]_net_1 ), .D(\data_13[31] ), .Y(
        un1_current_state_20_i_0_0_a3_2_net_1));
    CFG3 #( .INIT(8'h01) )  \current_state_RNI37UF[6]  (.A(
        \current_state[11]_net_1 ), .B(\current_state[6]_net_1 ), .C(
        \current_state[13]_net_1 ), .Y(
        un1_addr_temp_8_sqmuxa_5_0_1_a3_0));
    CFG4 #( .INIT(16'hFCAC) )  \addr_temp_lm_0[5]  (.A(N_302), .B(
        \addr_temp_s[5] ), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_301), .Y(
        \addr_temp_lm[5] ));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_4 (.A(
        \current_state[3]_net_1 ), .B(\current_state[13]_net_1 ), .C(
        \current_state[1]_net_1 ), .D(\current_state[9]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_4_net_1));
    CFG4 #( .INIT(16'hFFBF) )  \current_state_ns_i_i_0_o2[4]  (.A(
        \current_state[3]_net_1 ), .B(AHB_IF_0_DATAOUT[2]), .C(
        AHB_IF_0_DATAOUT[1]), .D(AHB_IF_0_DATAOUT[0]), .Y(N_253));
    ARI1 #( .INIT(20'h48800) )  \data_cry[25]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[25]), .D(
        GND_net_1), .FCI(\data_cry[24]_net_1 ), .S(\data_s[25] ), .Y(), 
        .FCO(\data_cry[25]_net_1 ));
    SLE \data[17]  (.D(\data_s[17] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[17]));
    SLE \addr_temp[29]  (.D(\addr_temp_lm[29] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[29]));
    CFG4 #( .INIT(16'h3230) )  un1_READ_1_sqmuxa_2_i_0_0_0 (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1), .B(
        \current_state[14]_net_1 ), .C(N_352), .D(N_376), .Y(
        un1_READ_1_sqmuxa_2_i_0_0_0_net_1));
    SLE \current_state[8]  (.D(\current_state_ns[8] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[8]_net_1 ));
    SLE \current_state[1]  (.D(N_50), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[1]_net_1 ));
    SLE \current_state[15]  (.D(\current_state_ns[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[21]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[21]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[20]_net_1 ), .S(\addr_temp_s[21] ), .Y(), .FCO(
        \addr_temp_cry[21]_net_1 ));
    SLE WRITE (.D(N_792_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_392_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_WRITE));
    CFG3 #( .INIT(8'h41) )  \data_cnt_RNO[4]  (.A(N_575), .B(
        \data_cnt[4]_net_1 ), .C(N_214), .Y(N_200_i_0));
    SLE \data[18]  (.D(\data_s[18] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[18]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[14]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[14]), .FCI(\data_cry[13]_net_1 ), .S(
        \data_s[14] ), .Y(), .FCO(\data_cry[14]_net_1 ));
    SLE \data[20]  (.D(\data_s[20] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[20]));
    CFG3 #( .INIT(8'hEA) )  \current_state_ns_0_0[15]  (.A(N_272), .B(
        \current_state[15]_net_1 ), .C(N_190), .Y(
        \current_state_ns[15] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[22]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[22]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[21]_net_1 ), .S(\addr_temp_s[22] ), .Y(), .FCO(
        \addr_temp_cry[22]_net_1 ));
    SLE \current_state[3]  (.D(\current_state_ns[3] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[3]_net_1 ));
    SLE \current_state[9]  (.D(\current_state_ns[9] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[9]_net_1 ));
    SLE \data[23]  (.D(\data_s[23] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[23]));
    CFG3 #( .INIT(8'hC5) )  \current_state_ns_0_0[3]  (.A(N_181), .B(
        \current_state[3]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns[3] ));
    CFG4 #( .INIT(16'hAEAA) )  WRITE_RNO_4 (.A(N_373), .B(N_365), .C(
        \current_state[16]_net_1 ), .D(AHB_IF_0_AHB_BUSY), .Y(
        un1_current_state_16_0_0_i_0_0_0));
    CFG4 #( .INIT(16'h5530) )  \current_state_RNIORRS1[8]  (.A(
        \current_state[2]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        N_187), .D(AHB_IF_0_DATAOUT[0]), .Y(N_219));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[18]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[18]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[17]_net_1 ), .S(\addr_temp_s[18] ), .Y(), .FCO(
        \addr_temp_cry[18]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \current_state_RNI7RPH[7]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[7]_net_1 ), .Y(N_46_i));
    CFG4 #( .INIT(16'h0A88) )  \current_state_RNICMIM1[2]  (.A(N_175), 
        .B(N_187), .C(\current_state[2]_net_1 ), .D(
        AHB_IF_0_DATAOUT[0]), .Y(N_268_2));
    CFG4 #( .INIT(16'h0015) )  WRITE_RNO_0 (.A(
        un1_current_state_19_i_0_0_0_net_1), .B(N_188), .C(
        un1_current_state_19_i_0_0_a3_0_2_net_1), .D(N_277), .Y(
        N_392_i_0));
    CFG4 #( .INIT(16'h0F0D) )  ram_wen_RNO (.A(N_342), .B(
        \current_state[13]_net_1 ), .C(N_272), .D(N_244), .Y(N_387_i_0)
        );
    CFG4 #( .INIT(16'hFA3A) )  \addr_temp_lm_0[19]  (.A(
        \addr_temp_s[19] ), .B(eSRAM_eNVM_access_0_HPMS_READY), .C(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_303), .Y(
        \addr_temp_lm[19] ));
    SLE \addr_temp[12]  (.D(\addr_temp_lm[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[12]));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_0_2 (.A(
        \current_state[13]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        \current_state[7]_net_1 ), .D(\current_state[4]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1));
    SLE \ram_wdata[24]  (.D(AHB_IF_0_DATAOUT[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[24]));
    CFG4 #( .INIT(16'hEAC0) )  \current_state_ns_0_0[10]  (.A(
        AHB_IF_0_AHB_BUSY), .B(esram_select_net_1), .C(
        \current_state[0]_net_1 ), .D(\data_13[31] ), .Y(
        \current_state_ns[10] ));
    SLE \data[12]  (.D(\data_s[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[12]));
    SLE \addr_temp[18]  (.D(\addr_temp_lm[18] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[18]));
    CFG4 #( .INIT(16'h0013) )  READ_RNO (.A(
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1), .B(N_272), .C(N_364), 
        .D(un1_READ_1_sqmuxa_2_i_0_0_0_net_1), .Y(N_378_i_0));
    SLE \ram_wdata[15]  (.D(AHB_IF_0_DATAOUT[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[15]));
    CFG4 #( .INIT(16'hECA0) )  \current_state_RNIJMK32[4]  (.A(
        AHB_IF_0_DATAOUT[0]), .B(N_378), .C(\current_state[4]_net_1 ), 
        .D(AHB_IF_0_AHB_BUSY), .Y(N_369_i_i_0_0));
    SLE \ram_wdata[1]  (.D(AHB_IF_0_DATAOUT[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[1]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[19]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[19]), .D(
        GND_net_1), .FCI(\data_cry[18]_net_1 ), .S(\data_s[19] ), .Y(), 
        .FCO(\data_cry[19]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[18]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[18]), .D(
        GND_net_1), .FCI(\data_cry[17]_net_1 ), .S(\data_s[18] ), .Y(), 
        .FCO(\data_cry[18]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[30]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[30]), .D(
        GND_net_1), .FCI(\data_cry[29]_net_1 ), .S(\data_s[30] ), .Y(), 
        .FCO(\data_cry[30]_net_1 ));
    CFG3 #( .INIT(8'h7F) )  \current_state_RNI4SUQ[4]  (.A(
        AHB_IF_0_DATAOUT[1]), .B(\current_state[4]_net_1 ), .C(
        AHB_IF_0_DATAOUT[2]), .Y(N_187));
    CFG2 #( .INIT(4'hB) )  ram_wdata_0_sqmuxa_i_0_o3 (.A(
        AHB_IF_0_AHB_BUSY), .B(AHB_IF_0_VALID), .Y(N_190));
    ARI1 #( .INIT(20'h4AA00) )  addr_temp_s_15 (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[2]), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(addr_temp_s_15_FCO));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[21]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[21] ), .Y(\addr_temp_lm[21] ));
    SLE \addr_temp[22]  (.D(\addr_temp_lm[22] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[22]));
    SLE \ram_wdata[22]  (.D(AHB_IF_0_DATAOUT[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[22]));
    SLE \ram_wdata[10]  (.D(AHB_IF_0_DATAOUT[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[10]));
    CFG4 #( .INIT(16'h0C5C) )  \addr_temp_lm_0[8]  (.A(
        \addr_temp_cnst_i_a2_0_0_0[8]_net_1 ), .B(\addr_temp_s[8] ), 
        .C(un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .D(N_306), .Y(
        \addr_temp_lm[8] ));
    SLE \data[21]  (.D(\data_s[21] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_18_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[21]));
    SLE \addr_temp[28]  (.D(\addr_temp_lm[28] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[28]));
    CFG3 #( .INIT(8'hF1) )  un40_0_0_0 (.A(N_175), .B(
        AHB_IF_0_AHB_BUSY), .C(\current_state[9]_net_1 ), .Y(
        un40_0_0_0_net_1));
    CFG4 #( .INIT(16'h0C06) )  \data_cnt_RNO[3]  (.A(
        \data_cnt[2]_net_1 ), .B(\data_cnt[3]_net_1 ), .C(N_575), .D(
        N_194), .Y(N_199_i_0));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[23]  (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_0_RNIDE2U_net_1), .B(
        \addr_temp_s[23] ), .Y(\addr_temp_lm[23] ));
    SLE \addr_temp[15]  (.D(\addr_temp_lm[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_35_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[15]));
    SLE \ram_wdata[19]  (.D(AHB_IF_0_DATAOUT[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[19]));
    SLE \ram_wdata[0]  (.D(AHB_IF_0_DATAOUT[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[0]));
    SLE \ram_wdata[30]  (.D(AHB_IF_0_DATAOUT[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_87_i_0), .ALn(VCC_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[30]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[11]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[11]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[10]_net_1 ), .S(\addr_temp_s[11] ), .Y(), .FCO(
        \addr_temp_cry[11]_net_1 ));
    SLE \data[3]  (.D(\data_s[3] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_18_i_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[3]));
    
endmodule


module AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(
       eSRAM_eNVM_RW_0_DATAOUT,
       AHB_IF_0_DATAOUT,
       AHB_IF_0_BIF_1_HRDATA,
       AHB_IF_0_BIF_1_HWDATA,
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HTRANS,
       ahb_fsm_current_state,
       eSRAM_eNVM_RW_0_ADDR,
       ahb_fsm_current_state_ns_0,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_access_0_HPMS_READY,
       DATAOUT_1_sqmuxa,
       HWDATA_1_sqmuxa,
       N_101_i_0,
       AHB_IF_0_VALID,
       N_51_0_i_0,
       AHB_IF_0_AHB_BUSY,
       N_541_i_0,
       N_55_0,
       N_126_i_0,
       N_148_mux_i_0,
       AHB_IF_0_BIF_1_HWRITE,
       N_147_mux_i_0,
       N_144_mux_i_0,
       HREADY_M_iv_i_0,
       N_143_mux_i_0,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ
    );
input  [31:0] eSRAM_eNVM_RW_0_DATAOUT;
output [31:0] AHB_IF_0_DATAOUT;
input  [31:0] AHB_IF_0_BIF_1_HRDATA;
output [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:2] AHB_IF_0_BIF_1_HADDR;
output [1:1] AHB_IF_0_BIF_1_HTRANS;
output [6:0] ahb_fsm_current_state;
input  [31:2] eSRAM_eNVM_RW_0_ADDR;
input  ahb_fsm_current_state_ns_0;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  eSRAM_eNVM_access_0_HPMS_READY;
input  DATAOUT_1_sqmuxa;
input  HWDATA_1_sqmuxa;
input  N_101_i_0;
output AHB_IF_0_VALID;
input  N_51_0_i_0;
output AHB_IF_0_AHB_BUSY;
input  N_541_i_0;
input  N_55_0;
input  N_126_i_0;
input  N_148_mux_i_0;
output AHB_IF_0_BIF_1_HWRITE;
input  N_147_mux_i_0;
input  N_144_mux_i_0;
input  HREADY_M_iv_i_0;
input  N_143_mux_i_0;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;

    wire \HWDATA_int[20]_net_1 , VCC_net_1, HWDATA_int_0_sqmuxa, 
        GND_net_1, \HWDATA_int[21]_net_1 , \HWDATA_int[22]_net_1 , 
        \HWDATA_int[23]_net_1 , \HWDATA_int[24]_net_1 , 
        \HWDATA_int[25]_net_1 , \HWDATA_int[26]_net_1 , 
        \HWDATA_int[27]_net_1 , \HWDATA_int[28]_net_1 , 
        \HWDATA_int[29]_net_1 , \HWDATA_int[30]_net_1 , 
        \HWDATA_int[31]_net_1 , \HWDATA_int[5]_net_1 , 
        \HWDATA_int[6]_net_1 , \HWDATA_int[7]_net_1 , 
        \HWDATA_int[8]_net_1 , \HWDATA_int[9]_net_1 , 
        \HWDATA_int[10]_net_1 , \HWDATA_int[11]_net_1 , 
        \HWDATA_int[12]_net_1 , \HWDATA_int[13]_net_1 , 
        \HWDATA_int[14]_net_1 , \HWDATA_int[15]_net_1 , 
        \HWDATA_int[16]_net_1 , \HWDATA_int[17]_net_1 , 
        \HWDATA_int[18]_net_1 , \HWDATA_int[19]_net_1 , 
        \HWDATA_int[0]_net_1 , \HWDATA_int[1]_net_1 , 
        \HWDATA_int[2]_net_1 , \HWDATA_int[3]_net_1 , 
        \HWDATA_int[4]_net_1 , \HADDR_6[26]_net_1 , 
        \HADDR_6[27]_net_1 , \HADDR_6[28]_net_1 , \HADDR_6[29]_net_1 , 
        \HADDR_6[30]_net_1 , \HADDR_6[31]_net_1 , \HADDR_6[11]_net_1 , 
        \HADDR_6[12]_net_1 , \HADDR_6[13]_net_1 , \HADDR_6[14]_net_1 , 
        \HADDR_6[15]_net_1 , \HADDR_6[16]_net_1 , \HADDR_6[17]_net_1 , 
        \HADDR_6[18]_net_1 , \HADDR_6[19]_net_1 , \HADDR_6[20]_net_1 , 
        \HADDR_6[21]_net_1 , \HADDR_6[22]_net_1 , \HADDR_6[23]_net_1 , 
        \HADDR_6[24]_net_1 , \HADDR_6[25]_net_1 , \HADDR_6[2]_net_1 , 
        \HADDR_6[3]_net_1 , \HADDR_6[4]_net_1 , \HADDR_6[5]_net_1 , 
        \HADDR_6[6]_net_1 , \HADDR_6[7]_net_1 , \HADDR_6[8]_net_1 , 
        \HADDR_6[9]_net_1 , \HADDR_6[10]_net_1 , N_94_i_0, 
        \ahb_fsm_current_state_ns[4] ;
    
    SLE \HADDR[9]  (.D(\HADDR_6[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[9]));
    SLE \HADDR[19]  (.D(\HADDR_6[19]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[19]));
    SLE \DATAOUT[2]  (.D(AHB_IF_0_BIF_1_HRDATA[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[2]));
    SLE \HADDR[8]  (.D(\HADDR_6[8]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[8]));
    SLE \HWDATA_int[0]  (.D(eSRAM_eNVM_RW_0_DATAOUT[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[0]_net_1 ));
    SLE \HWDATA_int[29]  (.D(eSRAM_eNVM_RW_0_DATAOUT[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[29]_net_1 ));
    SLE \HWDATA[5]  (.D(\HWDATA_int[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[5]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[10]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[10]), .Y(\HADDR_6[10]_net_1 ));
    SLE \ahb_fsm_current_state[3]  (.D(ahb_fsm_current_state[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HREADY_M_iv_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[3]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[3]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[3]), .Y(\HADDR_6[3]_net_1 ));
    SLE \DATAOUT[1]  (.D(AHB_IF_0_BIF_1_HRDATA[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[1]));
    SLE \DATAOUT[21]  (.D(AHB_IF_0_BIF_1_HRDATA[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[21]));
    SLE \DATAOUT[22]  (.D(AHB_IF_0_BIF_1_HRDATA[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[22]));
    SLE \HWDATA_int[9]  (.D(eSRAM_eNVM_RW_0_DATAOUT[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[9]_net_1 ));
    SLE \ahb_fsm_current_state[5]  (.D(N_143_mux_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[5]));
    SLE \HADDR[6]  (.D(\HADDR_6[6]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[6]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[29]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[29]), .Y(\HADDR_6[29]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[28]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[28]), .Y(\HADDR_6[28]_net_1 ));
    SLE \DATAOUT[23]  (.D(AHB_IF_0_BIF_1_HRDATA[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[23]));
    SLE \HADDR[18]  (.D(\HADDR_6[18]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[18]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[5]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[5]), .Y(\HADDR_6[5]_net_1 ));
    SLE \HWDATA_int[7]  (.D(eSRAM_eNVM_RW_0_DATAOUT[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[7]_net_1 ));
    SLE \HWDATA_int[18]  (.D(eSRAM_eNVM_RW_0_DATAOUT[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[18]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[27]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[27]), .Y(\HADDR_6[27]_net_1 ));
    SLE \HADDR[3]  (.D(\HADDR_6[3]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[3]));
    SLE \DATAOUT[0]  (.D(AHB_IF_0_BIF_1_HRDATA[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[0]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[15]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[15]), .Y(\HADDR_6[15]_net_1 ));
    SLE \DATAOUT[14]  (.D(AHB_IF_0_BIF_1_HRDATA[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[14]));
    SLE \DATAOUT[28]  (.D(AHB_IF_0_BIF_1_HRDATA[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[28]));
    SLE \HWDATA[2]  (.D(\HWDATA_int[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[2]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[30]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[30]), .Y(\HADDR_6[30]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[8]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[8]), .Y(\HADDR_6[8]_net_1 ));
    SLE \DATAOUT[3]  (.D(AHB_IF_0_BIF_1_HRDATA[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[3]));
    CFG2 #( .INIT(4'h8) )  \ahb_fsm_current_state_RNO[1]  (.A(
        ahb_fsm_current_state[0]), .B(eSRAM_eNVM_RW_0_WRITE), .Y(
        N_94_i_0));
    SLE \HWDATA_int[16]  (.D(eSRAM_eNVM_RW_0_DATAOUT[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[16]_net_1 ));
    SLE \HADDR[29]  (.D(\HADDR_6[29]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[29]));
    SLE \ahb_fsm_current_state[1]  (.D(N_94_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[1]));
    SLE \HWDATA[3]  (.D(\HWDATA_int[3]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[3]));
    SLE \DATAOUT[30]  (.D(AHB_IF_0_BIF_1_HRDATA[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[30]));
    SLE \HWDATA_int[1]  (.D(eSRAM_eNVM_RW_0_DATAOUT[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[1]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \HADDR[12]  (.D(\HADDR_6[12]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[12]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[14]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[14]), .Y(\HADDR_6[14]_net_1 ));
    SLE \HWDATA[17]  (.D(\HWDATA_int[17]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[17]));
    SLE \DATAOUT[17]  (.D(AHB_IF_0_BIF_1_HRDATA[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[17]));
    SLE \HADDR[28]  (.D(\HADDR_6[28]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[28]));
    SLE \HADDR[13]  (.D(\HADDR_6[13]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[13]));
    SLE \DATAOUT[26]  (.D(AHB_IF_0_BIF_1_HRDATA[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[26]));
    SLE AHB_BUSY (.D(N_541_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .EN(N_55_0), .ALn(eSRAM_eNVM_access_0_HPMS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(AHB_IF_0_AHB_BUSY));
    SLE \ahb_fsm_current_state[4]  (.D(\ahb_fsm_current_state_ns[4] ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[4]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[11]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[11]), .Y(\HADDR_6[11]_net_1 ));
    SLE \HWDATA_int[28]  (.D(eSRAM_eNVM_RW_0_DATAOUT[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[28]_net_1 ));
    SLE \DATAOUT[29]  (.D(AHB_IF_0_BIF_1_HRDATA[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[29]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[12]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[12]), .Y(\HADDR_6[12]_net_1 ));
    CFG3 #( .INIT(8'h80) )  HWDATA_int_0_sqmuxa_0_a3 (.A(
        eSRAM_eNVM_access_0_HPMS_READY), .B(ahb_fsm_current_state[0]), 
        .C(eSRAM_eNVM_RW_0_WRITE), .Y(HWDATA_int_0_sqmuxa));
    SLE \DATAOUT[10]  (.D(AHB_IF_0_BIF_1_HRDATA[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[10]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[2]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[2]), .Y(\HADDR_6[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[20]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[20]), .Y(\HADDR_6[20]_net_1 ));
    SLE \DATAOUT[6]  (.D(AHB_IF_0_BIF_1_HRDATA[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[6]));
    SLE \HWDATA_int[26]  (.D(eSRAM_eNVM_RW_0_DATAOUT[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[26]_net_1 ));
    SLE \HWDATA[27]  (.D(\HWDATA_int[27]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[27]));
    VCC VCC (.Y(VCC_net_1));
    SLE \HWDATA[8]  (.D(\HWDATA_int[8]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[8]));
    SLE \HWDATA_int[5]  (.D(eSRAM_eNVM_RW_0_DATAOUT[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[5]_net_1 ));
    SLE \HWDATA_int[11]  (.D(eSRAM_eNVM_RW_0_DATAOUT[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[11]_net_1 ));
    SLE \HADDR[22]  (.D(\HADDR_6[22]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[22]));
    SLE \HWDATA[18]  (.D(\HWDATA_int[18]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[18]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[31]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[31]), .Y(\HADDR_6[31]_net_1 ));
    SLE \HWDATA[15]  (.D(\HWDATA_int[15]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[15]));
    SLE \HWDATA[14]  (.D(\HWDATA_int[14]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[14]));
    SLE \HADDR[23]  (.D(\HADDR_6[23]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[23]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[25]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[25]), .Y(\HADDR_6[25]_net_1 ));
    SLE \DATAOUT[5]  (.D(AHB_IF_0_BIF_1_HRDATA[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[5]));
    SLE \HWDATA_int[13]  (.D(eSRAM_eNVM_RW_0_DATAOUT[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[13]_net_1 ));
    SLE \HWDATA[4]  (.D(\HWDATA_int[4]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[4]));
    SLE \DATAOUT[7]  (.D(AHB_IF_0_BIF_1_HRDATA[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[7]));
    SLE \HWDATA[7]  (.D(\HWDATA_int[7]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[7]));
    SLE \HWDATA[0]  (.D(\HWDATA_int[0]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[0]));
    SLE \HADDR[15]  (.D(\HADDR_6[15]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[15]));
    SLE \HWDATA[28]  (.D(\HWDATA_int[28]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[28]));
    SLE \HADDR[17]  (.D(\HADDR_6[17]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[17]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[16]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[16]), .Y(\HADDR_6[16]_net_1 ));
    SLE \HWDATA[11]  (.D(\HWDATA_int[11]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[11]));
    SLE \HWDATA[25]  (.D(\HWDATA_int[25]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[25]));
    SLE \DATAOUT[24]  (.D(AHB_IF_0_BIF_1_HRDATA[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[24]));
    SLE \HWDATA_int[10]  (.D(eSRAM_eNVM_RW_0_DATAOUT[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[10]_net_1 ));
    SLE \HADDR[11]  (.D(\HADDR_6[11]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[11]));
    SLE \DATAOUT[31]  (.D(AHB_IF_0_BIF_1_HRDATA[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[31]));
    SLE \HWDATA[24]  (.D(\HWDATA_int[24]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[24]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[24]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[24]), .Y(\HADDR_6[24]_net_1 ));
    SLE \HWDATA_int[21]  (.D(eSRAM_eNVM_RW_0_DATAOUT[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[21]_net_1 ));
    SLE \HWDATA_int[14]  (.D(eSRAM_eNVM_RW_0_DATAOUT[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[14]_net_1 ));
    SLE \HADDR[16]  (.D(\HADDR_6[16]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[16]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[4]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[4]), .Y(\HADDR_6[4]_net_1 ));
    SLE \HTRANS_1[1]  (.D(N_126_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_148_mux_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HTRANS[1]));
    SLE \HWDATA_int[2]  (.D(eSRAM_eNVM_RW_0_DATAOUT[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[2]_net_1 ));
    SLE \HWDATA[31]  (.D(\HWDATA_int[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[31]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[21]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[21]), .Y(\HADDR_6[21]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \ahb_fsm_current_state_ns_a3_0_a3[4]  (.A(
        eSRAM_eNVM_RW_0_WRITE), .B(ahb_fsm_current_state[0]), .C(
        eSRAM_eNVM_RW_0_READ), .Y(\ahb_fsm_current_state_ns[4] ));
    SLE \HWDATA_int[6]  (.D(eSRAM_eNVM_RW_0_DATAOUT[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[6]_net_1 ));
    SLE \HWDATA[13]  (.D(\HWDATA_int[13]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[13]));
    SLE \DATAOUT[15]  (.D(AHB_IF_0_BIF_1_HRDATA[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[15]));
    SLE \HWDATA_int[8]  (.D(eSRAM_eNVM_RW_0_DATAOUT[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[8]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[13]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[13]), .Y(\HADDR_6[13]_net_1 ));
    SLE \HADDR[31]  (.D(\HADDR_6[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[31]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[22]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[22]), .Y(\HADDR_6[22]_net_1 ));
    SLE \HWDATA_int[23]  (.D(eSRAM_eNVM_RW_0_DATAOUT[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[23]_net_1 ));
    SLE \HWDATA[21]  (.D(\HWDATA_int[21]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[21]));
    SLE \DATAOUT[27]  (.D(AHB_IF_0_BIF_1_HRDATA[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[27]));
    SLE \HADDR[5]  (.D(\HADDR_6[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[5]));
    SLE \HADDR[25]  (.D(\HADDR_6[25]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[25]));
    SLE \HWDATA_int[31]  (.D(eSRAM_eNVM_RW_0_DATAOUT[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[31]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[6]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[6]), .Y(\HADDR_6[6]_net_1 ));
    SLE \DATAOUT[4]  (.D(AHB_IF_0_BIF_1_HRDATA[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[4]));
    SLE \HWDATA[16]  (.D(\HWDATA_int[16]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[16]));
    SLE \HADDR[27]  (.D(\HADDR_6[27]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[27]));
    SLE \DATAOUT[11]  (.D(AHB_IF_0_BIF_1_HRDATA[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[11]));
    SLE \DATAOUT[12]  (.D(AHB_IF_0_BIF_1_HRDATA[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[12]));
    SLE \HWDATA_int[3]  (.D(eSRAM_eNVM_RW_0_DATAOUT[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[3]_net_1 ));
    SLE \HADDR[21]  (.D(\HADDR_6[21]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[21]));
    SLE \HWDATA_int[20]  (.D(eSRAM_eNVM_RW_0_DATAOUT[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[20]_net_1 ));
    SLE \HWDATA[1]  (.D(\HWDATA_int[1]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[1]));
    SLE HWRITE (.D(ahb_fsm_current_state[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_147_mux_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWRITE));
    SLE \HADDR[26]  (.D(\HADDR_6[26]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[26]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[9]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[9]), .Y(\HADDR_6[9]_net_1 ));
    SLE \HWDATA[23]  (.D(\HWDATA_int[23]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[23]));
    SLE \DATAOUT[9]  (.D(AHB_IF_0_BIF_1_HRDATA[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[9]));
    SLE \ahb_fsm_current_state[2]  (.D(N_144_mux_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[2]));
    SLE \HWDATA_int[24]  (.D(eSRAM_eNVM_RW_0_DATAOUT[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[24]_net_1 ));
    SLE \DATAOUT[13]  (.D(AHB_IF_0_BIF_1_HRDATA[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[13]));
    SLE \HWDATA_int[15]  (.D(eSRAM_eNVM_RW_0_DATAOUT[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[15]_net_1 ));
    SLE \HADDR[2]  (.D(\HADDR_6[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[2]));
    SLE \DATAOUT[20]  (.D(AHB_IF_0_BIF_1_HRDATA[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[20]));
    SLE \HWDATA_int[17]  (.D(eSRAM_eNVM_RW_0_DATAOUT[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[17]_net_1 ));
    SLE \HADDR[4]  (.D(\HADDR_6[4]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[4]));
    SLE \DATAOUT[18]  (.D(AHB_IF_0_BIF_1_HRDATA[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[18]));
    SLE \HWDATA[12]  (.D(\HWDATA_int[12]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[12]));
    SLE \HWDATA[26]  (.D(\HWDATA_int[26]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[26]));
    SLE \HWDATA_int[30]  (.D(eSRAM_eNVM_RW_0_DATAOUT[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[30]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[19]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[19]), .Y(\HADDR_6[19]_net_1 ));
    SLE \HWDATA_int[4]  (.D(eSRAM_eNVM_RW_0_DATAOUT[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[26]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[26]), .Y(\HADDR_6[26]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[18]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[18]), .Y(\HADDR_6[18]_net_1 ));
    SLE \HWDATA_int[12]  (.D(eSRAM_eNVM_RW_0_DATAOUT[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[17]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[17]), .Y(\HADDR_6[17]_net_1 ));
    SLE \HWDATA[10]  (.D(\HWDATA_int[10]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[10]));
    SLE \HADDR[14]  (.D(\HADDR_6[14]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[14]));
    SLE \HWDATA[19]  (.D(\HWDATA_int[19]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[19]));
    SLE \HADDR[10]  (.D(\HADDR_6[10]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[10]));
    SLE \HWDATA_int[19]  (.D(eSRAM_eNVM_RW_0_DATAOUT[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[19]_net_1 ));
    SLE \HWDATA[22]  (.D(\HWDATA_int[22]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[22]));
    SLE \DATAOUT[16]  (.D(AHB_IF_0_BIF_1_HRDATA[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[16]));
    SLE \HWDATA[30]  (.D(\HWDATA_int[30]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[30]));
    SLE \HWDATA_int[25]  (.D(eSRAM_eNVM_RW_0_DATAOUT[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[25]_net_1 ));
    SLE \HWDATA[6]  (.D(\HWDATA_int[6]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[6]));
    SLE \HWDATA_int[27]  (.D(eSRAM_eNVM_RW_0_DATAOUT[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[27]_net_1 ));
    SLE \DATAOUT[8]  (.D(AHB_IF_0_BIF_1_HRDATA[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[8]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[23]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[23]), .Y(\HADDR_6[23]_net_1 ));
    SLE \DATAOUT[19]  (.D(AHB_IF_0_BIF_1_HRDATA[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[19]));
    SLE \HADDR[30]  (.D(\HADDR_6[30]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[30]));
    SLE \HADDR[7]  (.D(\HADDR_6[7]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[7]));
    SLE \HWDATA[20]  (.D(\HWDATA_int[20]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[20]));
    SLE \HWDATA[29]  (.D(\HWDATA_int[29]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[29]));
    SLE VALID (.D(DATAOUT_1_sqmuxa), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_51_0_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_VALID)
        );
    SLE \ahb_fsm_current_state[0]  (.D(ahb_fsm_current_state_ns_0), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[0]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[7]  (.A(ahb_fsm_current_state[0]), 
        .B(eSRAM_eNVM_RW_0_ADDR[7]), .Y(\HADDR_6[7]_net_1 ));
    SLE \HADDR[24]  (.D(\HADDR_6[24]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[24]));
    SLE \HWDATA[9]  (.D(\HWDATA_int[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[9]));
    SLE \HWDATA_int[22]  (.D(eSRAM_eNVM_RW_0_DATAOUT[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[22]_net_1 ));
    SLE \HADDR[20]  (.D(\HADDR_6[20]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[20]));
    SLE \DATAOUT[25]  (.D(AHB_IF_0_BIF_1_HRDATA[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[25]));
    SLE \ahb_fsm_current_state[6]  (.D(ahb_fsm_current_state[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HREADY_M_iv_i_0), .ALn(
        eSRAM_eNVM_access_0_HPMS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ahb_fsm_current_state[6]));
    
endmodule


module eSRAM_eNVM_access_top(
       RD,
       DEVRST_N,
       start_envm,
       start_esram
    );
output [7:0] RD;
input  DEVRST_N;
input  start_envm;
input  start_esram;

    wire eSRAM_eNVM_access_0_FIC_0_CLK, eSRAM_eNVM_access_0_HPMS_READY, 
        eSRAM_eNVM_RW_0_READ, eSRAM_eNVM_RW_0_WRITE, 
        \eSRAM_eNVM_RW_0_ADDR[2] , \eSRAM_eNVM_RW_0_DATAOUT[0] , 
        \eSRAM_eNVM_RW_0_DATAOUT[1] , \eSRAM_eNVM_RW_0_DATAOUT[2] , 
        \eSRAM_eNVM_RW_0_DATAOUT[3] , \eSRAM_eNVM_RW_0_DATAOUT[4] , 
        \eSRAM_eNVM_RW_0_DATAOUT[5] , \eSRAM_eNVM_RW_0_DATAOUT[6] , 
        \eSRAM_eNVM_RW_0_DATAOUT[7] , \eSRAM_eNVM_RW_0_DATAOUT[8] , 
        \eSRAM_eNVM_RW_0_DATAOUT[9] , \eSRAM_eNVM_RW_0_DATAOUT[10] , 
        \eSRAM_eNVM_RW_0_DATAOUT[11] , \eSRAM_eNVM_RW_0_DATAOUT[12] , 
        \eSRAM_eNVM_RW_0_DATAOUT[13] , \eSRAM_eNVM_RW_0_DATAOUT[14] , 
        \eSRAM_eNVM_RW_0_DATAOUT[15] , \eSRAM_eNVM_RW_0_DATAOUT[16] , 
        \eSRAM_eNVM_RW_0_DATAOUT[17] , \eSRAM_eNVM_RW_0_DATAOUT[18] , 
        \eSRAM_eNVM_RW_0_DATAOUT[19] , \eSRAM_eNVM_RW_0_DATAOUT[20] , 
        \eSRAM_eNVM_RW_0_DATAOUT[21] , \eSRAM_eNVM_RW_0_DATAOUT[22] , 
        \eSRAM_eNVM_RW_0_DATAOUT[23] , \eSRAM_eNVM_RW_0_DATAOUT[24] , 
        \eSRAM_eNVM_RW_0_DATAOUT[25] , \eSRAM_eNVM_RW_0_DATAOUT[26] , 
        \eSRAM_eNVM_RW_0_DATAOUT[27] , \eSRAM_eNVM_RW_0_DATAOUT[28] , 
        \eSRAM_eNVM_RW_0_DATAOUT[29] , \eSRAM_eNVM_RW_0_DATAOUT[30] , 
        \eSRAM_eNVM_RW_0_DATAOUT[31] , GND_net_1, VCC_net_1, 
        \AHB_IF_0_DATAOUT[0] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_BIF_1_HADDR[2] , \AHB_IF_0_BIF_1_HADDR[3] , 
        \AHB_IF_0_BIF_1_HADDR[4] , \AHB_IF_0_BIF_1_HADDR[5] , 
        \AHB_IF_0_BIF_1_HADDR[6] , \AHB_IF_0_BIF_1_HADDR[7] , 
        \AHB_IF_0_BIF_1_HADDR[8] , \AHB_IF_0_BIF_1_HADDR[9] , 
        \AHB_IF_0_BIF_1_HADDR[10] , \AHB_IF_0_BIF_1_HADDR[11] , 
        \AHB_IF_0_BIF_1_HADDR[12] , \AHB_IF_0_BIF_1_HADDR[13] , 
        \AHB_IF_0_BIF_1_HADDR[14] , \AHB_IF_0_BIF_1_HADDR[15] , 
        \AHB_IF_0_BIF_1_HADDR[16] , \AHB_IF_0_BIF_1_HADDR[17] , 
        \AHB_IF_0_BIF_1_HADDR[18] , \AHB_IF_0_BIF_1_HADDR[19] , 
        \AHB_IF_0_BIF_1_HADDR[20] , \AHB_IF_0_BIF_1_HADDR[21] , 
        \AHB_IF_0_BIF_1_HADDR[22] , \AHB_IF_0_BIF_1_HADDR[23] , 
        \AHB_IF_0_BIF_1_HADDR[24] , \AHB_IF_0_BIF_1_HADDR[25] , 
        \AHB_IF_0_BIF_1_HADDR[26] , \AHB_IF_0_BIF_1_HADDR[27] , 
        \AHB_IF_0_BIF_1_HADDR[28] , \AHB_IF_0_BIF_1_HADDR[29] , 
        \AHB_IF_0_BIF_1_HADDR[30] , \AHB_IF_0_BIF_1_HADDR[31] , 
        \AHB_IF_0_BIF_1_HTRANS[1] , AHB_IF_0_BIF_1_HWRITE, 
        \AHB_IF_0_BIF_1_HWDATA[0] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HRDATA[0] , \AHB_IF_0_BIF_1_HRDATA[1] , 
        \AHB_IF_0_BIF_1_HRDATA[2] , \AHB_IF_0_BIF_1_HRDATA[3] , 
        \AHB_IF_0_BIF_1_HRDATA[4] , \AHB_IF_0_BIF_1_HRDATA[5] , 
        \AHB_IF_0_BIF_1_HRDATA[6] , \AHB_IF_0_BIF_1_HRDATA[7] , 
        \AHB_IF_0_BIF_1_HRDATA[8] , \AHB_IF_0_BIF_1_HRDATA[9] , 
        \AHB_IF_0_BIF_1_HRDATA[10] , \AHB_IF_0_BIF_1_HRDATA[11] , 
        \AHB_IF_0_BIF_1_HRDATA[12] , \AHB_IF_0_BIF_1_HRDATA[13] , 
        \AHB_IF_0_BIF_1_HRDATA[14] , \AHB_IF_0_BIF_1_HRDATA[15] , 
        \AHB_IF_0_BIF_1_HRDATA[16] , \AHB_IF_0_BIF_1_HRDATA[17] , 
        \AHB_IF_0_BIF_1_HRDATA[18] , \AHB_IF_0_BIF_1_HRDATA[19] , 
        \AHB_IF_0_BIF_1_HRDATA[20] , \AHB_IF_0_BIF_1_HRDATA[21] , 
        \AHB_IF_0_BIF_1_HRDATA[22] , \AHB_IF_0_BIF_1_HRDATA[23] , 
        \AHB_IF_0_BIF_1_HRDATA[24] , \AHB_IF_0_BIF_1_HRDATA[25] , 
        \AHB_IF_0_BIF_1_HRDATA[26] , \AHB_IF_0_BIF_1_HRDATA[27] , 
        \AHB_IF_0_BIF_1_HRDATA[28] , \AHB_IF_0_BIF_1_HRDATA[29] , 
        \AHB_IF_0_BIF_1_HRDATA[30] , \AHB_IF_0_BIF_1_HRDATA[31] , 
        AHB_IF_0_AHB_BUSY, AHB_IF_0_VALID, eSRAM_eNVM_RW_0_ram_wen, 
        \eSRAM_eNVM_RW_0_ram_waddr[0] , \eSRAM_eNVM_RW_0_ram_waddr[1] , 
        \eSRAM_eNVM_RW_0_ram_waddr[2] , \eSRAM_eNVM_RW_0_ram_waddr[3] , 
        \eSRAM_eNVM_RW_0_ram_waddr[4] , \eSRAM_eNVM_RW_0_ram_wdata[0] , 
        \eSRAM_eNVM_RW_0_ram_wdata[1] , \eSRAM_eNVM_RW_0_ram_wdata[2] , 
        \eSRAM_eNVM_RW_0_ram_wdata[3] , \eSRAM_eNVM_RW_0_ram_wdata[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[5] , \eSRAM_eNVM_RW_0_ram_wdata[6] , 
        \eSRAM_eNVM_RW_0_ram_wdata[7] , \eSRAM_eNVM_RW_0_ram_wdata[8] , 
        \eSRAM_eNVM_RW_0_ram_wdata[9] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \AHB_IF_0.ahb_fsm_current_state[0] , 
        \AHB_IF_0.ahb_fsm_current_state[1] , 
        \AHB_IF_0.ahb_fsm_current_state[2] , 
        \AHB_IF_0.ahb_fsm_current_state[3] , 
        \AHB_IF_0.ahb_fsm_current_state[4] , 
        \AHB_IF_0.ahb_fsm_current_state[5] , 
        \AHB_IF_0.ahb_fsm_current_state[6] , 
        \AHB_IF_0.ahb_fsm_current_state_ns[0] , 
        \AHB_IF_0.HWDATA_1_sqmuxa , \AHB_IF_0.DATAOUT_1_sqmuxa , 
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 , 
        N_55_0, start_envm_c, start_esram_c, \RD_c[0] , \RD_c[1] , 
        \RD_c[2] , \RD_c[3] , \RD_c[4] , \RD_c[5] , \RD_c[6] , 
        \RD_c[7] , \eSRAM_eNVM_RW_0_ADDR[3] , 
        \eSRAM_eNVM_RW_0_ADDR[4] , \eSRAM_eNVM_RW_0_ADDR[5] , 
        \eSRAM_eNVM_RW_0_ADDR[6] , \eSRAM_eNVM_RW_0_ADDR[7] , 
        \eSRAM_eNVM_RW_0_ADDR[8] , \eSRAM_eNVM_RW_0_ADDR[9] , 
        \eSRAM_eNVM_RW_0_ADDR[10] , \eSRAM_eNVM_RW_0_ADDR[11] , 
        \eSRAM_eNVM_RW_0_ADDR[12] , \eSRAM_eNVM_RW_0_ADDR[13] , 
        \eSRAM_eNVM_RW_0_ADDR[14] , \eSRAM_eNVM_RW_0_ADDR[15] , 
        \eSRAM_eNVM_RW_0_ADDR[16] , \eSRAM_eNVM_RW_0_ADDR[17] , 
        \eSRAM_eNVM_RW_0_ADDR[18] , \eSRAM_eNVM_RW_0_ADDR[19] , 
        \eSRAM_eNVM_RW_0_ADDR[20] , \eSRAM_eNVM_RW_0_ADDR[21] , 
        \eSRAM_eNVM_RW_0_ADDR[22] , \eSRAM_eNVM_RW_0_ADDR[23] , 
        \eSRAM_eNVM_RW_0_ADDR[24] , \eSRAM_eNVM_RW_0_ADDR[25] , 
        \eSRAM_eNVM_RW_0_ADDR[26] , \eSRAM_eNVM_RW_0_ADDR[27] , 
        \eSRAM_eNVM_RW_0_ADDR[28] , \eSRAM_eNVM_RW_0_ADDR[29] , 
        \eSRAM_eNVM_RW_0_ADDR[30] , \eSRAM_eNVM_RW_0_ADDR[31] , 
        N_143_mux_i_0, N_144_mux_i_0, N_147_mux_i_0, 
        \AHB_IF_0.N_126_i_0 , N_148_mux_i_0, \AHB_IF_0.N_541_i_0 , 
        N_51_0_i_0, \AHB_IF_0.N_101_i_0 ;
    
    eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM TPSRAM_0 (.RD_c({\RD_c[7] , 
        \RD_c[6] , \RD_c[5] , \RD_c[4] , \RD_c[3] , \RD_c[2] , 
        \RD_c[1] , \RD_c[0] }), .eSRAM_eNVM_RW_0_ram_wdata({
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[9] , \eSRAM_eNVM_RW_0_ram_wdata[8] , 
        \eSRAM_eNVM_RW_0_ram_wdata[7] , \eSRAM_eNVM_RW_0_ram_wdata[6] , 
        \eSRAM_eNVM_RW_0_ram_wdata[5] , \eSRAM_eNVM_RW_0_ram_wdata[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[3] , \eSRAM_eNVM_RW_0_ram_wdata[2] , 
        \eSRAM_eNVM_RW_0_ram_wdata[1] , \eSRAM_eNVM_RW_0_ram_wdata[0] })
        , .eSRAM_eNVM_RW_0_ram_waddr({\eSRAM_eNVM_RW_0_ram_waddr[4] , 
        \eSRAM_eNVM_RW_0_ram_waddr[3] , \eSRAM_eNVM_RW_0_ram_waddr[2] , 
        \eSRAM_eNVM_RW_0_ram_waddr[1] , \eSRAM_eNVM_RW_0_ram_waddr[0] })
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .eSRAM_eNVM_RW_0_ram_wen(eSRAM_eNVM_RW_0_ram_wen));
    INBUF start_esram_ibuf (.PAD(start_esram), .Y(start_esram_c));
    OUTBUF \RD_obuf[2]  (.D(\RD_c[2] ), .PAD(RD[2]));
    eSRAM_eNVM_access eSRAM_eNVM_access_0 (.AHB_IF_0_BIF_1_HADDR({
        \AHB_IF_0_BIF_1_HADDR[31] , \AHB_IF_0_BIF_1_HADDR[30] , 
        \AHB_IF_0_BIF_1_HADDR[29] , \AHB_IF_0_BIF_1_HADDR[28] , 
        \AHB_IF_0_BIF_1_HADDR[27] , \AHB_IF_0_BIF_1_HADDR[26] , 
        \AHB_IF_0_BIF_1_HADDR[25] , \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[23] , \AHB_IF_0_BIF_1_HADDR[22] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[12] , 
        \AHB_IF_0_BIF_1_HADDR[11] , \AHB_IF_0_BIF_1_HADDR[10] , 
        \AHB_IF_0_BIF_1_HADDR[9] , \AHB_IF_0_BIF_1_HADDR[8] , 
        \AHB_IF_0_BIF_1_HADDR[7] , \AHB_IF_0_BIF_1_HADDR[6] , 
        \AHB_IF_0_BIF_1_HADDR[5] , \AHB_IF_0_BIF_1_HADDR[4] , 
        \AHB_IF_0_BIF_1_HADDR[3] , \AHB_IF_0_BIF_1_HADDR[2] }), 
        .AHB_IF_0_BIF_1_HTRANS({\AHB_IF_0_BIF_1_HTRANS[1] }), 
        .ahb_fsm_current_state({\AHB_IF_0.ahb_fsm_current_state[6] , 
        \AHB_IF_0.ahb_fsm_current_state[5] , 
        \AHB_IF_0.ahb_fsm_current_state[4] , 
        \AHB_IF_0.ahb_fsm_current_state[3] , 
        \AHB_IF_0.ahb_fsm_current_state[2] , 
        \AHB_IF_0.ahb_fsm_current_state[1] , 
        \AHB_IF_0.ahb_fsm_current_state[0] }), 
        .ahb_fsm_current_state_ns({
        \AHB_IF_0.ahb_fsm_current_state_ns[0] }), 
        .AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .AHB_IF_0_BIF_1_HRDATA({
        \AHB_IF_0_BIF_1_HRDATA[31] , \AHB_IF_0_BIF_1_HRDATA[30] , 
        \AHB_IF_0_BIF_1_HRDATA[29] , \AHB_IF_0_BIF_1_HRDATA[28] , 
        \AHB_IF_0_BIF_1_HRDATA[27] , \AHB_IF_0_BIF_1_HRDATA[26] , 
        \AHB_IF_0_BIF_1_HRDATA[25] , \AHB_IF_0_BIF_1_HRDATA[24] , 
        \AHB_IF_0_BIF_1_HRDATA[23] , \AHB_IF_0_BIF_1_HRDATA[22] , 
        \AHB_IF_0_BIF_1_HRDATA[21] , \AHB_IF_0_BIF_1_HRDATA[20] , 
        \AHB_IF_0_BIF_1_HRDATA[19] , \AHB_IF_0_BIF_1_HRDATA[18] , 
        \AHB_IF_0_BIF_1_HRDATA[17] , \AHB_IF_0_BIF_1_HRDATA[16] , 
        \AHB_IF_0_BIF_1_HRDATA[15] , \AHB_IF_0_BIF_1_HRDATA[14] , 
        \AHB_IF_0_BIF_1_HRDATA[13] , \AHB_IF_0_BIF_1_HRDATA[12] , 
        \AHB_IF_0_BIF_1_HRDATA[11] , \AHB_IF_0_BIF_1_HRDATA[10] , 
        \AHB_IF_0_BIF_1_HRDATA[9] , \AHB_IF_0_BIF_1_HRDATA[8] , 
        \AHB_IF_0_BIF_1_HRDATA[7] , \AHB_IF_0_BIF_1_HRDATA[6] , 
        \AHB_IF_0_BIF_1_HRDATA[5] , \AHB_IF_0_BIF_1_HRDATA[4] , 
        \AHB_IF_0_BIF_1_HRDATA[3] , \AHB_IF_0_BIF_1_HRDATA[2] , 
        \AHB_IF_0_BIF_1_HRDATA[1] , \AHB_IF_0_BIF_1_HRDATA[0] }), 
        .DEVRST_N(DEVRST_N), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), 
        .HREADY_M_iv_i_0(
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 )
        , .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE), 
        .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ), .N_55_0(N_55_0), 
        .N_51_0_i_0(N_51_0_i_0), .HWDATA_1_sqmuxa(
        \AHB_IF_0.HWDATA_1_sqmuxa ), .N_147_mux_i_0(N_147_mux_i_0), 
        .N_101_i_0(\AHB_IF_0.N_101_i_0 ), .DATAOUT_1_sqmuxa(
        \AHB_IF_0.DATAOUT_1_sqmuxa ), .N_541_i_0(\AHB_IF_0.N_541_i_0 ), 
        .N_143_mux_i_0(N_143_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), 
        .N_148_mux_i_0(N_148_mux_i_0), .N_126_i_0(\AHB_IF_0.N_126_i_0 )
        );
    INBUF start_envm_ibuf (.PAD(start_envm), .Y(start_envm_c));
    OUTBUF \RD_obuf[7]  (.D(\RD_c[7] ), .PAD(RD[7]));
    GND GND (.Y(GND_net_1));
    OUTBUF \RD_obuf[6]  (.D(\RD_c[6] ), .PAD(RD[6]));
    OUTBUF \RD_obuf[0]  (.D(\RD_c[0] ), .PAD(RD[0]));
    eSRAM_eNVM_RW eSRAM_eNVM_RW_0 (.eSRAM_eNVM_RW_0_ram_waddr({
        \eSRAM_eNVM_RW_0_ram_waddr[4] , \eSRAM_eNVM_RW_0_ram_waddr[3] , 
        \eSRAM_eNVM_RW_0_ram_waddr[2] , \eSRAM_eNVM_RW_0_ram_waddr[1] , 
        \eSRAM_eNVM_RW_0_ram_waddr[0] }), .eSRAM_eNVM_RW_0_ram_wdata({
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[9] , \eSRAM_eNVM_RW_0_ram_wdata[8] , 
        \eSRAM_eNVM_RW_0_ram_wdata[7] , \eSRAM_eNVM_RW_0_ram_wdata[6] , 
        \eSRAM_eNVM_RW_0_ram_wdata[5] , \eSRAM_eNVM_RW_0_ram_wdata[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[3] , \eSRAM_eNVM_RW_0_ram_wdata[2] , 
        \eSRAM_eNVM_RW_0_ram_wdata[1] , \eSRAM_eNVM_RW_0_ram_wdata[0] })
        , .AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[0] }), .eSRAM_eNVM_RW_0_ADDR({
        \eSRAM_eNVM_RW_0_ADDR[31] , \eSRAM_eNVM_RW_0_ADDR[30] , 
        \eSRAM_eNVM_RW_0_ADDR[29] , \eSRAM_eNVM_RW_0_ADDR[28] , 
        \eSRAM_eNVM_RW_0_ADDR[27] , \eSRAM_eNVM_RW_0_ADDR[26] , 
        \eSRAM_eNVM_RW_0_ADDR[25] , \eSRAM_eNVM_RW_0_ADDR[24] , 
        \eSRAM_eNVM_RW_0_ADDR[23] , \eSRAM_eNVM_RW_0_ADDR[22] , 
        \eSRAM_eNVM_RW_0_ADDR[21] , \eSRAM_eNVM_RW_0_ADDR[20] , 
        \eSRAM_eNVM_RW_0_ADDR[19] , \eSRAM_eNVM_RW_0_ADDR[18] , 
        \eSRAM_eNVM_RW_0_ADDR[17] , \eSRAM_eNVM_RW_0_ADDR[16] , 
        \eSRAM_eNVM_RW_0_ADDR[15] , \eSRAM_eNVM_RW_0_ADDR[14] , 
        \eSRAM_eNVM_RW_0_ADDR[13] , \eSRAM_eNVM_RW_0_ADDR[12] , 
        \eSRAM_eNVM_RW_0_ADDR[11] , \eSRAM_eNVM_RW_0_ADDR[10] , 
        \eSRAM_eNVM_RW_0_ADDR[9] , \eSRAM_eNVM_RW_0_ADDR[8] , 
        \eSRAM_eNVM_RW_0_ADDR[7] , \eSRAM_eNVM_RW_0_ADDR[6] , 
        \eSRAM_eNVM_RW_0_ADDR[5] , \eSRAM_eNVM_RW_0_ADDR[4] , 
        \eSRAM_eNVM_RW_0_ADDR[3] , \eSRAM_eNVM_RW_0_ADDR[2] }), 
        .eSRAM_eNVM_RW_0_DATAOUT({\eSRAM_eNVM_RW_0_DATAOUT[31] , 
        \eSRAM_eNVM_RW_0_DATAOUT[30] , \eSRAM_eNVM_RW_0_DATAOUT[29] , 
        \eSRAM_eNVM_RW_0_DATAOUT[28] , \eSRAM_eNVM_RW_0_DATAOUT[27] , 
        \eSRAM_eNVM_RW_0_DATAOUT[26] , \eSRAM_eNVM_RW_0_DATAOUT[25] , 
        \eSRAM_eNVM_RW_0_DATAOUT[24] , \eSRAM_eNVM_RW_0_DATAOUT[23] , 
        \eSRAM_eNVM_RW_0_DATAOUT[22] , \eSRAM_eNVM_RW_0_DATAOUT[21] , 
        \eSRAM_eNVM_RW_0_DATAOUT[20] , \eSRAM_eNVM_RW_0_DATAOUT[19] , 
        \eSRAM_eNVM_RW_0_DATAOUT[18] , \eSRAM_eNVM_RW_0_DATAOUT[17] , 
        \eSRAM_eNVM_RW_0_DATAOUT[16] , \eSRAM_eNVM_RW_0_DATAOUT[15] , 
        \eSRAM_eNVM_RW_0_DATAOUT[14] , \eSRAM_eNVM_RW_0_DATAOUT[13] , 
        \eSRAM_eNVM_RW_0_DATAOUT[12] , \eSRAM_eNVM_RW_0_DATAOUT[11] , 
        \eSRAM_eNVM_RW_0_DATAOUT[10] , \eSRAM_eNVM_RW_0_DATAOUT[9] , 
        \eSRAM_eNVM_RW_0_DATAOUT[8] , \eSRAM_eNVM_RW_0_DATAOUT[7] , 
        \eSRAM_eNVM_RW_0_DATAOUT[6] , \eSRAM_eNVM_RW_0_DATAOUT[5] , 
        \eSRAM_eNVM_RW_0_DATAOUT[4] , \eSRAM_eNVM_RW_0_DATAOUT[3] , 
        \eSRAM_eNVM_RW_0_DATAOUT[2] , \eSRAM_eNVM_RW_0_DATAOUT[1] , 
        \eSRAM_eNVM_RW_0_DATAOUT[0] }), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE), 
        .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ), 
        .eSRAM_eNVM_RW_0_ram_wen(eSRAM_eNVM_RW_0_ram_wen), 
        .start_envm_c(start_envm_c), .start_esram_c(start_esram_c), 
        .AHB_IF_0_VALID(AHB_IF_0_VALID), .AHB_IF_0_AHB_BUSY(
        AHB_IF_0_AHB_BUSY));
    VCC VCC (.Y(VCC_net_1));
    OUTBUF \RD_obuf[5]  (.D(\RD_c[5] ), .PAD(RD[5]));
    AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1 
        AHB_IF_0 (.eSRAM_eNVM_RW_0_DATAOUT({
        \eSRAM_eNVM_RW_0_DATAOUT[31] , \eSRAM_eNVM_RW_0_DATAOUT[30] , 
        \eSRAM_eNVM_RW_0_DATAOUT[29] , \eSRAM_eNVM_RW_0_DATAOUT[28] , 
        \eSRAM_eNVM_RW_0_DATAOUT[27] , \eSRAM_eNVM_RW_0_DATAOUT[26] , 
        \eSRAM_eNVM_RW_0_DATAOUT[25] , \eSRAM_eNVM_RW_0_DATAOUT[24] , 
        \eSRAM_eNVM_RW_0_DATAOUT[23] , \eSRAM_eNVM_RW_0_DATAOUT[22] , 
        \eSRAM_eNVM_RW_0_DATAOUT[21] , \eSRAM_eNVM_RW_0_DATAOUT[20] , 
        \eSRAM_eNVM_RW_0_DATAOUT[19] , \eSRAM_eNVM_RW_0_DATAOUT[18] , 
        \eSRAM_eNVM_RW_0_DATAOUT[17] , \eSRAM_eNVM_RW_0_DATAOUT[16] , 
        \eSRAM_eNVM_RW_0_DATAOUT[15] , \eSRAM_eNVM_RW_0_DATAOUT[14] , 
        \eSRAM_eNVM_RW_0_DATAOUT[13] , \eSRAM_eNVM_RW_0_DATAOUT[12] , 
        \eSRAM_eNVM_RW_0_DATAOUT[11] , \eSRAM_eNVM_RW_0_DATAOUT[10] , 
        \eSRAM_eNVM_RW_0_DATAOUT[9] , \eSRAM_eNVM_RW_0_DATAOUT[8] , 
        \eSRAM_eNVM_RW_0_DATAOUT[7] , \eSRAM_eNVM_RW_0_DATAOUT[6] , 
        \eSRAM_eNVM_RW_0_DATAOUT[5] , \eSRAM_eNVM_RW_0_DATAOUT[4] , 
        \eSRAM_eNVM_RW_0_DATAOUT[3] , \eSRAM_eNVM_RW_0_DATAOUT[2] , 
        \eSRAM_eNVM_RW_0_DATAOUT[1] , \eSRAM_eNVM_RW_0_DATAOUT[0] }), 
        .AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[0] }), .AHB_IF_0_BIF_1_HRDATA({
        \AHB_IF_0_BIF_1_HRDATA[31] , \AHB_IF_0_BIF_1_HRDATA[30] , 
        \AHB_IF_0_BIF_1_HRDATA[29] , \AHB_IF_0_BIF_1_HRDATA[28] , 
        \AHB_IF_0_BIF_1_HRDATA[27] , \AHB_IF_0_BIF_1_HRDATA[26] , 
        \AHB_IF_0_BIF_1_HRDATA[25] , \AHB_IF_0_BIF_1_HRDATA[24] , 
        \AHB_IF_0_BIF_1_HRDATA[23] , \AHB_IF_0_BIF_1_HRDATA[22] , 
        \AHB_IF_0_BIF_1_HRDATA[21] , \AHB_IF_0_BIF_1_HRDATA[20] , 
        \AHB_IF_0_BIF_1_HRDATA[19] , \AHB_IF_0_BIF_1_HRDATA[18] , 
        \AHB_IF_0_BIF_1_HRDATA[17] , \AHB_IF_0_BIF_1_HRDATA[16] , 
        \AHB_IF_0_BIF_1_HRDATA[15] , \AHB_IF_0_BIF_1_HRDATA[14] , 
        \AHB_IF_0_BIF_1_HRDATA[13] , \AHB_IF_0_BIF_1_HRDATA[12] , 
        \AHB_IF_0_BIF_1_HRDATA[11] , \AHB_IF_0_BIF_1_HRDATA[10] , 
        \AHB_IF_0_BIF_1_HRDATA[9] , \AHB_IF_0_BIF_1_HRDATA[8] , 
        \AHB_IF_0_BIF_1_HRDATA[7] , \AHB_IF_0_BIF_1_HRDATA[6] , 
        \AHB_IF_0_BIF_1_HRDATA[5] , \AHB_IF_0_BIF_1_HRDATA[4] , 
        \AHB_IF_0_BIF_1_HRDATA[3] , \AHB_IF_0_BIF_1_HRDATA[2] , 
        \AHB_IF_0_BIF_1_HRDATA[1] , \AHB_IF_0_BIF_1_HRDATA[0] }), 
        .AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .AHB_IF_0_BIF_1_HADDR({
        \AHB_IF_0_BIF_1_HADDR[31] , \AHB_IF_0_BIF_1_HADDR[30] , 
        \AHB_IF_0_BIF_1_HADDR[29] , \AHB_IF_0_BIF_1_HADDR[28] , 
        \AHB_IF_0_BIF_1_HADDR[27] , \AHB_IF_0_BIF_1_HADDR[26] , 
        \AHB_IF_0_BIF_1_HADDR[25] , \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[23] , \AHB_IF_0_BIF_1_HADDR[22] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[12] , 
        \AHB_IF_0_BIF_1_HADDR[11] , \AHB_IF_0_BIF_1_HADDR[10] , 
        \AHB_IF_0_BIF_1_HADDR[9] , \AHB_IF_0_BIF_1_HADDR[8] , 
        \AHB_IF_0_BIF_1_HADDR[7] , \AHB_IF_0_BIF_1_HADDR[6] , 
        \AHB_IF_0_BIF_1_HADDR[5] , \AHB_IF_0_BIF_1_HADDR[4] , 
        \AHB_IF_0_BIF_1_HADDR[3] , \AHB_IF_0_BIF_1_HADDR[2] }), 
        .AHB_IF_0_BIF_1_HTRANS({\AHB_IF_0_BIF_1_HTRANS[1] }), 
        .ahb_fsm_current_state({\AHB_IF_0.ahb_fsm_current_state[6] , 
        \AHB_IF_0.ahb_fsm_current_state[5] , 
        \AHB_IF_0.ahb_fsm_current_state[4] , 
        \AHB_IF_0.ahb_fsm_current_state[3] , 
        \AHB_IF_0.ahb_fsm_current_state[2] , 
        \AHB_IF_0.ahb_fsm_current_state[1] , 
        \AHB_IF_0.ahb_fsm_current_state[0] }), .eSRAM_eNVM_RW_0_ADDR({
        \eSRAM_eNVM_RW_0_ADDR[31] , \eSRAM_eNVM_RW_0_ADDR[30] , 
        \eSRAM_eNVM_RW_0_ADDR[29] , \eSRAM_eNVM_RW_0_ADDR[28] , 
        \eSRAM_eNVM_RW_0_ADDR[27] , \eSRAM_eNVM_RW_0_ADDR[26] , 
        \eSRAM_eNVM_RW_0_ADDR[25] , \eSRAM_eNVM_RW_0_ADDR[24] , 
        \eSRAM_eNVM_RW_0_ADDR[23] , \eSRAM_eNVM_RW_0_ADDR[22] , 
        \eSRAM_eNVM_RW_0_ADDR[21] , \eSRAM_eNVM_RW_0_ADDR[20] , 
        \eSRAM_eNVM_RW_0_ADDR[19] , \eSRAM_eNVM_RW_0_ADDR[18] , 
        \eSRAM_eNVM_RW_0_ADDR[17] , \eSRAM_eNVM_RW_0_ADDR[16] , 
        \eSRAM_eNVM_RW_0_ADDR[15] , \eSRAM_eNVM_RW_0_ADDR[14] , 
        \eSRAM_eNVM_RW_0_ADDR[13] , \eSRAM_eNVM_RW_0_ADDR[12] , 
        \eSRAM_eNVM_RW_0_ADDR[11] , \eSRAM_eNVM_RW_0_ADDR[10] , 
        \eSRAM_eNVM_RW_0_ADDR[9] , \eSRAM_eNVM_RW_0_ADDR[8] , 
        \eSRAM_eNVM_RW_0_ADDR[7] , \eSRAM_eNVM_RW_0_ADDR[6] , 
        \eSRAM_eNVM_RW_0_ADDR[5] , \eSRAM_eNVM_RW_0_ADDR[4] , 
        \eSRAM_eNVM_RW_0_ADDR[3] , \eSRAM_eNVM_RW_0_ADDR[2] }), 
        .ahb_fsm_current_state_ns_0(
        \AHB_IF_0.ahb_fsm_current_state_ns[0] ), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .eSRAM_eNVM_access_0_HPMS_READY(eSRAM_eNVM_access_0_HPMS_READY)
        , .DATAOUT_1_sqmuxa(\AHB_IF_0.DATAOUT_1_sqmuxa ), 
        .HWDATA_1_sqmuxa(\AHB_IF_0.HWDATA_1_sqmuxa ), .N_101_i_0(
        \AHB_IF_0.N_101_i_0 ), .AHB_IF_0_VALID(AHB_IF_0_VALID), 
        .N_51_0_i_0(N_51_0_i_0), .AHB_IF_0_AHB_BUSY(AHB_IF_0_AHB_BUSY), 
        .N_541_i_0(\AHB_IF_0.N_541_i_0 ), .N_55_0(N_55_0), .N_126_i_0(
        \AHB_IF_0.N_126_i_0 ), .N_148_mux_i_0(N_148_mux_i_0), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), .N_147_mux_i_0(
        N_147_mux_i_0), .N_144_mux_i_0(N_144_mux_i_0), 
        .HREADY_M_iv_i_0(
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 )
        , .N_143_mux_i_0(N_143_mux_i_0), .eSRAM_eNVM_RW_0_WRITE(
        eSRAM_eNVM_RW_0_WRITE), .eSRAM_eNVM_RW_0_READ(
        eSRAM_eNVM_RW_0_READ));
    OUTBUF \RD_obuf[4]  (.D(\RD_c[4] ), .PAD(RD[4]));
    OUTBUF \RD_obuf[3]  (.D(\RD_c[3] ), .PAD(RD[3]));
    OUTBUF \RD_obuf[1]  (.D(\RD_c[1] ), .PAD(RD[1]));
    
endmodule
