[Library]
others = $MODEL_TECH/../modelsim.ini
SmartFusion2 = C:/Microsemi/Libero_SoC_v11.7/Designer/lib/modelsim/precompiled/vlog/SmartFusion2



presynth = presynth
COREAHBLITE_LIB = ../component/Actel/DirectCore/CoreAHBLite/5.2.100/mti/user_vlog/COREAHBLITE_LIB














syncad_vhdl_lib = C:\Microsemi\Libero_SoC_v11.7\Designer/lib/actel/syncad_vhdl_lib

[vcom]
VHDL93 = 1

[vsim]
IterationLimit = 5000
