@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net eSRAM_eNVM_access_0_MSS_READY on CLKINT  I_35 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
