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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Fri Feb 19 16:22:28 2016
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>eSRAM_eNVM_access_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\SF2\synthesis\eSRAM_eNVM_access_top.edn</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\SF2\constraint\io\eSRAM_eNVM_access_top.root_0.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>449</cell>
 <cell>86184</cell>
 <cell>0.52</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>364</cell>
 <cell>86184</cell>
 <cell>0.42</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>795</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>10</cell>
 <cell>265</cell>
 <cell>3.77</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>10</cell>
 <cell>265</cell>
 <cell>3.77</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>0</cell>
 <cell>132</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>112</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>1</cell>
 <cell>109</cell>
 <cell>0.92</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>84</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>2</cell>
 <cell>16</cell>
 <cell>12.50</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>6</cell>
 <cell>16.67</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>4</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>413</cell>
 <cell>328</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>36</cell>
 <cell>36</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>449</cell>
 <cell>364</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (512KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>30</cell>
 <cell>1</cell>
</row>
<row>
 <cell>33</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>2</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>2</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>8</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 2</cell>
 <cell> 8</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 10</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>331</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0_FIC_0_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>225</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0_MSS_READY</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>38</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/ahb_fsm_current_state[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/ahb_fsm_current_state[0]</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/m0s16DataSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/defSlaveSMNextState_0_o2</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_0_o2</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[0]</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/DATAOUT_1_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/un18_0_0_a2</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/HWDATA_1_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/un1_ahb_fsm_current_state_4_0_0_a2</cell>
</row>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_RW_0/N_204_i_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_RW_0/ram_wdata_0_sqmuxa_i_0_a3_5_RNID0JJ2</cell>
</row>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_RW_0/N_45_i_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_RW_0/current_state_RNIACPO5[4]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>38</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/ahb_fsm_current_state[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/ahb_fsm_current_state[0]</cell>
</row>
<row>
 <cell>35</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/m0s16DataSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[16]</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/defSlaveSMNextState_0_o2</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_0_o2</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_0_a2[0]</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterDataInProg[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/slavestage_16/masterDataInProg[0]</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/DATAOUT_1_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/un18_0_0_a2</cell>
</row>
<row>
 <cell>33</cell>
 <cell>INT_NET</cell>
 <cell>Net   : AHB_IF_0/HWDATA_1_sqmuxa</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: AHB_IF_0/un1_ahb_fsm_current_state_4_0_0_a2</cell>
</row>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_RW_0/N_204_i_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_RW_0/ram_wdata_0_sqmuxa_i_0_a3_5_RNID0JJ2</cell>
</row>
<row>
 <cell>32</cell>
 <cell>INT_NET</cell>
 <cell>Net   : eSRAM_eNVM_RW_0/N_45_i_0</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: eSRAM_eNVM_RW_0/current_state_RNIACPO5[4]</cell>
</row>
</table>
</doc>
