<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.7.0.119</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Fri Feb 19 17:19:33 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>eSRAM_eNVM_access_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>5.361</cell>
 <cell>186.532</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>0.747</cell>
 <cell>0.189</cell>
 <cell>8.245</cell>
 <cell>14.484</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:EN</cell>
 <cell>4.742</cell>
 <cell>4.672</cell>
 <cell>10.143</cell>
 <cell>14.815</cell>
 <cell>0.335</cell>
 <cell>5.328</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[26]:EN</cell>
 <cell>4.742</cell>
 <cell>4.672</cell>
 <cell>10.143</cell>
 <cell>14.815</cell>
 <cell>0.335</cell>
 <cell>5.328</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[20]:EN</cell>
 <cell>4.742</cell>
 <cell>4.672</cell>
 <cell>10.143</cell>
 <cell>14.815</cell>
 <cell>0.335</cell>
 <cell>5.328</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[9]:EN</cell>
 <cell>4.742</cell>
 <cell>4.672</cell>
 <cell>10.143</cell>
 <cell>14.815</cell>
 <cell>0.335</cell>
 <cell>5.328</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[8]:EN</cell>
 <cell>4.743</cell>
 <cell>4.681</cell>
 <cell>10.144</cell>
 <cell>14.825</cell>
 <cell>0.335</cell>
 <cell>5.319</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.815</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.143</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.672</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>3.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>3.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>3.775</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>4.378</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>4.694</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>5.101</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>5.310</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.091</cell>
 <cell>5.401</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/eSRAM_eNVM_access_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_READYOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>1.714</cell>
 <cell>7.115</cell>
 <cell>7</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_iv_0_o2_0_o2:B</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0_AHBmslave16_HREADY</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.058</cell>
 <cell>8.173</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/HREADY_M_iv_0_o2_0_o2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>8.260</cell>
 <cell>13</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2:A</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0_CoreAHBLite_0_matrix4x16_masterstage_0_HREADY_M_iv</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.649</cell>
 <cell>8.909</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable_0_a2:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>8.996</cell>
 <cell>31</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:EN</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterAddrClockEnable</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.147</cell>
 <cell>10.143</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.143</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>13.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>13.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>13.775</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB10:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.595</cell>
 <cell>14.370</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB10:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>14.686</cell>
 <cell>29</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:CLK</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB10_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.464</cell>
 <cell>15.150</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>14.815</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.815</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>start_envm</cell>
 <cell>eSRAM_eNVM_RW_0/start_envm_reg:D</cell>
 <cell>5.544</cell>
 <cell></cell>
 <cell>5.544</cell>
 <cell></cell>
 <cell>0.174</cell>
 <cell>0.747</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>start_esram</cell>
 <cell>eSRAM_eNVM_RW_0/start_esram_reg:D</cell>
 <cell>5.353</cell>
 <cell></cell>
 <cell>5.353</cell>
 <cell></cell>
 <cell>0.174</cell>
 <cell>0.550</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: start_envm</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: eSRAM_eNVM_RW_0/start_envm_reg:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.544</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>start_envm</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>start_envm_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>start_envm</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>start_envm_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.544</cell>
 <cell>2.544</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>start_envm_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>start_envm_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.544</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>start_envm_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.090</cell>
 <cell>2.634</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_RW_0/start_envm_reg:D</cell>
 <cell>net</cell>
 <cell>start_envm_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.910</cell>
 <cell>5.544</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.544</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.155</cell>
 <cell>N/C</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.522</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>N/C</cell>
 <cell>52</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_RW_0/start_envm_reg:CLK</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.448</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_RW_0/start_envm_reg:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.174</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>RD[1]</cell>
 <cell>9.163</cell>
 <cell></cell>
 <cell>14.484</cell>
 <cell></cell>
 <cell>14.484</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>RD[0]</cell>
 <cell>9.142</cell>
 <cell></cell>
 <cell>14.463</cell>
 <cell></cell>
 <cell>14.463</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>RD[3]</cell>
 <cell>8.933</cell>
 <cell></cell>
 <cell>14.254</cell>
 <cell></cell>
 <cell>14.254</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>RD[7]</cell>
 <cell>8.876</cell>
 <cell></cell>
 <cell>14.197</cell>
 <cell></cell>
 <cell>14.197</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>RD[2]</cell>
 <cell>8.846</cell>
 <cell></cell>
 <cell>14.167</cell>
 <cell></cell>
 <cell>14.167</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: RD[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>14.484</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>3.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>3.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>3.775</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>4.378</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>4.694</cell>
 <cell>22</cell>
 <cell>r</cell>
</row>
<row>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/FF_0:CLK</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.491</cell>
 <cell>5.185</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/FF_0:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.059</cell>
 <cell>5.244</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:A_CLK</cell>
 <cell>net</cell>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/A_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.077</cell>
 <cell>5.321</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>TPSRAM_0/eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0/INST_RAM1K18_IP:B_DOUT[1]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>+</cell>
 <cell>2.208</cell>
 <cell>7.529</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>RD_obuf[1]/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>RD_c[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.910</cell>
 <cell>11.439</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>RD_obuf[1]/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>11.782</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>RD_obuf[1]/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>RD_obuf[1]/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>11.782</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>RD_obuf[1]/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.702</cell>
 <cell>14.484</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>RD[1]</cell>
 <cell>net</cell>
 <cell>RD[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>14.484</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.484</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>RD[1]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>AHB_IF_0/HWDATA[14]:ALn</cell>
 <cell>4.962</cell>
 <cell>4.639</cell>
 <cell>10.163</cell>
 <cell>14.802</cell>
 <cell>0.353</cell>
 <cell>5.361</cell>
 <cell>0.046</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>AHB_IF_0/HWDATA[22]:ALn</cell>
 <cell>4.962</cell>
 <cell>4.639</cell>
 <cell>10.163</cell>
 <cell>14.802</cell>
 <cell>0.353</cell>
 <cell>5.361</cell>
 <cell>0.046</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>AHB_IF_0/HWDATA[2]:ALn</cell>
 <cell>4.961</cell>
 <cell>4.640</cell>
 <cell>10.162</cell>
 <cell>14.802</cell>
 <cell>0.353</cell>
 <cell>5.360</cell>
 <cell>0.046</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>AHB_IF_0/HWDATA[30]:ALn</cell>
 <cell>4.961</cell>
 <cell>4.640</cell>
 <cell>10.162</cell>
 <cell>14.802</cell>
 <cell>0.353</cell>
 <cell>5.360</cell>
 <cell>0.046</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>eSRAM_eNVM_RW_0/data[17]:ALn</cell>
 <cell>4.960</cell>
 <cell>4.640</cell>
 <cell>10.161</cell>
 <cell>14.801</cell>
 <cell>0.353</cell>
 <cell>5.360</cell>
 <cell>0.047</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AHB_IF_0/HWDATA[14]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.802</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.163</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.639</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>3.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>3.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>3.775</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.597</cell>
 <cell>4.372</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>4.688</cell>
 <cell>13</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.513</cell>
 <cell>5.201</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>5.288</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.014</cell>
 <cell>8.302</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>8.676</cell>
 <cell>11</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.600</cell>
 <cell>9.276</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>9.592</cell>
 <cell>39</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HWDATA[14]:ALn</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CORERESETP_0/MSS_HPMS_READY_int_RNISI68/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.571</cell>
 <cell>10.163</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.163</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.398</cell>
 <cell>13.398</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>13.597</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>13.775</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.600</cell>
 <cell>14.375</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>14.691</cell>
 <cell>52</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HWDATA[14]:CLK</cell>
 <cell>net</cell>
 <cell>eSRAM_eNVM_access_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.464</cell>
 <cell>15.155</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HWDATA[14]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>14.802</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.802</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain eSRAM_eNVM_access_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
