`

    #Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
    #install: C:\Microsemi\Libero_SoC_v11.7\Synplify
    #OS: Windows 7 6.1
    #Hostname: W764-KUMARJ

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\igloo2.v"
    @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v"
    @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v"
    @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v"
    @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\hdl\AHB_IF.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\hdl\eSRAM_eNVM_RW.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access\CCC_0\eSRAM_eNVM_access_CCC_0_FCCC.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\SgCore\OSC\2.0.101\osc_comps.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS_syn.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access\eSRAM_eNVM_access.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_top\TPSRAM_0\eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM.v"
    @I::"E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_top\eSRAM_eNVM_access_top.v"
    Verilog syntax check successful!
    File E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\hdl\AHB_IF.v changed - recompiling
    File E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\hdl\eSRAM_eNVM_RW.v changed - recompiling
    File E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_top\TPSRAM_0\eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM.v changed - recompiling
    File E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\component\work\eSRAM_eNVM_access_top\eSRAM_eNVM_access_top.v changed - recompiling
    Selecting top level module eSRAM_eNVM_access_top
    @N:CG364 : AHB_IF.v(21) | Synthesizing module AHB_IF

    	Idle_1=3'b000
    	Write_FIC_0=3'b001
    	Write_FIC_1=3'b010
    	Write_FIC_2=3'b011
    	Read_FIC_0=3'b100
    	Read_FIC_1=3'b101
    	Read_FIC_2=3'b110
    	Data_size=5'b00000
       Generated name = AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1

    @W:CG360 : AHB_IF.v(60) | No assignment to wire HSIZE_int

    @A:CL282 : AHB_IF.v(81) | Feedback mux created for signal HWDATA_int[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @W:CL190 : AHB_IF.v(81) | Optimizing register bit HTRANS[0] to a constant 0
    @W:CL260 : AHB_IF.v(81) | Pruning register bit 0 of HTRANS[1:0]

    @N:CG364 : igloo2.v(376) | Synthesizing module VCC

    @N:CG364 : igloo2.v(372) | Synthesizing module GND

    @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT

    @N:CG364 : igloo2.v(727) | Synthesizing module CCC

    @N:CG364 : eSRAM_eNVM_access_CCC_0_FCCC.v(5) | Synthesizing module eSRAM_eNVM_access_CCC_0_FCCC

    @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB
    @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC

    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC=16'b0000000001010101
    	M_AHBSLOTENABLE=17'b10000000000000000
    	MSB_ADDR=32'b00000000000000000000000000011111
    	SLAVE_0=16'b0000000000000001
    	SLAVE_1=16'b0000000000000010
    	SLAVE_2=16'b0000000000000100
    	SLAVE_3=16'b0000000000001000
    	SLAVE_4=16'b0000000000010000
    	SLAVE_5=16'b0000000000100000
    	SLAVE_6=16'b0000000001000000
    	SLAVE_7=16'b0000000010000000
    	SLAVE_8=16'b0000000100000000
    	SLAVE_9=16'b0000001000000000
    	SLAVE_10=16'b0000010000000000
    	SLAVE_11=16'b0000100000000000
    	SLAVE_12=16'b0001000000000000
    	SLAVE_13=16'b0010000000000000
    	SLAVE_14=16'b0100000000000000
    	SLAVE_15=16'b1000000000000000
    	NONE=16'b0000000000000000
       Generated name = COREAHBLITE_ADDRDEC_Z2

    @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM

    	SYNC_RESET=32'b00000000000000000000000000000000
    	IDLE=1'b0
    	HRESPEXTEND=1'b1
       Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1

    @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE

    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC=16'b0000000001010101
    	M_AHBSLOTENABLE=17'b10000000000000000
    	SYNC_RESET=32'b00000000000000000000000000000000
    	IDLE=1'b0
    	REGISTERED=1'b1
    	SLAVE_NONE=17'b00000000000000000
       Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0

    @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState.
    @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC

    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC=16'b0000000001010101
    	M_AHBSLOTENABLE=17'b00000000000000000
    	MSB_ADDR=32'b00000000000000000000000000011111
    	SLAVE_0=16'b0000000000000001
    	SLAVE_1=16'b0000000000000010
    	SLAVE_2=16'b0000000000000100
    	SLAVE_3=16'b0000000000001000
    	SLAVE_4=16'b0000000000010000
    	SLAVE_5=16'b0000000000100000
    	SLAVE_6=16'b0000000001000000
    	SLAVE_7=16'b0000000010000000
    	SLAVE_8=16'b0000000100000000
    	SLAVE_9=16'b0000001000000000
    	SLAVE_10=16'b0000010000000000
    	SLAVE_11=16'b0000100000000000
    	SLAVE_12=16'b0001000000000000
    	SLAVE_13=16'b0010000000000000
    	SLAVE_14=16'b0100000000000000
    	SLAVE_15=16'b1000000000000000
    	NONE=16'b0000000000000000
       Generated name = COREAHBLITE_ADDRDEC_Z3

    @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE

    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC=16'b0000000001010101
    	M_AHBSLOTENABLE=17'b00000000000000000
    	SYNC_RESET=32'b00000000000000000000000000000000
    	IDLE=1'b0
    	REGISTERED=1'b1
    	SLAVE_NONE=17'b00000000000000000
       Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0s_0_1_0

    @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState.
    @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER

    	SYNC_RESET=32'b00000000000000000000000000000000
    	M0EXTEND=4'b0000
    	M0DONE=4'b0001
    	M0LOCK=4'b0010
    	M0LOCKEXTEND=4'b0011
    	M1EXTEND=4'b0100
    	M1DONE=4'b0101
    	M1LOCK=4'b0110
    	M1LOCKEXTEND=4'b0111
    	M2EXTEND=4'b1000
    	M2DONE=4'b1001
    	M2LOCK=4'b1010
    	M2LOCKEXTEND=4'b1011
    	M3EXTEND=4'b1100
    	M3DONE=4'b1101
    	M3LOCK=4'b1110
    	M3LOCKEXTEND=4'b1111
    	MASTER_0=4'b0001
    	MASTER_1=4'b0010
    	MASTER_2=4'b0100
    	MASTER_3=4'b1000
    	MASTER_NONE=4'b0000
       Generated name = COREAHBLITE_SLAVEARBITER_Z4

    @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE

    	SYNC_RESET=32'b00000000000000000000000000000000
    	TRN_IDLE=1'b0
    	MASTER_NONE=4'b0000
       Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0

    @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16

    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC=16'b0000000001010101
    	M0_AHBSLOTENABLE=17'b10000000000000000
    	M1_AHBSLOTENABLE=17'b00000000000000000
    	M2_AHBSLOTENABLE=17'b00000000000000000
    	M3_AHBSLOTENABLE=17'b00000000000000000
    	SYNC_RESET=32'b00000000000000000000000000000000
       Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s

    @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite

    	FAMILY=6'b011000
    	MEMSPACE=3'b001
    	HADDR_SHG_CFG=1'b1
    	SC_0=1'b1
    	SC_1=1'b0
    	SC_2=1'b1
    	SC_3=1'b0
    	SC_4=1'b1
    	SC_5=1'b0
    	SC_6=1'b1
    	SC_7=1'b0
    	SC_8=1'b0
    	SC_9=1'b0
    	SC_10=1'b0
    	SC_11=1'b0
    	SC_12=1'b0
    	SC_13=1'b0
    	SC_14=1'b0
    	SC_15=1'b0
    	M0_AHBSLOT0ENABLE=1'b0
    	M0_AHBSLOT1ENABLE=1'b0
    	M0_AHBSLOT2ENABLE=1'b0
    	M0_AHBSLOT3ENABLE=1'b0
    	M0_AHBSLOT4ENABLE=1'b0
    	M0_AHBSLOT5ENABLE=1'b0
    	M0_AHBSLOT6ENABLE=1'b0
    	M0_AHBSLOT7ENABLE=1'b0
    	M0_AHBSLOT8ENABLE=1'b0
    	M0_AHBSLOT9ENABLE=1'b0
    	M0_AHBSLOT10ENABLE=1'b0
    	M0_AHBSLOT11ENABLE=1'b0
    	M0_AHBSLOT12ENABLE=1'b0
    	M0_AHBSLOT13ENABLE=1'b0
    	M0_AHBSLOT14ENABLE=1'b0
    	M0_AHBSLOT15ENABLE=1'b0
    	M0_AHBSLOT16ENABLE=1'b1
    	M1_AHBSLOT0ENABLE=1'b0
    	M1_AHBSLOT1ENABLE=1'b0
    	M1_AHBSLOT2ENABLE=1'b0
    	M1_AHBSLOT3ENABLE=1'b0
    	M1_AHBSLOT4ENABLE=1'b0
    	M1_AHBSLOT5ENABLE=1'b0
    	M1_AHBSLOT6ENABLE=1'b0
    	M1_AHBSLOT7ENABLE=1'b0
    	M1_AHBSLOT8ENABLE=1'b0
    	M1_AHBSLOT9ENABLE=1'b0
    	M1_AHBSLOT10ENABLE=1'b0
    	M1_AHBSLOT11ENABLE=1'b0
    	M1_AHBSLOT12ENABLE=1'b0
    	M1_AHBSLOT13ENABLE=1'b0
    	M1_AHBSLOT14ENABLE=1'b0
    	M1_AHBSLOT15ENABLE=1'b0
    	M1_AHBSLOT16ENABLE=1'b0
    	M2_AHBSLOT0ENABLE=1'b0
    	M2_AHBSLOT1ENABLE=1'b0
    	M2_AHBSLOT2ENABLE=1'b0
    	M2_AHBSLOT3ENABLE=1'b0
    	M2_AHBSLOT4ENABLE=1'b0
    	M2_AHBSLOT5ENABLE=1'b0
    	M2_AHBSLOT6ENABLE=1'b0
    	M2_AHBSLOT7ENABLE=1'b0
    	M2_AHBSLOT8ENABLE=1'b0
    	M2_AHBSLOT9ENABLE=1'b0
    	M2_AHBSLOT10ENABLE=1'b0
    	M2_AHBSLOT11ENABLE=1'b0
    	M2_AHBSLOT12ENABLE=1'b0
    	M2_AHBSLOT13ENABLE=1'b0
    	M2_AHBSLOT14ENABLE=1'b0
    	M2_AHBSLOT15ENABLE=1'b0
    	M2_AHBSLOT16ENABLE=1'b0
    	M3_AHBSLOT0ENABLE=1'b0
    	M3_AHBSLOT1ENABLE=1'b0
    	M3_AHBSLOT2ENABLE=1'b0
    	M3_AHBSLOT3ENABLE=1'b0
    	M3_AHBSLOT4ENABLE=1'b0
    	M3_AHBSLOT5ENABLE=1'b0
    	M3_AHBSLOT6ENABLE=1'b0
    	M3_AHBSLOT7ENABLE=1'b0
    	M3_AHBSLOT8ENABLE=1'b0
    	M3_AHBSLOT9ENABLE=1'b0
    	M3_AHBSLOT10ENABLE=1'b0
    	M3_AHBSLOT11ENABLE=1'b0
    	M3_AHBSLOT12ENABLE=1'b0
    	M3_AHBSLOT13ENABLE=1'b0
    	M3_AHBSLOT14ENABLE=1'b0
    	M3_AHBSLOT15ENABLE=1'b0
    	M3_AHBSLOT16ENABLE=1'b0
    	SYNC_RESET=32'b00000000000000000000000000000000
    	M0_AHBSLOTENABLE=17'b10000000000000000
    	M1_AHBSLOTENABLE=17'b00000000000000000
    	M2_AHBSLOTENABLE=17'b00000000000000000
    	M3_AHBSLOTENABLE=17'b00000000000000000
    	SC=16'b0000000001010101
       Generated name = CoreAHBLite_Z5

    @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

    	FAMILY=32'b00000000000000000000000000010011
    	EXT_RESET_CFG=32'b00000000000000000000000000000000
    	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
    	MDDR_IN_USE=32'b00000000000000000000000000000000
    	FDDR_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_IN_USE=32'b00000000000000000000000000000000
    	SDIF1_IN_USE=32'b00000000000000000000000000000000
    	SDIF2_IN_USE=32'b00000000000000000000000000000000
    	SDIF3_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_PCIE=32'b00000000000000000000000000000000
    	SDIF1_PCIE=32'b00000000000000000000000000000000
    	SDIF2_PCIE=32'b00000000000000000000000000000000
    	SDIF3_PCIE=32'b00000000000000000000000000000000
    	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
    	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
    	DEVICE_090=32'b00000000000000000000000000000000
    	DDR_WAIT=32'b00000000000000000000000011001000
    	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
    	SDIF_INTERVAL=32'b00000000000000000001100101100100
    	DDR_INTERVAL=32'b00000000000000000010011100010000
    	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
    	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
    	S0=32'b00000000000000000000000000000000
    	S1=32'b00000000000000000000000000000001
    	S2=32'b00000000000000000000000000000010
    	S3=32'b00000000000000000000000000000011
    	S4=32'b00000000000000000000000000000100
    	S5=32'b00000000000000000000000000000101
    	S6=32'b00000000000000000000000000000110
       Generated name = CoreResetP_Z6

    @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0]

    @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0]

    @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0]

    @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0]

    @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0]

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc

    @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable

    @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable

    @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable

    @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable

    @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable

    @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
    @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset

    @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int

    @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0]

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base

    @N:CG364 : eSRAM_eNVM_access_HPMS_syn.v(5) | Synthesizing module MSS_010

    @N:CG364 : eSRAM_eNVM_access_HPMS.v(9) | Synthesizing module eSRAM_eNVM_access_HPMS

    @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

    @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

    @N:CG364 : eSRAM_eNVM_access_FABOSC_0_OSC.v(5) | Synthesizing module eSRAM_eNVM_access_FABOSC_0_OSC

    @N:CG364 : igloo2.v(718) | Synthesizing module SYSRESET

    @N:CG364 : eSRAM_eNVM_access.v(9) | Synthesizing module eSRAM_eNVM_access

    @N:CG364 : eSRAM_eNVM_RW.v(29) | Synthesizing module eSRAM_eNVM_RW

    @A:CL282 : eSRAM_eNVM_RW.v(96) | Feedback mux created for signal ram_wdata[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @A:CL282 : eSRAM_eNVM_RW.v(96) | Feedback mux created for signal addr_temp[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
    @N:CG364 : igloo2.v(382) | Synthesizing module RAM1K18

    @N:CG364 : eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM.v(5) | Synthesizing module eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM

    @N:CG364 : eSRAM_eNVM_access_top.v(9) | Synthesizing module eSRAM_eNVM_access_top

    @W:CL189 : eSRAM_eNVM_RW.v(96) | Register bit addr_temp[0] is always 0, optimizing ...
    @W:CL189 : eSRAM_eNVM_RW.v(96) | Register bit addr_temp[1] is always 0, optimizing ...
    @W:CL279 : eSRAM_eNVM_RW.v(96) | Pruning register bits 1 to 0 of addr_temp[31:0]

    @N:CL201 : eSRAM_eNVM_RW.v(96) | Trying to extract state machine for register current_state
    Extracted state machine for register current_state
    State machine has 17 reachable states with original encodings of:
       00000
       00001
       00010
       00011
       00100
       00101
       00110
       00111
       01000
       01001
       01010
       01011
       01100
       01101
       01110
       01111
       10000
    @W:CL157 : eSRAM_eNVM_access_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : eSRAM_eNVM_access_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
    @W:CL157 : eSRAM_eNVM_access_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : eSRAM_eNVM_access_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
    @W:CL159 : eSRAM_eNVM_access_FABOSC_0_OSC.v(14) | Input XTL is unused
    @W:CL247 : eSRAM_eNVM_access_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
    @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
    @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
    @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
    @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
    @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
    @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused
    @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused
    @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused
    @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
    @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused
    @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused
    @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused
    @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused
    @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused
    @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused
    @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused
    @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused
    @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused
    @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused
    @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused
    @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused

    @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused

    @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused

    @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused

    @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused

    @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused

    @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused

    @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused

    @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused

    @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused

    @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused

    @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused

    @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused

    @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused

    @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused

    @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused

    @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused

    @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused

    @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused

    @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused

    @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused

    @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused
    @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused
    @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused
    @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused
    @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused
    @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused
    @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused
    @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(73) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(74) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(75) | Input HRESP_S0 is unused
    @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused
    @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused
    @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused
    @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused
    @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused
    @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused
    @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused
    @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused
    @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused
    @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused
    @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused
    @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused
    @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused
    @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused
    @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused
    @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused
    @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState
    Extracted state machine for register arbRegSMCurrentState
    State machine has 16 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       0101
       0110
       0111
       1000
       1001
       1010
       1011
       1100
       1101
       1110
       1111
    @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused
    @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused
    @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused
    @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused
    @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused

    @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 15 to 0 of SHRESP[16:0] are unused

    @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused
    @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused
    @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused
    @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused
    @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused
    @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused
    @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused
    @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused
    @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused
    @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused
    @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused
    @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused
    @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused
    @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused
    @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused
    @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused
    @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused
    @N:CL201 : AHB_IF.v(81) | Trying to extract state machine for register ahb_fsm_current_state
    Extracted state machine for register ahb_fsm_current_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 87MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 15:36:53 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 15:36:54 2016

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 15:36:54 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    File E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\synthesis\synwork\eSRAM_eNVM_access_top_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 15:36:55 2016

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: eSRAM_eNVM_access_top_scck.rpt
    Printing clock  summary report in "E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\synthesis\eSRAM_eNVM_access_top_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 118MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 118MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 118MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 119MB)

    @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14
    @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13
    @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12
    @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11
    @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs
    @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs
    @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs
    @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs
    @N:BN115 : coreahblite_matrix4x16.v(2890) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs
    @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog) because there are no references to its outputs
    syn_allowed_resources : blockrams=21  set on top level netlist eSRAM_eNVM_access_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 147MB)

    @S |Clock Summary
    *****************

    Start                                                                Requested     Requested     Clock        Clock
    Clock                                                                Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    =================================================================================================================================

    @W:MT530 : ahb_if.v(81) | Found inferred clock eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock which controls 402 sequential elements including AHB_IF_0.VALID. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.v(912) | Found inferred clock eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including eSRAM_eNVM_access_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\synthesis\eSRAM_eNVM_access_top.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 147MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 15:36:56 2016

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

    @W:MO111 : esram_envm_access_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC)
    @W:MO111 : esram_envm_access_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC)
    @W:MO111 : esram_envm_access_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC)
    @W:MO111 : esram_envm_access_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC)
    @W:MO171 : coreresetp.v(676) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(1388) | Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation
    @W:BN132 : coreresetp.v(963) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG2_DONE_q1
    @W:BN132 : coreresetp.v(946) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG2_DONE_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG1_DONE_q1
    @W:BN132 : coreresetp.v(946) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG2_DONE_clk_base,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.v(929) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG1_DONE_clk_base,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.v(884) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(912) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(898) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(856) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(898) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_rcosc
    @W:BN132 : coreresetp.v(912) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_rcosc

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 139MB)

    Encoding state machine ahb_fsm_current_state[6:0] (view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    @W:MO160 : ahb_if.v(81) | Register bit HADDR[1] is always 0, optimizing ...
    @W:MO160 : ahb_if.v(81) | Register bit HADDR[0] is always 0, optimizing ...
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs
    @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] is always 0, optimizing ...
    @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
    @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
    @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
    @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
    @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs
    Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog))
    original code -> new code
       0000 -> 0000000000000001
       0001 -> 0000000000000010
       0010 -> 0000000000000100
       0011 -> 0000000000001000
       0100 -> 0000000000010000
       0101 -> 0000000000100000
       0110 -> 0000000001000000
       0111 -> 0000000010000000
       1000 -> 0000000100000000
       1001 -> 0000001000000000
       1010 -> 0000010000000000
       1011 -> 0000100000000000
       1100 -> 0001000000000000
       1101 -> 0010000000000000
       1110 -> 0100000000000000
       1111 -> 1000000000000000
    @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
    @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
    @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
    Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z6(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    Encoding state machine current_state[16:0] (view:work.eSRAM_eNVM_RW(verilog))
    original code -> new code
       00000 -> 00000000000000001
       00001 -> 00000000000000010
       00010 -> 00000000000000100
       00011 -> 00000000000001000
       00100 -> 00000000000010000
       00101 -> 00000000000100000
       00110 -> 00000000001000000
       00111 -> 00000000010000000
       01000 -> 00000000100000000
       01001 -> 00000001000000000
       01010 -> 00000010000000000
       01011 -> 00000100000000000
       01100 -> 00001000000000000
       01101 -> 00010000000000000
       01110 -> 00100000000000000
       01111 -> 01000000000000000
       10000 -> 10000000000000000
    @N: : esram_envm_rw.v(96) | Found counter in view:work.eSRAM_eNVM_RW(verilog) inst addr_temp[31:2]
    @N: : esram_envm_rw.v(96) | Found counter in view:work.eSRAM_eNVM_RW(verilog) inst ram_waddr[4:0]
    @N: : esram_envm_rw.v(96) | Found counter in view:work.eSRAM_eNVM_RW(verilog) inst data[31:0]
    @N: : esram_envm_rw.v(96) | Found counter in view:work.eSRAM_eNVM_RW(verilog) inst data_cnt[4:0]
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)

    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)

    @N:BN362 : coreresetp.v(1613) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @A:BN291 : coreresetp.v(1613) | Boundary register eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @A:BN291 : coreresetp.v(1646) | Boundary register eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled_q1 packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N:BN362 : coreresetp.v(963) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(929) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(870) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(856) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(755) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(755) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)

    @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 143MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 143MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 141MB peak: 143MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 156MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		     1.97ns		 424 /       328
    @N:FP130 :  | Promoting Net eSRAM_eNVM_access_0_HPMS_READY on CLKINT  I_16

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 156MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 156MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 331 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================================================== Non-Gated/Non-Generated Clocks ===========================================================
    Clock Tree ID     Driving Element                        Drive Element Type     Fanout     Sample Instance
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        eSRAM_eNVM_access_0.CCC_0.GL0_INST     CLKINT                 331        eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST
    ======================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 125MB peak: 156MB)

    Writing Analyst data base E:\Libero_11p7_updates\downloaded\eSRAM_eNVM_RW_Fabric\Libero_project\IGL2\synthesis\synwork\eSRAM_eNVM_access_top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 156MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    J-2015.03M-SP1-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 156MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 156MB)

    @W:MT246 : esram_envm_access_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:eSRAM_eNVM_access_0.FABOSC_0.RCOSC_25_50MHZ_CCC"

    @W:MT420 :  | Found inferred clock eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:eSRAM_eNVM_access_0.CCC_0.GL0_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Feb 19 15:36:59 2016
    #

    Top view:               eSRAM_eNVM_access_top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 2.596

                                                                         Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                                       Frequency     Frequency     Period        Period        Slack     Type         Group
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     135.1 MHz     10.000        7.404         2.596     inferred     Inferred_clkgroup_0
    eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_1
    =======================================================================================================================================================================
    @N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack

    Clock Relationships
    *******************

    Clocks                                                                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                             Ending                                               |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock  eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      2.596  |  No paths    -      |  No paths    -      |  No paths    -
    ================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                                    Starting                                                                                                                    Arrival
    Instance                                                                        Reference                                               Type        Pin                Net                                  Time        Slack
                                                                                    Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_READYOUT     CoreAHBLite_0_AHBmslave16_HREADY     3.086       2.596
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  masterRegAddrSel                     0.094       3.362
    AHB_IF_0.HADDR[31]                                                              eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  AHB_IF_0_BIF_1_HADDR[31]             0.076       3.681
    AHB_IF_0.HTRANS_1[1]                                                            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  AHB_IF_0_BIF_1_HTRANS[1]             0.094       3.863
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  regHTRANS                            0.094       3.967
    AHB_IF_0.DATAOUT[0]                                                             eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  AHB_IF_0_DATAOUT[0]                  0.094       4.050
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[1]                       0.094       4.126
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[3]                       0.094       4.186
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[5]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[5]                       0.094       4.208
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[9]                       0.094       4.268
    =============================================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                    Starting                                                                                                                     Required
    Instance                                                        Reference                                               Type        Pin               Net                                    Time         Slack
                                                                    Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_TRANS1      m21_N_10_i_0                           8.886        2.596
    AHB_IF_0.HWRITE                                                 eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_147_mux_i_0                          9.707        3.163
    eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_ADDR[4]     CoreAHBLite_0_AHBmslave16_HADDR[4]     8.848        3.362
    AHB_IF_0.HADDR[2]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[3]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[4]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[5]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[6]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[7]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    AHB_IF_0.HADDR[8]                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                N_101_i_0                              9.707        3.392
    ===============================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            1.114
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.886

        - Propagation time:                      6.290
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     2.596

        Number of logic level(s):                2
        Starting point:                          eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT
        Ending point:                            eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST / F_FM0_TRANS1
        The start point is clocked by            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                                                                Pin                Pin               Arrival     No. of
    Name                                                                                                              Type        Name               Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                                                       MSS_010     F_FM0_READYOUT     Out     3.086     3.086       -
    CoreAHBLite_0_AHBmslave16_HREADY                                                                                  Net         -                  -       0.988     -           10
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMNextState_0_a3_RNI7JN65     CFG3        B                  In      -         4.074       -
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMNextState_0_a3_RNI7JN65     CFG3        Y                  Out     0.143     4.217       -
    PREVDATASLAVEREADY_iv_i_0                                                                                         Net         -                  -       0.920     -           14
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNISP6E8[16]                               CFG4        C                  In      -         5.137       -
    eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt_RNISP6E8[16]                               CFG4        Y                  Out     0.182     5.319       -
    m21_N_10_i_0                                                                                                      Net         -                  -       0.971     -           1
    eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                                                       MSS_010     F_FM0_TRANS1       In      -         6.290       -
    =========================================================================================================================================================================================
    Total path delay (propagation time + setup) of 7.404 is 4.525(61.1%) logic and 2.879(38.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 156MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 156MB)

    ---------------------------------------
    Resource Usage Report for eSRAM_eNVM_access_top

    Mapping to part: m2gl010tfbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          2 uses
    MSS_010         1 use
    RCOSC_25_50MHZ  1 use
    SYSRESET        1 use
    CFG2           155 uses
    CFG3           48 uses
    CFG4           146 uses

    Carry primitives used for arithmetic functions:
    ARI1           63 uses

    Sequential Cells:
    SLE            328 uses

    DSP Blocks:    0

    I/O ports: 11
    I/O primitives: 10
    INBUF          2 uses
    OUTBUF         8 uses

    Global Clock Buffers: 2

    RAM/ROM usage summary
    Block Rams (RAM1K18) : 1

    Total LUTs:    412

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 36; LUTs = 36;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  328 + 0 + 36 + 0 = 364;
    Total number of LUTs after P&R:  412 + 0 + 36 + 0 = 448;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 51MB peak: 156MB)

    Process took 0h:00m:02s realtime, 0h:00m:02s cputime
    # Fri Feb 19 15:36:59 2016

    ###########################################################]

`