@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3166:2:3166:13|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3120:2:3120:13|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT530 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\hdl\ahb_if.v":81:0:81:5|Found inferred clock eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock which controls 402 sequential elements including AHB_IF_0.VALID. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\libero_11p7_updates\downloaded\esram_envm_rw_fabric\libero_project\sf2\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Found inferred clock eSRAM_eNVM_access_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including eSRAM_eNVM_access_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. 
