//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri Feb 19 16:21:53 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// eSRAM_eNVM_access_top
module eSRAM_eNVM_access_top(
    // Inputs
    DEVRST_N,
    start_envm,
    start_esram,
    // Outputs
    RD
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        DEVRST_N;
input        start_envm;
input        start_esram;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [7:0] RD;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          AHB_IF_0_AHB_BUSY;
wire   [31:0] AHB_IF_0_BIF_1_HADDR;
wire   [2:0]  AHB_IF_0_BIF_1_HBURST;
wire   [3:0]  AHB_IF_0_BIF_1_HPROT;
wire   [31:0] AHB_IF_0_BIF_1_HRDATA;
wire          AHB_IF_0_BIF_1_HREADY;
wire   [1:0]  AHB_IF_0_BIF_1_HRESP;
wire   [2:0]  AHB_IF_0_BIF_1_HSIZE;
wire   [1:0]  AHB_IF_0_BIF_1_HTRANS;
wire   [31:0] AHB_IF_0_BIF_1_HWDATA;
wire          AHB_IF_0_BIF_1_HWRITE;
wire   [31:0] AHB_IF_0_DATAOUT;
wire          AHB_IF_0_VALID;
wire          DEVRST_N;
wire          eSRAM_eNVM_access_0_FIC_0_CLK;
wire          eSRAM_eNVM_access_0_MSS_READY;
wire   [31:0] eSRAM_eNVM_RW_0_ADDR;
wire   [31:0] eSRAM_eNVM_RW_0_DATAOUT;
wire   [4:0]  eSRAM_eNVM_RW_0_ram_waddr;
wire   [31:0] eSRAM_eNVM_RW_0_ram_wdata;
wire          eSRAM_eNVM_RW_0_ram_wen;
wire          eSRAM_eNVM_RW_0_READ;
wire          eSRAM_eNVM_RW_0_WRITE;
wire   [7:0]  RD_net_0;
wire          start_envm;
wire          start_esram;
wire   [7:0]  RD_net_1;
wire   [31:8] RD_slice_0;
wire   [31:0] RD_net_2;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [2:0]  HSIZE_IN_const_net_0;
wire          VCC_net;
wire          GND_net;
wire   [4:0]  RADDR_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign HSIZE_IN_const_net_0 = 3'h2;
assign VCC_net              = 1'b1;
assign GND_net              = 1'b0;
assign RADDR_const_net_0    = 5'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign RD_net_1 = RD_net_0;
assign RD[7:0]  = RD_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign RD_net_0   = RD_net_2[7:0];
assign RD_slice_0 = RD_net_2[31:8];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AHB_IF
AHB_IF #( 
        .Data_size   ( 32 ),
        .Idle_1      ( 0 ),
        .Read_FIC_0  ( 4 ),
        .Read_FIC_1  ( 5 ),
        .Read_FIC_2  ( 6 ),
        .Write_FIC_0 ( 1 ),
        .Write_FIC_1 ( 2 ),
        .Write_FIC_2 ( 3 ) )
AHB_IF_0(
        // Inputs
        .HCLK     ( eSRAM_eNVM_access_0_FIC_0_CLK ),
        .HRESETn  ( eSRAM_eNVM_access_0_MSS_READY ),
        .READ     ( eSRAM_eNVM_RW_0_READ ),
        .WRITE    ( eSRAM_eNVM_RW_0_WRITE ),
        .HREADY   ( AHB_IF_0_BIF_1_HREADY ),
        .ADDR     ( eSRAM_eNVM_RW_0_ADDR ),
        .DATAIN   ( eSRAM_eNVM_RW_0_DATAOUT ),
        .HSIZE_IN ( HSIZE_IN_const_net_0 ),
        .HRDATA   ( AHB_IF_0_BIF_1_HRDATA ),
        .HRESP    ( AHB_IF_0_BIF_1_HRESP ),
        // Outputs
        .HWRITE   ( AHB_IF_0_BIF_1_HWRITE ),
        .AHB_BUSY ( AHB_IF_0_AHB_BUSY ),
        .VALID    ( AHB_IF_0_VALID ),
        .DATAOUT  ( AHB_IF_0_DATAOUT ),
        .HADDR    ( AHB_IF_0_BIF_1_HADDR ),
        .HTRANS   ( AHB_IF_0_BIF_1_HTRANS ),
        .HSIZE    ( AHB_IF_0_BIF_1_HSIZE ),
        .HBURST   ( AHB_IF_0_BIF_1_HBURST ),
        .HPROT    ( AHB_IF_0_BIF_1_HPROT ),
        .HWDATA   ( AHB_IF_0_BIF_1_HWDATA ),
        .RESP_err (  ) 
        );

//--------eSRAM_eNVM_access
eSRAM_eNVM_access eSRAM_eNVM_access_0(
        // Inputs
        .FAB_RESET_N                ( VCC_net ),
        .AMBA_MASTER_0_HWRITE_M0    ( AHB_IF_0_BIF_1_HWRITE ),
        .AMBA_MASTER_0_HMASTLOCK_M0 ( GND_net ), // tied to 1'b0 from definition
        .DEVRST_N                   ( DEVRST_N ),
        .AMBA_MASTER_0_HADDR_M0     ( AHB_IF_0_BIF_1_HADDR ),
        .AMBA_MASTER_0_HTRANS_M0    ( AHB_IF_0_BIF_1_HTRANS ),
        .AMBA_MASTER_0_HSIZE_M0     ( AHB_IF_0_BIF_1_HSIZE ),
        .AMBA_MASTER_0_HBURST_M0    ( AHB_IF_0_BIF_1_HBURST ),
        .AMBA_MASTER_0_HPROT_M0     ( AHB_IF_0_BIF_1_HPROT ),
        .AMBA_MASTER_0_HWDATA_M0    ( AHB_IF_0_BIF_1_HWDATA ),
        // Outputs
        .POWER_ON_RESET_N           (  ),
        .INIT_DONE                  (  ),
        .AMBA_MASTER_0_HREADY_M0    ( AHB_IF_0_BIF_1_HREADY ),
        .FIC_0_CLK                  ( eSRAM_eNVM_access_0_FIC_0_CLK ),
        .FIC_0_LOCK                 (  ),
        .MSS_READY                  ( eSRAM_eNVM_access_0_MSS_READY ),
        .AMBA_MASTER_0_HRDATA_M0    ( AHB_IF_0_BIF_1_HRDATA ),
        .AMBA_MASTER_0_HRESP_M0     ( AHB_IF_0_BIF_1_HRESP ) 
        );

//--------eSRAM_eNVM_RW
eSRAM_eNVM_RW #( 
        .CMD_Write       ( 7 ),
        .ENVM0_ACCESS1   ( 3 ),
        .ENVM0_ACCESS2   ( 4 ),
        .ENVM0_Prog      ( 8 ),
        .ENVM0_RELEASE   ( 16 ),
        .ENVM0_WD        ( 5 ),
        .ENVM_Idle_0     ( 1 ),
        .ENVM_Idle_1     ( 2 ),
        .ENVM_INIT_DONE  ( 9 ),
        .ESRAM_0         ( 10 ),
        .ESRAM_1         ( 11 ),
        .ESRAM_2         ( 12 ),
        .Fill_WD         ( 6 ),
        .Idle_ESRAM_ENVM ( 0 ),
        .Read_0          ( 13 ),
        .Read_1          ( 14 ),
        .Read_2          ( 15 ) )
eSRAM_eNVM_RW_0(
        // Inputs
        .CLK         ( eSRAM_eNVM_access_0_FIC_0_CLK ),
        .RESETn      ( eSRAM_eNVM_access_0_MSS_READY ),
        .start_envm  ( start_envm ),
        .start_esram ( start_esram ),
        .valid       ( AHB_IF_0_VALID ),
        .busy        ( AHB_IF_0_AHB_BUSY ),
        .DATAIN      ( AHB_IF_0_DATAOUT ),
        // Outputs
        .READ        ( eSRAM_eNVM_RW_0_READ ),
        .WRITE       ( eSRAM_eNVM_RW_0_WRITE ),
        .ram_wen     ( eSRAM_eNVM_RW_0_ram_wen ),
        .ADDR        ( eSRAM_eNVM_RW_0_ADDR ),
        .DATAOUT     ( eSRAM_eNVM_RW_0_DATAOUT ),
        .ram_waddr   ( eSRAM_eNVM_RW_0_ram_waddr ),
        .ram_wdata   ( eSRAM_eNVM_RW_0_ram_wdata ) 
        );

//--------eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM TPSRAM_0(
        // Inputs
        .WEN   ( eSRAM_eNVM_RW_0_ram_wen ),
        .REN   ( GND_net ),
        .CLK   ( eSRAM_eNVM_access_0_FIC_0_CLK ),
        .WD    ( eSRAM_eNVM_RW_0_ram_wdata ),
        .WADDR ( eSRAM_eNVM_RW_0_ram_waddr ),
        .RADDR ( RADDR_const_net_0 ),
        // Outputs
        .RD    ( RD_net_2 ) 
        );


endmodule
