#Build: Synplify Pro I-2013.09M-SP1-1 , Build 034R, Jan 17 2014
#install: E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1
#OS: Windows 7 6.1
#Hostname: W764-KUMARJ

#Implementation: synthesis

$ Start of Compile
#Tue Aug 05 13:48:14 2014

Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v"
@I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\umr_capim.v"
@I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\scemi_objects.v"
@I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\scemi_pipes.svh"
@I::"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\vlog\hypermods.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\CCC_0\eSRAM_eNVM_access_CCC_0_FCCC.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS_syn.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\SgCore\OSC\1.0.102\osc_comps.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\eSRAM_eNVM_access.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_top\TPSRAM_0\eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM.v"
@I::"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_top\eSRAM_eNVM_access_top.v"
@W: CG775 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
Verilog syntax check successful!
Selecting top level module eSRAM_eNVM_access_top
@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":21:7:21:12|Synthesizing module AHB_IF

	Idle_1=3'b000
	Write_FIC_0=3'b001
	Write_FIC_1=3'b010
	Write_FIC_2=3'b011
	Read_FIC_0=3'b100
	Read_FIC_1=3'b101
	Read_FIC_2=3'b110
	Data_size=5'b00000
   Generated name = AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1

@W: CG360 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":60:13:60:21|No assignment to wire HSIZE_int

@A: CL282 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":81:0:81:5|Feedback mux created for signal HWDATA_int[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":81:0:81:5|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":81:0:81:5|Pruning register bit 0 of HTRANS[1:0] 

@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":371:7:371:9|Synthesizing module VCC

@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":367:7:367:9|Synthesizing module GND

@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":362:7:362:12|Synthesizing module CLKINT

@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":722:7:722:9|Synthesizing module CCC

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\CCC_0\eSRAM_eNVM_access_CCC_0_FCCC.v":5:7:5:34|Synthesizing module eSRAM_eNVM_access_CCC_0_FCCC

@W: CG775 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z2

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v":29:7:29:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b10000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0_1_0

@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v":29:7:29:25|Synthesizing module COREAHBLITE_ADDRDEC

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	MSB_ADDR=32'b00000000000000000000000000011111
	SLAVE_0=16'b0000000000000001
	SLAVE_1=16'b0000000000000010
	SLAVE_2=16'b0000000000000100
	SLAVE_3=16'b0000000000001000
	SLAVE_4=16'b0000000000010000
	SLAVE_5=16'b0000000000100000
	SLAVE_6=16'b0000000001000000
	SLAVE_7=16'b0000000010000000
	SLAVE_8=16'b0000000100000000
	SLAVE_9=16'b0000001000000000
	SLAVE_10=16'b0000010000000000
	SLAVE_11=16'b0000100000000000
	SLAVE_12=16'b0001000000000000
	SLAVE_13=16'b0010000000000000
	SLAVE_14=16'b0100000000000000
	SLAVE_15=16'b1000000000000000
	NONE=16'b0000000000000000
   Generated name = COREAHBLITE_ADDRDEC_Z3

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":31:7:31:29|Synthesizing module COREAHBLITE_MASTERSTAGE

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M_AHBSLOTENABLE=17'b00000000000000000
	IDLE=1'b0
	REGISTERED=1'b1
	SLAVE_NONE=17'b00000000000000000
   Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0

@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":629:0:629:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":28:7:28:30|Synthesizing module COREAHBLITE_SLAVEARBITER

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":30:7:30:28|Synthesizing module COREAHBLITE_SLAVESTAGE

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":31:7:31:28|Synthesizing module COREAHBLITE_MATRIX4X16

	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC=16'b0000000001010101
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
   Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":32:7:32:17|Synthesizing module CoreAHBLite

	FAMILY=6'b010011
	MEMSPACE=3'b001
	HADDR_SHG_CFG=1'b1
	SC_0=1'b1
	SC_1=1'b0
	SC_2=1'b1
	SC_3=1'b0
	SC_4=1'b1
	SC_5=1'b0
	SC_6=1'b1
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	M0_AHBSLOT0ENABLE=1'b0
	M0_AHBSLOT1ENABLE=1'b0
	M0_AHBSLOT2ENABLE=1'b0
	M0_AHBSLOT3ENABLE=1'b0
	M0_AHBSLOT4ENABLE=1'b0
	M0_AHBSLOT5ENABLE=1'b0
	M0_AHBSLOT6ENABLE=1'b0
	M0_AHBSLOT7ENABLE=1'b0
	M0_AHBSLOT8ENABLE=1'b0
	M0_AHBSLOT9ENABLE=1'b0
	M0_AHBSLOT10ENABLE=1'b0
	M0_AHBSLOT11ENABLE=1'b0
	M0_AHBSLOT12ENABLE=1'b0
	M0_AHBSLOT13ENABLE=1'b0
	M0_AHBSLOT14ENABLE=1'b0
	M0_AHBSLOT15ENABLE=1'b0
	M0_AHBSLOT16ENABLE=1'b1
	M1_AHBSLOT0ENABLE=1'b0
	M1_AHBSLOT1ENABLE=1'b0
	M1_AHBSLOT2ENABLE=1'b0
	M1_AHBSLOT3ENABLE=1'b0
	M1_AHBSLOT4ENABLE=1'b0
	M1_AHBSLOT5ENABLE=1'b0
	M1_AHBSLOT6ENABLE=1'b0
	M1_AHBSLOT7ENABLE=1'b0
	M1_AHBSLOT8ENABLE=1'b0
	M1_AHBSLOT9ENABLE=1'b0
	M1_AHBSLOT10ENABLE=1'b0
	M1_AHBSLOT11ENABLE=1'b0
	M1_AHBSLOT12ENABLE=1'b0
	M1_AHBSLOT13ENABLE=1'b0
	M1_AHBSLOT14ENABLE=1'b0
	M1_AHBSLOT15ENABLE=1'b0
	M1_AHBSLOT16ENABLE=1'b0
	M2_AHBSLOT0ENABLE=1'b0
	M2_AHBSLOT1ENABLE=1'b0
	M2_AHBSLOT2ENABLE=1'b0
	M2_AHBSLOT3ENABLE=1'b0
	M2_AHBSLOT4ENABLE=1'b0
	M2_AHBSLOT5ENABLE=1'b0
	M2_AHBSLOT6ENABLE=1'b0
	M2_AHBSLOT7ENABLE=1'b0
	M2_AHBSLOT8ENABLE=1'b0
	M2_AHBSLOT9ENABLE=1'b0
	M2_AHBSLOT10ENABLE=1'b0
	M2_AHBSLOT11ENABLE=1'b0
	M2_AHBSLOT12ENABLE=1'b0
	M2_AHBSLOT13ENABLE=1'b0
	M2_AHBSLOT14ENABLE=1'b0
	M2_AHBSLOT15ENABLE=1'b0
	M2_AHBSLOT16ENABLE=1'b0
	M3_AHBSLOT0ENABLE=1'b0
	M3_AHBSLOT1ENABLE=1'b0
	M3_AHBSLOT2ENABLE=1'b0
	M3_AHBSLOT3ENABLE=1'b0
	M3_AHBSLOT4ENABLE=1'b0
	M3_AHBSLOT5ENABLE=1'b0
	M3_AHBSLOT6ENABLE=1'b0
	M3_AHBSLOT7ENABLE=1'b0
	M3_AHBSLOT8ENABLE=1'b0
	M3_AHBSLOT9ENABLE=1'b0
	M3_AHBSLOT10ENABLE=1'b0
	M3_AHBSLOT11ENABLE=1'b0
	M3_AHBSLOT12ENABLE=1'b0
	M3_AHBSLOT13ENABLE=1'b0
	M3_AHBSLOT14ENABLE=1'b0
	M3_AHBSLOT15ENABLE=1'b0
	M3_AHBSLOT16ENABLE=1'b0
	M0_AHBSLOTENABLE=17'b10000000000000000
	M1_AHBSLOTENABLE=17'b00000000000000000
	M2_AHBSLOTENABLE=17'b00000000000000000
	M3_AHBSLOTENABLE=17'b00000000000000000
	SC=16'b0000000001010101
   Generated name = CoreAHBLite_Z4

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z5

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning register count_sdif0[12:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_rcosc 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning register count_sdif0_enable 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 

@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 

@W: CL169 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS_syn.v":5:7:5:13|Synthesizing module MSS_010

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS.v":9:7:9:28|Synthesizing module eSRAM_eNVM_access_HPMS

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\SgCore\OSC\1.0.102\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\SgCore\OSC\1.0.102\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":5:7:5:36|Synthesizing module eSRAM_eNVM_access_FABOSC_0_OSC

@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":713:7:713:14|Synthesizing module SYSRESET

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\eSRAM_eNVM_access.v":9:7:9:23|Synthesizing module eSRAM_eNVM_access

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":26:7:26:19|Synthesizing module eSRAM_eNVM_RW

@A: CL282 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Feedback mux created for signal ram_wdata[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Feedback mux created for signal addr_temp[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CG364 :"E:\Microsemi\Libero_v11.4\Synopsys\synplify_I201309MSP1-1\lib\generic\igloo2.v":377:7:377:13|Synthesizing module RAM1K18

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_top\TPSRAM_0\eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM.v":5:7:5:43|Synthesizing module eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM

@N: CG364 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_top\eSRAM_eNVM_access_top.v":9:7:9:27|Synthesizing module eSRAM_eNVM_access_top

@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[6] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[7] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[10] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[11] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[12] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[13] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[16] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[18] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[19] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[22] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[25] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[26] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[28] to a constant 0
@W: CL190 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Optimizing register bit data[30] to a constant 0
@W: CL189 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Register bit addr_temp[0] is always 0, optimizing ...
@W: CL189 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Register bit addr_temp[1] is always 0, optimizing ...
@W: CL279 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bits 1 to 0 of addr_temp[31:0] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 30 of data[31:0] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 28 of data[31:0] 

@W: CL279 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bits 26 to 25 of data[31:0] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 22 of data[31:0] 

@W: CL279 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bits 19 to 18 of data[31:0] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 16 of data[31:0] 

@W: CL279 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bits 13 to 10 of data[31:0] 

@W: CL279 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bits 7 to 6 of data[31:0] 

@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Trying to extract state machine for register current_state
Extracted state machine for register current_state
State machine has 18 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 9 of data[9:8] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 15 of data[15:14] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 21 of data[21:20] 

@W: CL260 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\eSRAM_eNVM_RW.v":80:0:80:5|Pruning register bit 24 of data[24:23] 

@W: CL157 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access\FABOSC_0\eSRAM_eNVM_access_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\work\eSRAM_eNVM_access_HPMS\eSRAM_eNVM_access_HPMS.v":51:14:51:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused

@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":107:20:107:37|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":108:20:108:33|Input SOFT_RESET_F2M is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":109:20:109:32|Input SOFT_M3_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":110:20:110:49|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":111:20:111:39|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":112:20:112:39|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":113:20:113:40|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":114:20:114:39|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":115:20:115:40|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":116:20:116:39|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":117:20:117:40|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":118:20:118:39|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":119:20:119:40|Input SOFT_SDIF3_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":123:20:123:42|Input SOFT_SDIF0_0_CORE_RESET is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":124:20:124:42|Input SOFT_SDIF0_1_CORE_RESET is unused
@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":128:15:128:23|Input port bit 0 of HTRANS_M0[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":139:15:139:23|Input port bit 0 of HTRANS_M1[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":150:15:150:23|Input port bit 0 of HTRANS_M2[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":161:15:161:23|Input port bit 0 of HTRANS_M3[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":171:15:171:22|Input port bit 1 of HRESP_S0[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S1[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S2[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S3[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S4[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S5[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S6[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S7[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S8[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S9[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":301:15:301:23|Input port bit 1 of HRESP_S10[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S11[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S12[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S13[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S14[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S15[1:0] is unused

@W: CL247 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S16[1:0] is unused

@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input HBURST_M0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":132:15:132:22|Input HPROT_M0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input HBURST_M1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":143:15:143:22|Input HPROT_M1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input HBURST_M2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":154:15:154:22|Input HPROT_M2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":164:15:164:23|Input HBURST_M3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v":165:15:165:22|Input HPROT_M3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":58:18:58:26|Input HWDATA_M1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":67:18:67:26|Input HWDATA_M2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":76:18:76:26|Input HWDATA_M3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":80:18:80:26|Input HRDATA_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":81:13:81:24|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":82:13:82:20|Input HRESP_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":91:18:91:26|Input HRDATA_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":92:13:92:24|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":93:13:93:20|Input HRESP_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":102:18:102:26|Input HRDATA_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":103:13:103:24|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":104:13:104:20|Input HRESP_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":113:18:113:26|Input HRDATA_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":114:13:114:24|Input HREADYOUT_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":115:13:115:20|Input HRESP_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":124:18:124:26|Input HRDATA_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":125:13:125:24|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":126:13:126:20|Input HRESP_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":135:18:135:26|Input HRDATA_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":136:13:136:24|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":137:13:137:20|Input HRESP_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":146:18:146:26|Input HRDATA_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":147:13:147:24|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":148:13:148:20|Input HRESP_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":157:18:157:26|Input HRDATA_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":158:13:158:24|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":159:13:159:20|Input HRESP_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":168:18:168:26|Input HRDATA_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":169:13:169:24|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":170:13:170:20|Input HRESP_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":179:18:179:26|Input HRDATA_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":180:13:180:24|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":181:13:181:20|Input HRESP_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":190:18:190:27|Input HRDATA_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":191:13:191:25|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":192:13:192:21|Input HRESP_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":201:18:201:27|Input HRDATA_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":202:13:202:25|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":203:13:203:21|Input HRESP_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":212:18:212:27|Input HRDATA_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":213:13:213:25|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":214:13:214:21|Input HRESP_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":223:18:223:27|Input HRDATA_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":224:13:224:25|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":225:13:225:21|Input HRESP_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":234:18:234:27|Input HRDATA_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":235:13:235:25|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":236:13:236:21|Input HRESP_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":245:18:245:27|Input HRDATA_S15 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":246:13:246:25|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":247:13:247:21|Input HRESP_S15 is unused
@W: CL246 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":46:15:46:33|Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused

@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Trying to extract state machine for register arbRegSMCurrentState
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input SDATAREADY is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input SHRESP is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":92:16:92:25|Input HRDATA_S16 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":93:11:93:23|Input HREADYOUT_S16 is unused
@W: CL246 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":50:16:50:25|Input port bits 15 to 0 of SDATAREADY[16:0] are unused

@W: CL246 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":51:16:51:21|Input port bits 15 to 0 of SHRESP[16:0] are unused

@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":60:16:60:24|Input HRDATA_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":61:11:61:22|Input HREADYOUT_S0 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":62:16:62:24|Input HRDATA_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":63:11:63:22|Input HREADYOUT_S1 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":64:16:64:24|Input HRDATA_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":65:11:65:22|Input HREADYOUT_S2 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":66:16:66:24|Input HRDATA_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":67:11:67:22|Input HREADYOUT_S3 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":68:16:68:24|Input HRDATA_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":69:11:69:22|Input HREADYOUT_S4 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":70:16:70:24|Input HRDATA_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":71:11:71:22|Input HREADYOUT_S5 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":72:16:72:24|Input HRDATA_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":73:11:73:22|Input HREADYOUT_S6 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":74:16:74:24|Input HRDATA_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":75:11:75:22|Input HREADYOUT_S7 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":76:16:76:24|Input HRDATA_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":77:11:77:22|Input HREADYOUT_S8 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":78:16:78:24|Input HRDATA_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":79:11:79:22|Input HREADYOUT_S9 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":80:16:80:25|Input HRDATA_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":81:11:81:23|Input HREADYOUT_S10 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":82:16:82:25|Input HRDATA_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":83:11:83:23|Input HREADYOUT_S11 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":84:16:84:25|Input HRDATA_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":85:11:85:23|Input HREADYOUT_S12 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":86:16:86:25|Input HRDATA_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":87:11:87:23|Input HREADYOUT_S13 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":88:16:88:25|Input HRDATA_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":89:11:89:23|Input HREADYOUT_S14 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":90:16:90:25|Input HRDATA_S15 is unused
@W: CL159 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":91:11:91:23|Input HREADYOUT_S15 is unused
@N: CL201 :"E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\hdl\AHB_IF.v":81:0:81:5|Trying to extract state machine for register ahb_fsm_current_state
Extracted state machine for register ahb_fsm_current_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@END

At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 05 13:48:16 2014

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 004R, Built May 28 2014 16:50:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\synthesis\eSRAM_eNVM_access_top_scck.rpt 
Printing clock  summary report in "E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\synthesis\eSRAM_eNVM_access_top_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 110MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 110MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)

@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3567:27:3567:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3522:27:3522:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3477:27:3477:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3432:27:3432:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3387:27:3387:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3297:26:3297:37|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3252:27:3252:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3207:27:3207:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3162:27:3162:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3117:27:3117:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3072:27:3072:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3027:27:3027:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_3,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2982:27:2982:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3342:27:3342:39|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_1
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2937:27:2937:38|Removing user instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_1,  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_0
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance eSRAM_eNVM_access_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance eSRAM_eNVM_access_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[31],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[29]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[29],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[23]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[23],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[20]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[20],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[17]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[17],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[14]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Removing sequential instance eSRAM_eNVM_RW_0.data[8],  because it is equivalent to instance eSRAM_eNVM_RW_0.data[14]
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2708:2:2708:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs 
@N: BN115 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2771:2:2771:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs 
@N: BN115 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2834:2:2834:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs 
@N: BN115 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2892:27:2892:38|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance sm0_state[6:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN115 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":90:29:90:41|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z5(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=21  set on top level netlist eSRAM_eNVM_access_top


Clock Summary
**************

Start                                                   Requested     Requested     Clock        Clock              
Clock                                                   Frequency     Period        Type         Group              
--------------------------------------------------------------------------------------------------------------------
System                                                  1.0 MHz       1000.000      system       system_clkgroup    
eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
====================================================================================================================

@W: MT530 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Found inferred clock eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock which controls 328 sequential elements including AHB_IF_0.VALID. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\synthesis\eSRAM_eNVM_access_top.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 140MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Aug 05 13:48:18 2014

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 004R, Built May 28 2014 16:50:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

@W: MO111 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\fabosc_0\esram_envm_access_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC) 
@W: MO111 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\fabosc_0\esram_envm_access_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC) 
@W: MO111 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\fabosc_0\esram_envm_access_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC) 
@W: MO111 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\fabosc_0\esram_envm_access_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module eSRAM_eNVM_access_FABOSC_0_OSC) 
@W: MO171 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 

Available hyper_sources - for debug and ip models
	None Found

@W: MO129 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance eSRAM_eNVM_access_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 138MB)

Encoding state machine ahb_fsm_current_state[6:0] (view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[30],  because it is equivalent to instance AHB_IF_0.HWDATA_int[28]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[28],  because it is equivalent to instance AHB_IF_0.HWDATA_int[26]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[26],  because it is equivalent to instance AHB_IF_0.HWDATA_int[25]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[25],  because it is equivalent to instance AHB_IF_0.HWDATA_int[22]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[22],  because it is equivalent to instance AHB_IF_0.HWDATA_int[19]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[19],  because it is equivalent to instance AHB_IF_0.HWDATA_int[18]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[18],  because it is equivalent to instance AHB_IF_0.HWDATA_int[16]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[16],  because it is equivalent to instance AHB_IF_0.HWDATA_int[13]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[13],  because it is equivalent to instance AHB_IF_0.HWDATA_int[12]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[12],  because it is equivalent to instance AHB_IF_0.HWDATA_int[11]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[11],  because it is equivalent to instance AHB_IF_0.HWDATA_int[10]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[7],  because it is equivalent to instance AHB_IF_0.HWDATA_int[10]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[6],  because it is equivalent to instance AHB_IF_0.HWDATA_int[10]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[7],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[12],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[16],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[19],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[25],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[28],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[30],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[26],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[22],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[18],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[13],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[11],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[10],  because it is equivalent to instance AHB_IF_0.HWDATA[6]
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing sequential instance HADDR[0] in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing sequential instance HADDR[1] in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing sequential instance HWDATA[6] in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing sequential instance HWDATA_int[10] in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1],  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v":82:4:82:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":233:0:233:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] in hierarchy view:work.eSRAM_eNVM_access(verilog) because there are no references to its outputs 
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31],  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28]
Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog))
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@W: MO160 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
Encoding state machine current_state[17:0] (view:work.eSRAM_eNVM_RW(verilog))
original code -> new code
   00000 -> 000000000000000001
   00001 -> 000000000000000010
   00010 -> 000000000000000100
   00011 -> 000000000000001000
   00100 -> 000000000000010000
   00101 -> 000000000000100000
   00110 -> 000000000001000000
   00111 -> 000000000010000000
   01000 -> 000000000100000000
   01001 -> 000000001000000000
   01010 -> 000000010000000000
   01011 -> 000000100000000000
   01100 -> 000001000000000000
   01101 -> 000010000000000000
   01110 -> 000100000000000000
   01111 -> 001000000000000000
   10000 -> 010000000000000000
   10001 -> 100000000000000000
@N:"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Found counter in view:work.eSRAM_eNVM_RW(verilog) inst addr_temp[31:2]
@N:"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Found counter in view:work.eSRAM_eNVM_RW(verilog) inst data[5:0]
@N:"e:\projects\igl2_esram_envm_rw_fabric\hdl\esram_envm_rw.v":80:0:80:5|Found counter in view:work.eSRAM_eNVM_RW(verilog) inst ram_waddr[4:0]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28],  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[1],  because it is equivalent to instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[9],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[14],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[15],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[17],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[20],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[21],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[23],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[24],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[29],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA_int[31],  because it is equivalent to instance AHB_IF_0.HWDATA_int[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[9],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[14],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[15],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[17],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[20],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[21],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[23],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[24],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[29],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@W: BN132 :"e:\projects\igl2_esram_envm_rw_fabric\hdl\ahb_if.v":81:0:81:5|Removing instance AHB_IF_0.HWDATA[31],  because it is equivalent to instance AHB_IF_0.HWDATA[8]
@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v":167:0:167:5|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[0] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 

Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N: BN362 :"e:\projects\igl2_esram_envm_rw_fabric\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v":452:4:452:9|Removing sequential instance eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.eSRAM_eNVM_access_top(verilog) because there are no references to its outputs 

Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 147MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -4.60ns		 349 /       254
------------------------------------------------------------




Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -4.60ns		 347 /       254
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -4.60ns		 347 /       254
------------------------------------------------------------

@N: FP130 |Promoting Net eSRAM_eNVM_access_0_HPMS_READY on CLKINT  I_14 

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 147MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 147MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 257 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================================================== Non-Gated/Non-Generated Clocks ===========================================================
Clock Tree ID     Driving Element                        Drive Element Type     Fanout     Sample Instance                                            
------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       eSRAM_eNVM_access_0.CCC_0.GL0_INST     CLKINT                 257        eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST
======================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base E:\projects\IGL2_eSRAM_eNVM_RW_Fabric\synthesis\eSRAM_eNVM_access_top.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 147MB)

Writing EDIF Netlist and constraint files
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
I-2013.09M-SP1-1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 147MB)

@W: MT246 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\esram_envm_access.v":794:9:794:20|Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"e:\projects\igl2_esram_envm_rw_fabric\component\work\esram_envm_access\ccc_0\esram_envm_access_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:eSRAM_eNVM_access_0.CCC_0.GL0_net"



##### START OF TIMING REPORT #####[
# Timing Report written on Tue Aug 05 13:48:21 2014
#


Top view:               eSRAM_eNVM_access_top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 3.043

                                                        Requested     Estimated      Requested     Estimated               Clock        Clock              
Starting Clock                                          Frequency     Frequency      Period        Period        Slack     Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     143.8 MHz      10.000        6.957         3.043     inferred     Inferred_clkgroup_0
System                                                  100.0 MHz     1029.4 MHz     10.000        0.971         9.029     system       system_clkgroup    
===========================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                             Ending                                               |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                               System                                               |  10.000      9.029  |  No paths    -      |  No paths    -      |  No paths    -    
eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock  System                                               |  10.000      8.921  |  No paths    -      |  No paths    -      |  No paths    -    
eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock  eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      3.044  |  No paths    -      |  No paths    -      |  No paths    -    
================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                                                Starting                                                                                                                    Arrival          
Instance                                                                        Reference                                               Type        Pin                Net                                  Time        Slack
                                                                                Clock                                                                                                                                        
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_READYOUT     CoreAHBLite_0_AHBmslave16_HREADY     2.915       3.043
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  masterRegAddrSel                     0.094       3.670
AHB_IF_0.HTRANS_1[1]                                                            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  AHB_IF_0_BIF_1_HTRANS[1]             0.094       3.997
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  regHTRANS                            0.094       4.087
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  m0s16DataSel                         0.094       4.128
AHB_IF_0.AHB_BUSY                                                               eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  AHB_IF_0_AHB_BUSY                    0.076       4.217
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[3]                       0.094       4.355
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[8]                       0.094       4.356
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[1]                       0.094       4.361
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[7]       eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         Q                  SDATASELInt[7]                       0.094       4.400
=============================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                            Starting                                                                                          Required          
Instance                                                                    Reference                                               Type        Pin              Net          Time         Slack
                                                                            Clock                                                                                                               
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                 eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     MSS_010     F_FM0_TRANS1     N_38_i_0     9.012        3.043
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[2]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[3]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[4]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[5]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[6]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[7]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[8]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[9]      eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[10]     eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN               N_49_i_0     9.707        3.440
================================================================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.988
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.012

    - Propagation time:                      5.968
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     3.044

    Number of logic level(s):                2
    Starting point:                          eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT
    Ending point:                            eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST / F_FM0_TRANS1
    The start point is clocked by            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            eSRAM_eNVM_access_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                                                                                    Pin                Pin               Arrival     No. of    
Name                                                                                                                  Type        Name               Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                                                           MSS_010     F_FM0_READYOUT     Out     2.915     2.915       -         
CoreAHBLite_0_AHBmslave16_HREADY                                                                                      Net         -                  -       0.990     -           13        
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMNextState_RNI1S9H               CFG3        B                  In      -         3.905       -         
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMNextState_RNI1S9H               CFG3        Y                  Out     0.133     4.038       -         
N_39                                                                                                                  Net         -                  -       0.548     -           2         
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState_ns_i_a2_RNIH0SB1[0]     CFG4        D                  In      -         4.586       -         
eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState_ns_i_a2_RNIH0SB1[0]     CFG4        Y                  Out     0.411     4.997       -         
N_38_i_0                                                                                                              Net         -                  -       0.971     -           1         
eSRAM_eNVM_access_0.eSRAM_eNVM_access_HPMS_0.MSS_ADLIB_INST                                                           MSS_010     F_FM0_TRANS1       In      -         5.968       -         
=============================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.956 is 4.447(63.9%) logic and 2.510(36.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                  Starting                                                                                           Arrival          
Instance                                          Reference     Type               Pin        Net                                                    Time        Slack
                                                  Clock                                                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.FABOSC_0.I_RCOSC_25_50MHZ     System        RCOSC_25_50MHZ     CLKOUT     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       9.029
======================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                       Starting                                                                                         Required          
Instance                               Reference     Type     Pin                Net                                                    Time         Slack
                                       Clock                                                                                                              
----------------------------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.CCC_0.CCC_INST     System        CCC      RCOSC_25_50MHZ     FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     10.000       9.029
==========================================================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.971
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 9.029

    Number of logic level(s):                0
    Starting point:                          eSRAM_eNVM_access_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT
    Ending point:                            eSRAM_eNVM_access_0.CCC_0.CCC_INST / RCOSC_25_50MHZ
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                                            Pin                Pin               Arrival     No. of    
Name                                                   Type               Name               Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
eSRAM_eNVM_access_0.FABOSC_0.I_RCOSC_25_50MHZ          RCOSC_25_50MHZ     CLKOUT             Out     0.000     0.000       -         
FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     Net                -                  -       0.971     -           1         
eSRAM_eNVM_access_0.CCC_0.CCC_INST                     CCC                RCOSC_25_50MHZ     In      -         0.971       -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for eSRAM_eNVM_access_top 

Mapping to part: m2gl010tfbga484-1
Cell usage:
CCC             1 use
CLKINT          2 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
SYSRESET        1 use
CFG1           5 uses
CFG2           132 uses
CFG3           43 uses
CFG4           119 uses

Carry primitives used for arithmetic functions:
ARI1           43 uses


Sequential Cells: 
SLE            254 uses

DSP Blocks:    0

I/O ports: 11
I/O primitives: 10
INBUF          2 uses
OUTBUF         8 uses


Global Clock Buffers: 2


RAM/ROM usage summary
Block Rams (RAM1K18) : 1

Total LUTs:    342

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 51MB peak: 147MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Tue Aug 05 13:48:21 2014

###########################################################]
