`timescale 1 ns/100 ps
// Version: v11.7 11.7.0.119


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_075(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM(
       RD_c,
       eSRAM_eNVM_RW_0_ram_wdata,
       eSRAM_eNVM_RW_0_ram_waddr,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_RW_0_ram_wen
    );
output [7:0] RD_c;
input  [31:0] eSRAM_eNVM_RW_0_ram_wdata;
input  [4:0] eSRAM_eNVM_RW_0_ram_waddr;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  eSRAM_eNVM_RW_0_ram_wen;

    wire VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    RAM1K18 eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM_R0C0 (.A_DOUT({nc0, 
        nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17}), .B_DOUT({nc18, nc19, nc20, 
        nc21, nc22, nc23, nc24, nc25, nc26, nc27, RD_c[7], RD_c[6], 
        RD_c[5], RD_c[4], RD_c[3], RD_c[2], RD_c[1], RD_c[0]}), .BUSY()
        , .A_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .A_DOUT_CLK(VCC_net_1)
        , .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({
        GND_net_1, VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, 
        eSRAM_eNVM_RW_0_ram_wdata[31], eSRAM_eNVM_RW_0_ram_wdata[30], 
        eSRAM_eNVM_RW_0_ram_wdata[29], eSRAM_eNVM_RW_0_ram_wdata[28], 
        eSRAM_eNVM_RW_0_ram_wdata[27], eSRAM_eNVM_RW_0_ram_wdata[26], 
        eSRAM_eNVM_RW_0_ram_wdata[25], eSRAM_eNVM_RW_0_ram_wdata[24], 
        GND_net_1, eSRAM_eNVM_RW_0_ram_wdata[23], 
        eSRAM_eNVM_RW_0_ram_wdata[22], eSRAM_eNVM_RW_0_ram_wdata[21], 
        eSRAM_eNVM_RW_0_ram_wdata[20], eSRAM_eNVM_RW_0_ram_wdata[19], 
        eSRAM_eNVM_RW_0_ram_wdata[18], eSRAM_eNVM_RW_0_ram_wdata[17], 
        eSRAM_eNVM_RW_0_ram_wdata[16]}), .A_ADDR({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .A_WEN({VCC_net_1, VCC_net_1}), .B_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        eSRAM_eNVM_RW_0_ram_wen, VCC_net_1, VCC_net_1}), 
        .B_DOUT_ARST_N(VCC_net_1), .B_DOUT_SRST_N(VCC_net_1), .B_DIN({
        GND_net_1, eSRAM_eNVM_RW_0_ram_wdata[15], 
        eSRAM_eNVM_RW_0_ram_wdata[14], eSRAM_eNVM_RW_0_ram_wdata[13], 
        eSRAM_eNVM_RW_0_ram_wdata[12], eSRAM_eNVM_RW_0_ram_wdata[11], 
        eSRAM_eNVM_RW_0_ram_wdata[10], eSRAM_eNVM_RW_0_ram_wdata[9], 
        eSRAM_eNVM_RW_0_ram_wdata[8], GND_net_1, 
        eSRAM_eNVM_RW_0_ram_wdata[7], eSRAM_eNVM_RW_0_ram_wdata[6], 
        eSRAM_eNVM_RW_0_ram_wdata[5], eSRAM_eNVM_RW_0_ram_wdata[4], 
        eSRAM_eNVM_RW_0_ram_wdata[3], eSRAM_eNVM_RW_0_ram_wdata[2], 
        eSRAM_eNVM_RW_0_ram_wdata[1], eSRAM_eNVM_RW_0_ram_wdata[0]}), 
        .B_ADDR({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        eSRAM_eNVM_RW_0_ram_waddr[4], eSRAM_eNVM_RW_0_ram_waddr[3], 
        eSRAM_eNVM_RW_0_ram_waddr[2], eSRAM_eNVM_RW_0_ram_waddr[1], 
        eSRAM_eNVM_RW_0_ram_waddr[0], GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .B_WEN({VCC_net_1, VCC_net_1}), .A_EN(
        VCC_net_1), .A_DOUT_LAT(VCC_net_1), .A_WIDTH({VCC_net_1, 
        GND_net_1, VCC_net_1}), .A_WMODE(GND_net_1), .B_EN(VCC_net_1), 
        .B_DOUT_LAT(VCC_net_1), .B_WIDTH({VCC_net_1, GND_net_1, 
        VCC_net_1}), .B_WMODE(GND_net_1), .SII_LOCK(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module CoreResetP_Z6(
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       SYSRESET_POR,
       eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F,
       eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N
    );
output eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  SYSRESET_POR;
input  eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F;
input  eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N;

    wire MSS_HPMS_READY_int_net_1, mss_ready_select_net_1, VCC_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        GND_net_1, mss_ready_state_net_1, RESET_N_M2F_clk_base_net_1, 
        POWER_ON_RESET_N_q1_net_1, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, MSS_HPMS_READY_int_4_net_1;
    
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_clk_base_net_1));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        SYSRESET_POR), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1)
        , .LAT(GND_net_1), .Q(POWER_ON_RESET_N_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(mss_ready_select4_net_1), 
        .ALn(POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_select_net_1));
    CLKINT MSS_HPMS_READY_int_RNISI68 (.A(MSS_HPMS_READY_int_net_1), 
        .Y(eSRAM_eNVM_access_0_MSS_READY));
    GND GND (.Y(GND_net_1));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(RESET_N_M2F_clk_base_net_1)
        , .ALn(POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    VCC VCC (.Y(VCC_net_1));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_q1_net_1));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FIC_2_APB_M_PRESET_N_clk_base_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        SYSRESET_POR), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1)
        , .LAT(GND_net_1), .Q(POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FIC_2_APB_M_PRESET_N_q1_net_1));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       SDATASELInt_13,
       SDATASELInt_12,
       SDATASELInt_8,
       SDATASELInt_2,
       SDATASELInt_11,
       SDATASELInt_6,
       SDATASELInt_4,
       SDATASELInt_0,
       SDATASELInt_14,
       SDATASELInt_10,
       SDATASELInt_9,
       SDATASELInt_7,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       defSlaveSMNextState,
       defSlaveSMNextState_0_o2,
       CoreAHBLite_0_AHBmslave16_HREADY,
       m0s16DataSel,
       N_165_i_0
    );
input  SDATASELInt_13;
input  SDATASELInt_12;
input  SDATASELInt_8;
input  SDATASELInt_2;
input  SDATASELInt_11;
input  SDATASELInt_6;
input  SDATASELInt_4;
input  SDATASELInt_0;
input  SDATASELInt_14;
input  SDATASELInt_10;
input  SDATASELInt_9;
input  SDATASELInt_7;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output defSlaveSMNextState;
output defSlaveSMNextState_0_o2;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  m0s16DataSel;
output N_165_i_0;

    wire defSlaveSMCurrentState_net_1, VCC_net_1, GND_net_1, 
        defSlaveSMNextState_0_o2_7_net_1, 
        defSlaveSMNextState_0_o2_8_net_1, 
        defSlaveSMNextState_0_o2_6_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hFFFE) )  defSlaveSMNextState_0_o2_6 (.A(
        SDATASELInt_14), .B(SDATASELInt_10), .C(SDATASELInt_9), .D(
        SDATASELInt_7), .Y(defSlaveSMNextState_0_o2_6_net_1));
    CFG4 #( .INIT(16'h00EF) )  defSlaveSMNextState_0_a2_RNIHN8M (.A(
        defSlaveSMNextState_0_o2), .B(CoreAHBLite_0_AHBmslave16_HREADY)
        , .C(m0s16DataSel), .D(defSlaveSMNextState), .Y(N_165_i_0));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hFFFE) )  defSlaveSMNextState_0_o2_8 (.A(
        SDATASELInt_13), .B(SDATASELInt_12), .C(SDATASELInt_8), .D(
        SDATASELInt_2), .Y(defSlaveSMNextState_0_o2_8_net_1));
    CFG4 #( .INIT(16'h0F0E) )  defSlaveSMNextState_0_a2 (.A(
        defSlaveSMNextState_0_o2_7_net_1), .B(
        defSlaveSMNextState_0_o2_8_net_1), .C(
        defSlaveSMCurrentState_net_1), .D(
        defSlaveSMNextState_0_o2_6_net_1), .Y(defSlaveSMNextState));
    CFG4 #( .INIT(16'hFFFE) )  defSlaveSMNextState_0_o2_7 (.A(
        SDATASELInt_11), .B(SDATASELInt_6), .C(SDATASELInt_4), .D(
        SDATASELInt_0), .Y(defSlaveSMNextState_0_o2_7_net_1));
    CFG3 #( .INIT(8'hFE) )  defSlaveSMNextState_0_o2_inst_1 (.A(
        defSlaveSMNextState_0_o2_8_net_1), .B(
        defSlaveSMNextState_0_o2_7_net_1), .C(
        defSlaveSMNextState_0_o2_6_net_1), .Y(defSlaveSMNextState_0_o2)
        );
    SLE defSlaveSMCurrentState (.D(defSlaveSMNextState), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState_net_1));
    
endmodule


module COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0(
       masterDataInProg,
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       regHADDR_22,
       regHADDR_23,
       regHADDR_24,
       regHADDR_25,
       regHADDR_7,
       regHADDR_8,
       regHADDR_9,
       regHADDR_10,
       regHADDR_11,
       regHADDR_12,
       regHADDR_13,
       regHADDR_14,
       regHADDR_15,
       regHADDR_16,
       regHADDR_17,
       regHADDR_18,
       regHADDR_19,
       regHADDR_20,
       regHADDR_21,
       regHADDR_0,
       regHADDR_1,
       regHADDR_2,
       regHADDR_3,
       regHADDR_4,
       regHADDR_5,
       regHADDR_6,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       m0s16DataSel,
       N_90,
       regHWRITE,
       AHB_IF_0_BIF_1_HWRITE,
       regHTRANS,
       masterRegAddrSel,
       CoreAHBLite_0_AHBmslave16_HREADY,
       defSlaveSMNextState,
       HREADY_M_iv,
       defSlaveSMNextState_0_o2,
       N_98,
       N_99,
       N_154,
       N_188
    );
input  [0:0] masterDataInProg;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
output regHADDR_22;
output regHADDR_23;
output regHADDR_24;
output regHADDR_25;
output regHADDR_7;
output regHADDR_8;
output regHADDR_9;
output regHADDR_10;
output regHADDR_11;
output regHADDR_12;
output regHADDR_13;
output regHADDR_14;
output regHADDR_15;
output regHADDR_16;
output regHADDR_17;
output regHADDR_18;
output regHADDR_19;
output regHADDR_20;
output regHADDR_21;
output regHADDR_0;
output regHADDR_1;
output regHADDR_2;
output regHADDR_3;
output regHADDR_4;
output regHADDR_5;
output regHADDR_6;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output m0s16DataSel;
output N_90;
output regHWRITE;
input  AHB_IF_0_BIF_1_HWRITE;
output regHTRANS;
output masterRegAddrSel;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output defSlaveSMNextState;
output HREADY_M_iv;
output defSlaveSMNextState_0_o2;
output N_98;
output N_99;
output N_154;
input  N_188;

    wire VCC_net_1, masterAddrClockEnable, GND_net_1, 
        \regHADDR[29]_net_1 , \regHADDR[30]_net_1 , 
        \SDATASELInt[12]_net_1 , \SADDRSEL[12] , N_165_i_0, 
        \SDATASELInt[13]_net_1 , \SADDRSEL[13] , 
        \SDATASELInt[14]_net_1 , \SADDRSEL[14] , 
        \SDATASELInt[15]_net_1 , \SADDRSEL[15] , 
        \SDATASELInt[1]_net_1 , \SADDRSEL[1] , \SDATASELInt[3]_net_1 , 
        \SADDRSEL[3] , \SDATASELInt[5]_net_1 , \SADDRSEL[5] , 
        \SDATASELInt[7]_net_1 , \SADDRSEL[7] , \SDATASELInt[8]_net_1 , 
        \SADDRSEL[8] , \SDATASELInt[9]_net_1 , \SADDRSEL[9] , 
        \SDATASELInt[10]_net_1 , \SADDRSEL[10] , 
        \SDATASELInt[11]_net_1 , \SADDRSEL[11] , d_masterRegAddrSel, 
        HREADY_M_iv_0_o2_0_o2_1_net_1, N_148, N_151, 
        masterAddrClockEnable_0_a2_0_net_1, N_21;
    
    CFG3 #( .INIT(8'hD8) )  \PREGATEDHADDR_i_m2[29]  (.A(
        masterRegAddrSel), .B(\regHADDR[29]_net_1 ), .C(
        AHB_IF_0_BIF_1_HADDR[29]), .Y(N_99));
    SLE \regHADDR[21]  (.D(AHB_IF_0_BIF_1_HADDR[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_19));
    SLE \regHADDR[15]  (.D(AHB_IF_0_BIF_1_HADDR[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_13));
    SLE \regHADDR[30]  (.D(AHB_IF_0_BIF_1_HADDR[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[30]_net_1 ));
    SLE \regHADDR[7]  (.D(AHB_IF_0_BIF_1_HADDR[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_5));
    CFG4 #( .INIT(16'h0010) )  masterAddrClockEnable_0_a2_0 (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(masterRegAddrSel), .C(
        AHB_IF_0_BIF_1_HTRANS[1]), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        masterAddrClockEnable_0_a2_0_net_1));
    SLE \regHADDR[9]  (.D(AHB_IF_0_BIF_1_HADDR[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_7));
    CFG4 #( .INIT(16'h2000) )  \SADDRSEL_0_a2[3]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        N_148), .D(N_99), .Y(\SADDRSEL[3] ));
    SLE masterRegAddrSel_inst_1 (.D(d_masterRegAddrSel), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        masterRegAddrSel));
    CFG3 #( .INIT(8'h80) )  \SADDRSEL_0_a2[15]  (.A(N_99), .B(N_21), 
        .C(N_98), .Y(\SADDRSEL[15] ));
    SLE regHTRANS_inst_1 (.D(VCC_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHTRANS));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'h0400) )  \SADDRSEL_0_a2[12]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(N_151), .C(
        AHB_IF_0_BIF_1_HADDR[29]), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        \SADDRSEL[12] ));
    CFG2 #( .INIT(4'h4) )  HREADY_M_iv_0_o2_0_o2_1 (.A(
        defSlaveSMNextState_0_o2), .B(m0s16DataSel), .Y(
        HREADY_M_iv_0_o2_0_o2_1_net_1));
    SLE \regHADDR[29]  (.D(AHB_IF_0_BIF_1_HADDR[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \regHADDR[29]_net_1 ));
    SLE \regHADDR[24]  (.D(AHB_IF_0_BIF_1_HADDR[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_22));
    CFG4 #( .INIT(16'h4000) )  \SADDRSEL_0_a2[14]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(N_151), .C(
        AHB_IF_0_BIF_1_HADDR[29]), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        \SADDRSEL[14] ));
    CFG4 #( .INIT(16'h4000) )  \SADDRSEL_0_a2[10]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        N_148), .D(N_99), .Y(\SADDRSEL[10] ));
    SLE \regHADDR[10]  (.D(AHB_IF_0_BIF_1_HADDR[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_8));
    CFG4 #( .INIT(16'h0040) )  \SADDRSEL_0_a2[8]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        N_148), .D(N_99), .Y(\SADDRSEL[8] ));
    SLE \regHADDR[13]  (.D(AHB_IF_0_BIF_1_HADDR[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_11));
    SLE \regHADDR[12]  (.D(AHB_IF_0_BIF_1_HADDR[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_10));
    SLE \regHADDR[5]  (.D(AHB_IF_0_BIF_1_HADDR[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_3));
    SLE \regHADDR[2]  (.D(AHB_IF_0_BIF_1_HADDR[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_0));
    SLE \SDATASELInt[15]  (.D(\SADDRSEL[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[15]_net_1 ));
    CFG4 #( .INIT(16'h00D5) )  HREADY_M_iv_0_o2_0_o2 (.A(
        HREADY_M_iv_0_o2_0_o2_1_net_1), .B(
        CoreAHBLite_0_AHBmslave16_HREADY), .C(masterDataInProg[0]), .D(
        defSlaveSMNextState), .Y(HREADY_M_iv));
    SLE \SDATASELInt[14]  (.D(\SADDRSEL[14] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[14]_net_1 ));
    SLE \regHADDR[8]  (.D(AHB_IF_0_BIF_1_HADDR[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_6));
    SLE \regHADDR[25]  (.D(AHB_IF_0_BIF_1_HADDR[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_23));
    GND GND (.Y(GND_net_1));
    SLE \regHADDR[17]  (.D(AHB_IF_0_BIF_1_HADDR[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_15));
    CFG3 #( .INIT(8'hD8) )  GATEDHTRANS_i_m3 (.A(masterRegAddrSel), .B(
        regHTRANS), .C(AHB_IF_0_BIF_1_HTRANS[1]), .Y(N_154));
    CFG3 #( .INIT(8'h08) )  \SADDRSEL_0_a2_1[5]  (.A(N_98), .B(
        AHB_IF_0_BIF_1_HTRANS[1]), .C(masterRegAddrSel), .Y(N_151));
    CFG4 #( .INIT(16'h0080) )  \SADDRSEL_0_a2[7]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(N_151), .C(
        AHB_IF_0_BIF_1_HADDR[29]), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        \SADDRSEL[7] ));
    SLE \regHADDR[6]  (.D(AHB_IF_0_BIF_1_HADDR[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_4));
    SLE \regHADDR[16]  (.D(AHB_IF_0_BIF_1_HADDR[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_14));
    SLE \SDATASELInt[13]  (.D(\SADDRSEL[13] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[13]_net_1 ));
    CFG3 #( .INIT(8'h08) )  \SADDRSEL_0_a2[11]  (.A(N_99), .B(N_21), 
        .C(N_98), .Y(\SADDRSEL[11] ));
    SLE regHWRITE_inst_1 (.D(AHB_IF_0_BIF_1_HWRITE), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHWRITE));
    SLE \SDATASELInt[9]  (.D(\SADDRSEL[9] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[9]_net_1 ));
    SLE \SDATASELInt[1]  (.D(\SADDRSEL[1] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[1]_net_1 ));
    SLE \SDATASELInt[12]  (.D(\SADDRSEL[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[12]_net_1 ));
    SLE \regHADDR[11]  (.D(AHB_IF_0_BIF_1_HADDR[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_9));
    CFG4 #( .INIT(16'h0800) )  \SADDRSEL_0_a2_0[9]  (.A(
        AHB_IF_0_BIF_1_HADDR[31]), .B(AHB_IF_0_BIF_1_HADDR[28]), .C(
        masterRegAddrSel), .D(N_154), .Y(N_21));
    SLE \SDATASELInt[5]  (.D(\SADDRSEL[5] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[5]_net_1 ));
    CFG4 #( .INIT(16'hDCCC) )  d_masterRegAddrSel_0 (.A(N_188), .B(
        masterAddrClockEnable), .C(masterRegAddrSel), .D(N_90), .Y(
        d_masterRegAddrSel));
    SLE \regHADDR[3]  (.D(AHB_IF_0_BIF_1_HADDR[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_1));
    CFG4 #( .INIT(16'h0008) )  \SADDRSEL_0_a2[5]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(N_151), .C(
        AHB_IF_0_BIF_1_HADDR[29]), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(
        \SADDRSEL[5] ));
    SLE \SDATASELInt[3]  (.D(\SADDRSEL[3] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[3]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \SADDRSEL_0_a2_0[8]  (.A(N_98), .B(
        AHB_IF_0_BIF_1_HTRANS[1]), .C(masterRegAddrSel), .Y(N_148));
    SLE \regHADDR[20]  (.D(AHB_IF_0_BIF_1_HADDR[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_18));
    SLE \regHADDR[23]  (.D(AHB_IF_0_BIF_1_HADDR[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_21));
    SLE \regHADDR[22]  (.D(AHB_IF_0_BIF_1_HADDR[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_20));
    SLE \SDATASELInt[7]  (.D(\SADDRSEL[7] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[7]_net_1 ));
    CFG4 #( .INIT(16'h0020) )  \SADDRSEL_0_a2[1]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HADDR[31]), .C(
        N_148), .D(N_99), .Y(\SADDRSEL[1] ));
    CFG3 #( .INIT(8'h40) )  \SADDRSEL_0_a2[13]  (.A(N_99), .B(N_21), 
        .C(N_98), .Y(\SADDRSEL[13] ));
    SLE \regHADDR[19]  (.D(AHB_IF_0_BIF_1_HADDR[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_17));
    CFG4 #( .INIT(16'hF100) )  GATEDHTRANS_i_m3_RNIFLL31 (.A(
        AHB_IF_0_BIF_1_HADDR[31]), .B(AHB_IF_0_BIF_1_HADDR[28]), .C(
        masterRegAddrSel), .D(N_154), .Y(N_90));
    SLE \regHADDR[14]  (.D(AHB_IF_0_BIF_1_HADDR[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_12));
    SLE \regHADDR[27]  (.D(AHB_IF_0_BIF_1_HADDR[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_25));
    SLE \SDATASELInt[16]  (.D(N_90), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(m0s16DataSel));
    SLE \regHADDR[18]  (.D(AHB_IF_0_BIF_1_HADDR[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_16));
    SLE \SDATASELInt[11]  (.D(\SADDRSEL[11] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[11]_net_1 ));
    SLE \SDATASELInt[8]  (.D(\SADDRSEL[8] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[8]_net_1 ));
    SLE \regHADDR[4]  (.D(AHB_IF_0_BIF_1_HADDR[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_2));
    SLE \regHADDR[26]  (.D(AHB_IF_0_BIF_1_HADDR[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(masterAddrClockEnable), 
        .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(regHADDR_24));
    SLE \SDATASELInt[10]  (.D(\SADDRSEL[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_165_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[10]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \PREGATEDHADDR_i_m2[30]  (.A(
        masterRegAddrSel), .B(\regHADDR[30]_net_1 ), .C(
        AHB_IF_0_BIF_1_HADDR[30]), .Y(N_98));
    CFG3 #( .INIT(8'h08) )  masterAddrClockEnable_0_a2 (.A(HREADY_M_iv)
        , .B(masterAddrClockEnable_0_a2_0_net_1), .C(N_188), .Y(
        masterAddrClockEnable));
    CFG3 #( .INIT(8'h04) )  \SADDRSEL_0_a2[9]  (.A(N_99), .B(N_21), .C(
        N_98), .Y(\SADDRSEL[9] ));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (
        .SDATASELInt_13(\SDATASELInt[14]_net_1 ), .SDATASELInt_12(
        \SDATASELInt[13]_net_1 ), .SDATASELInt_8(
        \SDATASELInt[9]_net_1 ), .SDATASELInt_2(\SDATASELInt[3]_net_1 )
        , .SDATASELInt_11(\SDATASELInt[12]_net_1 ), .SDATASELInt_6(
        \SDATASELInt[7]_net_1 ), .SDATASELInt_4(\SDATASELInt[5]_net_1 )
        , .SDATASELInt_0(\SDATASELInt[1]_net_1 ), .SDATASELInt_14(
        \SDATASELInt[15]_net_1 ), .SDATASELInt_10(
        \SDATASELInt[11]_net_1 ), .SDATASELInt_9(
        \SDATASELInt[10]_net_1 ), .SDATASELInt_7(
        \SDATASELInt[8]_net_1 ), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .defSlaveSMNextState(
        defSlaveSMNextState), .defSlaveSMNextState_0_o2(
        defSlaveSMNextState_0_o2), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .m0s16DataSel(m0s16DataSel), 
        .N_165_i_0(N_165_i_0));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z4_1(
       regHADDR,
       arbRegSMCurrentState_0,
       AHB_IF_0_BIF_1_HADDR_29,
       AHB_IF_0_BIF_1_HADDR_26,
       AHB_IF_0_BIF_1_HADDR_18,
       AHB_IF_0_BIF_1_HADDR_17,
       AHB_IF_0_BIF_1_HADDR_16,
       AHB_IF_0_BIF_1_HADDR_15,
       AHB_IF_0_BIF_1_HADDR_14,
       AHB_IF_0_BIF_1_HADDR_13,
       AHB_IF_0_BIF_1_HADDR_12,
       AHB_IF_0_BIF_1_HADDR_11,
       AHB_IF_0_BIF_1_HADDR_10,
       AHB_IF_0_BIF_1_HADDR_9,
       AHB_IF_0_BIF_1_HADDR_8,
       AHB_IF_0_BIF_1_HADDR_7,
       AHB_IF_0_BIF_1_HADDR_6,
       AHB_IF_0_BIF_1_HADDR_5,
       AHB_IF_0_BIF_1_HADDR_4,
       AHB_IF_0_BIF_1_HADDR_3,
       AHB_IF_0_BIF_1_HADDR_2,
       AHB_IF_0_BIF_1_HADDR_1,
       AHB_IF_0_BIF_1_HADDR_0,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       N_160,
       CoreAHBLite_0_AHBmslave16_HREADY,
       N_188,
       N_90,
       N_155,
       N_154,
       N_152,
       masterRegAddrSel,
       N_50_i_0,
       N_98,
       N_93_i_0,
       N_99,
       N_91_i_0,
       N_48_i_0,
       N_89_i_0,
       N_87_i_0,
       N_85_i_0,
       N_83_i_0,
       N_81_i_0,
       N_79_i_0,
       N_77_i_0,
       N_75_i_0,
       N_73_i_0,
       N_71_i_0,
       N_69_i_0,
       N_67_i_0,
       N_65_i_0,
       N_63_i_0,
       N_61_i_0,
       N_59_i_0,
       N_57_i_0,
       N_55_i_0,
       N_53_i_0
    );
input  [20:2] regHADDR;
output arbRegSMCurrentState_0;
input  AHB_IF_0_BIF_1_HADDR_29;
input  AHB_IF_0_BIF_1_HADDR_26;
input  AHB_IF_0_BIF_1_HADDR_18;
input  AHB_IF_0_BIF_1_HADDR_17;
input  AHB_IF_0_BIF_1_HADDR_16;
input  AHB_IF_0_BIF_1_HADDR_15;
input  AHB_IF_0_BIF_1_HADDR_14;
input  AHB_IF_0_BIF_1_HADDR_13;
input  AHB_IF_0_BIF_1_HADDR_12;
input  AHB_IF_0_BIF_1_HADDR_11;
input  AHB_IF_0_BIF_1_HADDR_10;
input  AHB_IF_0_BIF_1_HADDR_9;
input  AHB_IF_0_BIF_1_HADDR_8;
input  AHB_IF_0_BIF_1_HADDR_7;
input  AHB_IF_0_BIF_1_HADDR_6;
input  AHB_IF_0_BIF_1_HADDR_5;
input  AHB_IF_0_BIF_1_HADDR_4;
input  AHB_IF_0_BIF_1_HADDR_3;
input  AHB_IF_0_BIF_1_HADDR_2;
input  AHB_IF_0_BIF_1_HADDR_1;
input  AHB_IF_0_BIF_1_HADDR_0;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output N_160;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output N_188;
input  N_90;
input  N_155;
input  N_154;
output N_152;
input  masterRegAddrSel;
output N_50_i_0;
input  N_98;
output N_93_i_0;
input  N_99;
output N_91_i_0;
output N_48_i_0;
output N_89_i_0;
output N_87_i_0;
output N_85_i_0;
output N_83_i_0;
output N_81_i_0;
output N_79_i_0;
output N_77_i_0;
output N_75_i_0;
output N_73_i_0;
output N_71_i_0;
output N_69_i_0;
output N_67_i_0;
output N_65_i_0;
output N_63_i_0;
output N_61_i_0;
output N_59_i_0;
output N_57_i_0;
output N_55_i_0;
output N_53_i_0;

    wire VCC_net_1, N_104_i_0, GND_net_1, 
        \arbRegSMCurrentState[1]_net_1 , N_106_i_0, 
        \arbRegSMCurrentState[5]_net_1 , N_66_i_0, 
        \arbRegSMCurrentState[9]_net_1 , N_104_i_0_0, 
        \arbRegSMCurrentState[13]_net_1 , N_102_i_0, N_110, N_142;
    
    CFG4 #( .INIT(16'h0E0F) )  \arbRegSMCurrentState_RNO[1]  (.A(
        arbRegSMCurrentState_0), .B(\arbRegSMCurrentState[1]_net_1 ), 
        .C(N_142), .D(N_110), .Y(N_106_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNITNI01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_0), .B(regHADDR[2]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_53_i_0));
    CFG3 #( .INIT(8'h20) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIT1VR[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_26), .B(masterRegAddrSel), .C(N_152), .Y(
        N_48_i_0));
    CFG4 #( .INIT(16'hFFFE) )  \arbRegSMCurrentState_RNIFG98[1]  (.A(
        \arbRegSMCurrentState[13]_net_1 ), .B(
        \arbRegSMCurrentState[9]_net_1 ), .C(
        \arbRegSMCurrentState[5]_net_1 ), .D(
        \arbRegSMCurrentState[1]_net_1 ), .Y(N_160));
    CFG4 #( .INIT(16'h01FF) )  \arbRegSMCurrentState_ns_i_0_o2_0[1]  (
        .A(\arbRegSMCurrentState[13]_net_1 ), .B(
        \arbRegSMCurrentState[9]_net_1 ), .C(
        \arbRegSMCurrentState[5]_net_1 ), .D(N_90), .Y(N_110));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI965A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_15), .B(regHADDR[17]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_83_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIDA5A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_17), .B(regHADDR[19]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_87_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI1SI01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_2), .B(regHADDR[4]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_57_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNITP4A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_9), .B(regHADDR[11]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_71_i_0));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[0]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_152), .Y(N_104_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIB6J01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_7), .B(regHADDR[9]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_67_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI3UI01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_3), .B(regHADDR[5]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_59_i_0));
    SLE \arbRegSMCurrentState[0]  (.D(N_104_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI745A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_14), .B(regHADDR[16]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_81_i_0));
    CFG3 #( .INIT(8'hC8) )  \arbRegSMCurrentState_RNI59S9[0]  (.A(
        N_160), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        arbRegSMCurrentState_0), .Y(N_188));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI72J01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_5), .B(regHADDR[7]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_63_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIVR4A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_10), .B(regHADDR[12]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_73_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI50J01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_4), .B(regHADDR[6]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_61_i_0));
    SLE \arbRegSMCurrentState[1]  (.D(N_106_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[1]_net_1 ));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_0_a2_RNIH38K[0]  
        (.A(N_152), .B(N_99), .Y(N_91_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNITR6A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_18), .B(regHADDR[20]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_89_i_0));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[13]  (.A(N_90), 
        .B(\arbRegSMCurrentState[13]_net_1 ), .Y(N_102_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIRN4A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_8), .B(regHADDR[10]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_69_i_0));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_ns_i_0_a2_RNI9S8K[0]  
        (.A(N_152), .B(N_98), .Y(N_93_i_0));
    SLE \arbRegSMCurrentState[9]  (.D(N_104_i_0_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[9]_net_1 ));
    CFG3 #( .INIT(8'h23) )  \arbRegSMCurrentState_ns_i_0_a2_0[1]  (.A(
        N_90), .B(CoreAHBLite_0_AHBmslave16_HREADY), .C(
        \arbRegSMCurrentState[1]_net_1 ), .Y(N_142));
    SLE \arbRegSMCurrentState[13]  (.D(N_102_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[13]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI525A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_13), .B(regHADDR[15]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_79_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI94J01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_6), .B(regHADDR[8]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_65_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIB85A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_16), .B(regHADDR[18]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_85_i_0));
    CFG3 #( .INIT(8'hDC) )  \arbRegSMCurrentState_ns_i_0_a2[0]  (.A(
        N_155), .B(arbRegSMCurrentState_0), .C(N_154), .Y(N_152));
    SLE \arbRegSMCurrentState[5]  (.D(N_66_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[5]_net_1 ));
    CFG3 #( .INIT(8'h20) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNINSVR[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_29), .B(masterRegAddrSel), .C(N_152), .Y(
        N_50_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNIVPI01[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_1), .B(regHADDR[3]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_55_i_0));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[5]  (.A(N_90), .B(
        \arbRegSMCurrentState[5]_net_1 ), .Y(N_66_i_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI305A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_12), .B(regHADDR[14]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_77_i_0));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[9]  (.A(N_90), .B(
        \arbRegSMCurrentState[9]_net_1 ), .Y(N_104_i_0_0));
    CFG4 #( .INIT(16'hC0A0) )  
        \arbRegSMCurrentState_ns_i_0_a2_RNI1U4A1[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_11), .B(regHADDR[13]), .C(N_152), .D(
        masterRegAddrSel), .Y(N_75_i_0));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_0(
       masterDataInProg,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       AHB_IF_0_BIF_1_HTRANS,
       CoreAHBLite_0_AHBmslave16_HADDR,
       regHADDR,
       AHB_IF_0_BIF_1_HADDR_29,
       AHB_IF_0_BIF_1_HADDR_26,
       AHB_IF_0_BIF_1_HADDR_25,
       AHB_IF_0_BIF_1_HADDR_24,
       AHB_IF_0_BIF_1_HADDR_23,
       AHB_IF_0_BIF_1_HADDR_22,
       AHB_IF_0_BIF_1_HADDR_21,
       AHB_IF_0_BIF_1_HADDR_20,
       AHB_IF_0_BIF_1_HADDR_19,
       AHB_IF_0_BIF_1_HADDR_18,
       AHB_IF_0_BIF_1_HADDR_17,
       AHB_IF_0_BIF_1_HADDR_16,
       AHB_IF_0_BIF_1_HADDR_15,
       AHB_IF_0_BIF_1_HADDR_14,
       AHB_IF_0_BIF_1_HADDR_13,
       AHB_IF_0_BIF_1_HADDR_12,
       AHB_IF_0_BIF_1_HADDR_11,
       AHB_IF_0_BIF_1_HADDR_10,
       AHB_IF_0_BIF_1_HADDR_9,
       AHB_IF_0_BIF_1_HADDR_8,
       AHB_IF_0_BIF_1_HADDR_7,
       AHB_IF_0_BIF_1_HADDR_6,
       AHB_IF_0_BIF_1_HADDR_5,
       AHB_IF_0_BIF_1_HADDR_4,
       AHB_IF_0_BIF_1_HADDR_3,
       AHB_IF_0_BIF_1_HADDR_2,
       AHB_IF_0_BIF_1_HADDR_1,
       AHB_IF_0_BIF_1_HADDR_0,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       N_152,
       CoreAHBLite_0_AHBmslave16_HREADY,
       regHTRANS,
       masterRegAddrSel,
       AHB_IF_0_BIF_1_HWRITE,
       regHWRITE,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       N_95_i_0,
       defSlaveSMNextState,
       m0s16DataSel,
       N_154,
       N_51_i_0,
       N_188,
       N_90,
       N_50_i_0,
       N_98,
       N_93_i_0,
       N_99,
       N_91_i_0,
       N_48_i_0,
       N_89_i_0,
       N_87_i_0,
       N_85_i_0,
       N_83_i_0,
       N_81_i_0,
       N_79_i_0,
       N_77_i_0,
       N_75_i_0,
       N_73_i_0,
       N_71_i_0,
       N_69_i_0,
       N_67_i_0,
       N_65_i_0,
       N_63_i_0,
       N_61_i_0,
       N_59_i_0,
       N_57_i_0,
       N_55_i_0,
       N_53_i_0
    );
output [0:0] masterDataInProg;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
output [27:21] CoreAHBLite_0_AHBmslave16_HADDR;
input  [27:2] regHADDR;
input  AHB_IF_0_BIF_1_HADDR_29;
input  AHB_IF_0_BIF_1_HADDR_26;
input  AHB_IF_0_BIF_1_HADDR_25;
input  AHB_IF_0_BIF_1_HADDR_24;
input  AHB_IF_0_BIF_1_HADDR_23;
input  AHB_IF_0_BIF_1_HADDR_22;
input  AHB_IF_0_BIF_1_HADDR_21;
input  AHB_IF_0_BIF_1_HADDR_20;
input  AHB_IF_0_BIF_1_HADDR_19;
input  AHB_IF_0_BIF_1_HADDR_18;
input  AHB_IF_0_BIF_1_HADDR_17;
input  AHB_IF_0_BIF_1_HADDR_16;
input  AHB_IF_0_BIF_1_HADDR_15;
input  AHB_IF_0_BIF_1_HADDR_14;
input  AHB_IF_0_BIF_1_HADDR_13;
input  AHB_IF_0_BIF_1_HADDR_12;
input  AHB_IF_0_BIF_1_HADDR_11;
input  AHB_IF_0_BIF_1_HADDR_10;
input  AHB_IF_0_BIF_1_HADDR_9;
input  AHB_IF_0_BIF_1_HADDR_8;
input  AHB_IF_0_BIF_1_HADDR_7;
input  AHB_IF_0_BIF_1_HADDR_6;
input  AHB_IF_0_BIF_1_HADDR_5;
input  AHB_IF_0_BIF_1_HADDR_4;
input  AHB_IF_0_BIF_1_HADDR_3;
input  AHB_IF_0_BIF_1_HADDR_2;
input  AHB_IF_0_BIF_1_HADDR_1;
input  AHB_IF_0_BIF_1_HADDR_0;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output N_152;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  regHTRANS;
input  masterRegAddrSel;
input  AHB_IF_0_BIF_1_HWRITE;
input  regHWRITE;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output N_95_i_0;
input  defSlaveSMNextState;
input  m0s16DataSel;
input  N_154;
output N_51_i_0;
output N_188;
input  N_90;
output N_50_i_0;
input  N_98;
output N_93_i_0;
input  N_99;
output N_91_i_0;
output N_48_i_0;
output N_89_i_0;
output N_87_i_0;
output N_85_i_0;
output N_83_i_0;
output N_81_i_0;
output N_79_i_0;
output N_77_i_0;
output N_75_i_0;
output N_73_i_0;
output N_71_i_0;
output N_69_i_0;
output N_67_i_0;
output N_65_i_0;
output N_63_i_0;
output N_61_i_0;
output N_59_i_0;
output N_57_i_0;
output N_55_i_0;
output N_53_i_0;

    wire VCC_net_1, GND_net_1, \arbRegSMCurrentState[0] , 
        \HSIZE_i_0[1]_net_1 , N_160, N_155, N_190;
    
    CFG3 #( .INIT(8'h23) )  \HSIZE_i_0_RNI5C9I[1]  (.A(
        \arbRegSMCurrentState[0] ), .B(\HSIZE_i_0[1]_net_1 ), .C(N_155)
        , .Y(N_95_i_0));
    CFG4 #( .INIT(16'h3100) )  HTRANS_i_a2_RNIL3RC (.A(N_155), .B(
        N_190), .C(\arbRegSMCurrentState[0] ), .D(N_154), .Y(N_51_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[22]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[22]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[22]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[20]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[20]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[20]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[23]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[23]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[23]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[12]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[12]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[12]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[29]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[29]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[29]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[10]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[10]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[10]));
    CFG2 #( .INIT(4'h2) )  HTRANS_i_a2 (.A(defSlaveSMNextState), .B(
        m0s16DataSel), .Y(N_190));
    CFG2 #( .INIT(4'h8) )  \HWDATA[31]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[31]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[31]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[13]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[13]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[13]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[0]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[0]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[0]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[24]  (.A(
        AHB_IF_0_BIF_1_HADDR_22), .B(regHADDR[24]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[24]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[4]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[4]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[4]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[28]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[28]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[28]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[19]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[19]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[19]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[27]  (.A(
        AHB_IF_0_BIF_1_HADDR_25), .B(regHADDR[27]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[27]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[25]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[25]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[25]));
    CFG4 #( .INIT(16'hC0A0) )  HWRITE_0_a2 (.A(AHB_IF_0_BIF_1_HWRITE), 
        .B(regHWRITE), .C(N_152), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HWRITE));
    CFG2 #( .INIT(4'h8) )  \HWDATA[24]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[24]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[24]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[27]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[27]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[27]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[18]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[18]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[18]));
    GND GND (.Y(GND_net_1));
    SLE \masterDataInProg[0]  (.D(N_152), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        CoreAHBLite_0_AHBmslave16_HREADY), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        masterDataInProg[0]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[15]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[15]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[15]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[22]  (.A(
        AHB_IF_0_BIF_1_HADDR_20), .B(regHADDR[22]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[22]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[14]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[14]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[14]));
    CFG4 #( .INIT(16'h0EFF) )  HTRANS_i_o3 (.A(AHB_IF_0_BIF_1_HADDR_29)
        , .B(AHB_IF_0_BIF_1_HADDR_26), .C(masterRegAddrSel), .D(N_160), 
        .Y(N_155));
    CFG2 #( .INIT(4'h8) )  \HWDATA[8]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[8]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[8]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[3]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[3]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[3]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[17]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[17]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[17]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[5]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[5]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[5]));
    CFG4 #( .INIT(16'h5503) )  \HSIZE_i_0[1]  (.A(regHTRANS), .B(
        AHB_IF_0_BIF_1_HTRANS[1]), .C(\arbRegSMCurrentState[0] ), .D(
        masterRegAddrSel), .Y(\HSIZE_i_0[1]_net_1 ));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[26]  (.A(
        AHB_IF_0_BIF_1_HADDR_24), .B(regHADDR[26]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[26]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[30]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[30]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[30]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[9]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[9]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[9]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[21]  (.A(
        AHB_IF_0_BIF_1_HADDR_19), .B(regHADDR[21]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[21]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[7]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[7]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[7]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[23]  (.A(
        AHB_IF_0_BIF_1_HADDR_21), .B(regHADDR[23]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[23]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[1]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[1]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[1]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[6]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[6]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[6]));
    COREAHBLITE_SLAVEARBITER_Z4_1 slave_arbiter (.regHADDR({
        regHADDR[20], regHADDR[19], regHADDR[18], regHADDR[17], 
        regHADDR[16], regHADDR[15], regHADDR[14], regHADDR[13], 
        regHADDR[12], regHADDR[11], regHADDR[10], regHADDR[9], 
        regHADDR[8], regHADDR[7], regHADDR[6], regHADDR[5], 
        regHADDR[4], regHADDR[3], regHADDR[2]}), 
        .arbRegSMCurrentState_0(\arbRegSMCurrentState[0] ), 
        .AHB_IF_0_BIF_1_HADDR_29(AHB_IF_0_BIF_1_HADDR_29), 
        .AHB_IF_0_BIF_1_HADDR_26(AHB_IF_0_BIF_1_HADDR_26), 
        .AHB_IF_0_BIF_1_HADDR_18(AHB_IF_0_BIF_1_HADDR_18), 
        .AHB_IF_0_BIF_1_HADDR_17(AHB_IF_0_BIF_1_HADDR_17), 
        .AHB_IF_0_BIF_1_HADDR_16(AHB_IF_0_BIF_1_HADDR_16), 
        .AHB_IF_0_BIF_1_HADDR_15(AHB_IF_0_BIF_1_HADDR_15), 
        .AHB_IF_0_BIF_1_HADDR_14(AHB_IF_0_BIF_1_HADDR_14), 
        .AHB_IF_0_BIF_1_HADDR_13(AHB_IF_0_BIF_1_HADDR_13), 
        .AHB_IF_0_BIF_1_HADDR_12(AHB_IF_0_BIF_1_HADDR_12), 
        .AHB_IF_0_BIF_1_HADDR_11(AHB_IF_0_BIF_1_HADDR_11), 
        .AHB_IF_0_BIF_1_HADDR_10(AHB_IF_0_BIF_1_HADDR_10), 
        .AHB_IF_0_BIF_1_HADDR_9(AHB_IF_0_BIF_1_HADDR_9), 
        .AHB_IF_0_BIF_1_HADDR_8(AHB_IF_0_BIF_1_HADDR_8), 
        .AHB_IF_0_BIF_1_HADDR_7(AHB_IF_0_BIF_1_HADDR_7), 
        .AHB_IF_0_BIF_1_HADDR_6(AHB_IF_0_BIF_1_HADDR_6), 
        .AHB_IF_0_BIF_1_HADDR_5(AHB_IF_0_BIF_1_HADDR_5), 
        .AHB_IF_0_BIF_1_HADDR_4(AHB_IF_0_BIF_1_HADDR_4), 
        .AHB_IF_0_BIF_1_HADDR_3(AHB_IF_0_BIF_1_HADDR_3), 
        .AHB_IF_0_BIF_1_HADDR_2(AHB_IF_0_BIF_1_HADDR_2), 
        .AHB_IF_0_BIF_1_HADDR_1(AHB_IF_0_BIF_1_HADDR_1), 
        .AHB_IF_0_BIF_1_HADDR_0(AHB_IF_0_BIF_1_HADDR_0), 
        .eSRAM_eNVM_access_0_MSS_READY(eSRAM_eNVM_access_0_MSS_READY), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .N_160(N_160), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .N_188(N_188), .N_90(N_90), 
        .N_155(N_155), .N_154(N_154), .N_152(N_152), .masterRegAddrSel(
        masterRegAddrSel), .N_50_i_0(N_50_i_0), .N_98(N_98), .N_93_i_0(
        N_93_i_0), .N_99(N_99), .N_91_i_0(N_91_i_0), .N_48_i_0(
        N_48_i_0), .N_89_i_0(N_89_i_0), .N_87_i_0(N_87_i_0), .N_85_i_0(
        N_85_i_0), .N_83_i_0(N_83_i_0), .N_81_i_0(N_81_i_0), .N_79_i_0(
        N_79_i_0), .N_77_i_0(N_77_i_0), .N_75_i_0(N_75_i_0), .N_73_i_0(
        N_73_i_0), .N_71_i_0(N_71_i_0), .N_69_i_0(N_69_i_0), .N_67_i_0(
        N_67_i_0), .N_65_i_0(N_65_i_0), .N_63_i_0(N_63_i_0), .N_61_i_0(
        N_61_i_0), .N_59_i_0(N_59_i_0), .N_57_i_0(N_57_i_0), .N_55_i_0(
        N_55_i_0), .N_53_i_0(N_53_i_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[21]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[21]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[21]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[26]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[26]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[26]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[2]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[2]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[2]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[11]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[11]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[11]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[16]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[16]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[16]));
    CFG4 #( .INIT(16'hC0A0) )  \HADDR_0_a2[25]  (.A(
        AHB_IF_0_BIF_1_HADDR_23), .B(regHADDR[25]), .C(N_152), .D(
        masterRegAddrSel), .Y(CoreAHBLite_0_AHBmslave16_HADDR[25]));
    
endmodule


module COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       m0s16DataSel,
       AHB_IF_0_BIF_1_HWRITE,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_iv,
       defSlaveSMNextState_0_o2,
       N_152,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       N_95_i_0,
       N_51_i_0,
       N_50_i_0,
       N_93_i_0,
       N_91_i_0,
       N_48_i_0,
       N_89_i_0,
       N_87_i_0,
       N_85_i_0,
       N_83_i_0,
       N_81_i_0,
       N_79_i_0,
       N_77_i_0,
       N_75_i_0,
       N_73_i_0,
       N_71_i_0,
       N_69_i_0,
       N_67_i_0,
       N_65_i_0,
       N_63_i_0,
       N_61_i_0,
       N_59_i_0,
       N_57_i_0,
       N_55_i_0,
       N_53_i_0
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:21] CoreAHBLite_0_AHBmslave16_HADDR;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output m0s16DataSel;
input  AHB_IF_0_BIF_1_HWRITE;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_iv;
output defSlaveSMNextState_0_o2;
output N_152;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output N_95_i_0;
output N_51_i_0;
output N_50_i_0;
output N_93_i_0;
output N_91_i_0;
output N_48_i_0;
output N_89_i_0;
output N_87_i_0;
output N_85_i_0;
output N_83_i_0;
output N_81_i_0;
output N_79_i_0;
output N_77_i_0;
output N_75_i_0;
output N_73_i_0;
output N_71_i_0;
output N_69_i_0;
output N_67_i_0;
output N_65_i_0;
output N_63_i_0;
output N_61_i_0;
output N_59_i_0;
output N_57_i_0;
output N_55_i_0;
output N_53_i_0;

    wire \regHADDR[24] , \regHADDR[25] , \regHADDR[26] , 
        \regHADDR[27] , \regHADDR[9] , \regHADDR[10] , \regHADDR[11] , 
        \regHADDR[12] , \regHADDR[13] , \regHADDR[14] , \regHADDR[15] , 
        \regHADDR[16] , \regHADDR[17] , \regHADDR[18] , \regHADDR[19] , 
        \regHADDR[20] , \regHADDR[21] , \regHADDR[22] , \regHADDR[23] , 
        \regHADDR[2] , \regHADDR[3] , \regHADDR[4] , \regHADDR[5] , 
        \regHADDR[6] , \regHADDR[7] , \regHADDR[8] , 
        \masterDataInProg[0] , N_90, regHWRITE, regHTRANS, 
        masterRegAddrSel, defSlaveSMNextState, N_98, N_99, N_154, 
        N_188, GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 masterstage_0 (
        .masterDataInProg({\masterDataInProg[0] }), 
        .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .regHADDR_22(\regHADDR[24] ), 
        .regHADDR_23(\regHADDR[25] ), .regHADDR_24(\regHADDR[26] ), 
        .regHADDR_25(\regHADDR[27] ), .regHADDR_7(\regHADDR[9] ), 
        .regHADDR_8(\regHADDR[10] ), .regHADDR_9(\regHADDR[11] ), 
        .regHADDR_10(\regHADDR[12] ), .regHADDR_11(\regHADDR[13] ), 
        .regHADDR_12(\regHADDR[14] ), .regHADDR_13(\regHADDR[15] ), 
        .regHADDR_14(\regHADDR[16] ), .regHADDR_15(\regHADDR[17] ), 
        .regHADDR_16(\regHADDR[18] ), .regHADDR_17(\regHADDR[19] ), 
        .regHADDR_18(\regHADDR[20] ), .regHADDR_19(\regHADDR[21] ), 
        .regHADDR_20(\regHADDR[22] ), .regHADDR_21(\regHADDR[23] ), 
        .regHADDR_0(\regHADDR[2] ), .regHADDR_1(\regHADDR[3] ), 
        .regHADDR_2(\regHADDR[4] ), .regHADDR_3(\regHADDR[5] ), 
        .regHADDR_4(\regHADDR[6] ), .regHADDR_5(\regHADDR[7] ), 
        .regHADDR_6(\regHADDR[8] ), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .m0s16DataSel(m0s16DataSel), 
        .N_90(N_90), .regHWRITE(regHWRITE), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .regHTRANS(regHTRANS), 
        .masterRegAddrSel(masterRegAddrSel), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .defSlaveSMNextState(
        defSlaveSMNextState), .HREADY_M_iv(HREADY_M_iv), 
        .defSlaveSMNextState_0_o2(defSlaveSMNextState_0_o2), .N_98(
        N_98), .N_99(N_99), .N_154(N_154), .N_188(N_188));
    COREAHBLITE_SLAVESTAGE_0s_0_0_0 slavestage_16 (.masterDataInProg({
        \masterDataInProg[0] }), .AHB_IF_0_BIF_1_HWDATA({
        AHB_IF_0_BIF_1_HWDATA[31], AHB_IF_0_BIF_1_HWDATA[30], 
        AHB_IF_0_BIF_1_HWDATA[29], AHB_IF_0_BIF_1_HWDATA[28], 
        AHB_IF_0_BIF_1_HWDATA[27], AHB_IF_0_BIF_1_HWDATA[26], 
        AHB_IF_0_BIF_1_HWDATA[25], AHB_IF_0_BIF_1_HWDATA[24], 
        AHB_IF_0_BIF_1_HWDATA[23], AHB_IF_0_BIF_1_HWDATA[22], 
        AHB_IF_0_BIF_1_HWDATA[21], AHB_IF_0_BIF_1_HWDATA[20], 
        AHB_IF_0_BIF_1_HWDATA[19], AHB_IF_0_BIF_1_HWDATA[18], 
        AHB_IF_0_BIF_1_HWDATA[17], AHB_IF_0_BIF_1_HWDATA[16], 
        AHB_IF_0_BIF_1_HWDATA[15], AHB_IF_0_BIF_1_HWDATA[14], 
        AHB_IF_0_BIF_1_HWDATA[13], AHB_IF_0_BIF_1_HWDATA[12], 
        AHB_IF_0_BIF_1_HWDATA[11], AHB_IF_0_BIF_1_HWDATA[10], 
        AHB_IF_0_BIF_1_HWDATA[9], AHB_IF_0_BIF_1_HWDATA[8], 
        AHB_IF_0_BIF_1_HWDATA[7], AHB_IF_0_BIF_1_HWDATA[6], 
        AHB_IF_0_BIF_1_HWDATA[5], AHB_IF_0_BIF_1_HWDATA[4], 
        AHB_IF_0_BIF_1_HWDATA[3], AHB_IF_0_BIF_1_HWDATA[2], 
        AHB_IF_0_BIF_1_HWDATA[1], AHB_IF_0_BIF_1_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .AHB_IF_0_BIF_1_HTRANS({
        AHB_IF_0_BIF_1_HTRANS[1]}), .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21]}), .regHADDR({
        \regHADDR[27] , \regHADDR[26] , \regHADDR[25] , \regHADDR[24] , 
        \regHADDR[23] , \regHADDR[22] , \regHADDR[21] , \regHADDR[20] , 
        \regHADDR[19] , \regHADDR[18] , \regHADDR[17] , \regHADDR[16] , 
        \regHADDR[15] , \regHADDR[14] , \regHADDR[13] , \regHADDR[12] , 
        \regHADDR[11] , \regHADDR[10] , \regHADDR[9] , \regHADDR[8] , 
        \regHADDR[7] , \regHADDR[6] , \regHADDR[5] , \regHADDR[4] , 
        \regHADDR[3] , \regHADDR[2] }), .AHB_IF_0_BIF_1_HADDR_29(
        AHB_IF_0_BIF_1_HADDR[31]), .AHB_IF_0_BIF_1_HADDR_26(
        AHB_IF_0_BIF_1_HADDR[28]), .AHB_IF_0_BIF_1_HADDR_25(
        AHB_IF_0_BIF_1_HADDR[27]), .AHB_IF_0_BIF_1_HADDR_24(
        AHB_IF_0_BIF_1_HADDR[26]), .AHB_IF_0_BIF_1_HADDR_23(
        AHB_IF_0_BIF_1_HADDR[25]), .AHB_IF_0_BIF_1_HADDR_22(
        AHB_IF_0_BIF_1_HADDR[24]), .AHB_IF_0_BIF_1_HADDR_21(
        AHB_IF_0_BIF_1_HADDR[23]), .AHB_IF_0_BIF_1_HADDR_20(
        AHB_IF_0_BIF_1_HADDR[22]), .AHB_IF_0_BIF_1_HADDR_19(
        AHB_IF_0_BIF_1_HADDR[21]), .AHB_IF_0_BIF_1_HADDR_18(
        AHB_IF_0_BIF_1_HADDR[20]), .AHB_IF_0_BIF_1_HADDR_17(
        AHB_IF_0_BIF_1_HADDR[19]), .AHB_IF_0_BIF_1_HADDR_16(
        AHB_IF_0_BIF_1_HADDR[18]), .AHB_IF_0_BIF_1_HADDR_15(
        AHB_IF_0_BIF_1_HADDR[17]), .AHB_IF_0_BIF_1_HADDR_14(
        AHB_IF_0_BIF_1_HADDR[16]), .AHB_IF_0_BIF_1_HADDR_13(
        AHB_IF_0_BIF_1_HADDR[15]), .AHB_IF_0_BIF_1_HADDR_12(
        AHB_IF_0_BIF_1_HADDR[14]), .AHB_IF_0_BIF_1_HADDR_11(
        AHB_IF_0_BIF_1_HADDR[13]), .AHB_IF_0_BIF_1_HADDR_10(
        AHB_IF_0_BIF_1_HADDR[12]), .AHB_IF_0_BIF_1_HADDR_9(
        AHB_IF_0_BIF_1_HADDR[11]), .AHB_IF_0_BIF_1_HADDR_8(
        AHB_IF_0_BIF_1_HADDR[10]), .AHB_IF_0_BIF_1_HADDR_7(
        AHB_IF_0_BIF_1_HADDR[9]), .AHB_IF_0_BIF_1_HADDR_6(
        AHB_IF_0_BIF_1_HADDR[8]), .AHB_IF_0_BIF_1_HADDR_5(
        AHB_IF_0_BIF_1_HADDR[7]), .AHB_IF_0_BIF_1_HADDR_4(
        AHB_IF_0_BIF_1_HADDR[6]), .AHB_IF_0_BIF_1_HADDR_3(
        AHB_IF_0_BIF_1_HADDR[5]), .AHB_IF_0_BIF_1_HADDR_2(
        AHB_IF_0_BIF_1_HADDR[4]), .AHB_IF_0_BIF_1_HADDR_1(
        AHB_IF_0_BIF_1_HADDR[3]), .AHB_IF_0_BIF_1_HADDR_0(
        AHB_IF_0_BIF_1_HADDR[2]), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .N_152(N_152), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .regHTRANS(regHTRANS), 
        .masterRegAddrSel(masterRegAddrSel), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .regHWRITE(regHWRITE), 
        .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .N_95_i_0(N_95_i_0), 
        .defSlaveSMNextState(defSlaveSMNextState), .m0s16DataSel(
        m0s16DataSel), .N_154(N_154), .N_51_i_0(N_51_i_0), .N_188(
        N_188), .N_90(N_90), .N_50_i_0(N_50_i_0), .N_98(N_98), 
        .N_93_i_0(N_93_i_0), .N_99(N_99), .N_91_i_0(N_91_i_0), 
        .N_48_i_0(N_48_i_0), .N_89_i_0(N_89_i_0), .N_87_i_0(N_87_i_0), 
        .N_85_i_0(N_85_i_0), .N_83_i_0(N_83_i_0), .N_81_i_0(N_81_i_0), 
        .N_79_i_0(N_79_i_0), .N_77_i_0(N_77_i_0), .N_75_i_0(N_75_i_0), 
        .N_73_i_0(N_73_i_0), .N_71_i_0(N_71_i_0), .N_69_i_0(N_69_i_0), 
        .N_67_i_0(N_67_i_0), .N_65_i_0(N_65_i_0), .N_63_i_0(N_63_i_0), 
        .N_61_i_0(N_61_i_0), .N_59_i_0(N_59_i_0), .N_57_i_0(N_57_i_0), 
        .N_55_i_0(N_55_i_0), .N_53_i_0(N_53_i_0));
    
endmodule


module CoreAHBLite_Z5(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       m0s16DataSel,
       AHB_IF_0_BIF_1_HWRITE,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_iv,
       defSlaveSMNextState_0_o2,
       N_152,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       N_95_i_0,
       N_51_i_0,
       N_50_i_0,
       N_93_i_0,
       N_91_i_0,
       N_48_i_0,
       N_89_i_0,
       N_87_i_0,
       N_85_i_0,
       N_83_i_0,
       N_81_i_0,
       N_79_i_0,
       N_77_i_0,
       N_75_i_0,
       N_73_i_0,
       N_71_i_0,
       N_69_i_0,
       N_67_i_0,
       N_65_i_0,
       N_63_i_0,
       N_61_i_0,
       N_59_i_0,
       N_57_i_0,
       N_55_i_0,
       N_53_i_0
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:21] CoreAHBLite_0_AHBmslave16_HADDR;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output m0s16DataSel;
input  AHB_IF_0_BIF_1_HWRITE;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_iv;
output defSlaveSMNextState_0_o2;
output N_152;
output CoreAHBLite_0_AHBmslave16_HWRITE;
output N_95_i_0;
output N_51_i_0;
output N_50_i_0;
output N_93_i_0;
output N_91_i_0;
output N_48_i_0;
output N_89_i_0;
output N_87_i_0;
output N_85_i_0;
output N_83_i_0;
output N_81_i_0;
output N_79_i_0;
output N_77_i_0;
output N_75_i_0;
output N_73_i_0;
output N_71_i_0;
output N_69_i_0;
output N_67_i_0;
output N_65_i_0;
output N_63_i_0;
output N_61_i_0;
output N_59_i_0;
output N_57_i_0;
output N_55_i_0;
output N_53_i_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s matrix4x16 (
        .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .AHB_IF_0_BIF_1_HWDATA({
        AHB_IF_0_BIF_1_HWDATA[31], AHB_IF_0_BIF_1_HWDATA[30], 
        AHB_IF_0_BIF_1_HWDATA[29], AHB_IF_0_BIF_1_HWDATA[28], 
        AHB_IF_0_BIF_1_HWDATA[27], AHB_IF_0_BIF_1_HWDATA[26], 
        AHB_IF_0_BIF_1_HWDATA[25], AHB_IF_0_BIF_1_HWDATA[24], 
        AHB_IF_0_BIF_1_HWDATA[23], AHB_IF_0_BIF_1_HWDATA[22], 
        AHB_IF_0_BIF_1_HWDATA[21], AHB_IF_0_BIF_1_HWDATA[20], 
        AHB_IF_0_BIF_1_HWDATA[19], AHB_IF_0_BIF_1_HWDATA[18], 
        AHB_IF_0_BIF_1_HWDATA[17], AHB_IF_0_BIF_1_HWDATA[16], 
        AHB_IF_0_BIF_1_HWDATA[15], AHB_IF_0_BIF_1_HWDATA[14], 
        AHB_IF_0_BIF_1_HWDATA[13], AHB_IF_0_BIF_1_HWDATA[12], 
        AHB_IF_0_BIF_1_HWDATA[11], AHB_IF_0_BIF_1_HWDATA[10], 
        AHB_IF_0_BIF_1_HWDATA[9], AHB_IF_0_BIF_1_HWDATA[8], 
        AHB_IF_0_BIF_1_HWDATA[7], AHB_IF_0_BIF_1_HWDATA[6], 
        AHB_IF_0_BIF_1_HWDATA[5], AHB_IF_0_BIF_1_HWDATA[4], 
        AHB_IF_0_BIF_1_HWDATA[3], AHB_IF_0_BIF_1_HWDATA[2], 
        AHB_IF_0_BIF_1_HWDATA[1], AHB_IF_0_BIF_1_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21]}), 
        .eSRAM_eNVM_access_0_MSS_READY(eSRAM_eNVM_access_0_MSS_READY), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .m0s16DataSel(m0s16DataSel), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_iv(HREADY_M_iv), 
        .defSlaveSMNextState_0_o2(defSlaveSMNextState_0_o2), .N_152(
        N_152), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .N_95_i_0(N_95_i_0), 
        .N_51_i_0(N_51_i_0), .N_50_i_0(N_50_i_0), .N_93_i_0(N_93_i_0), 
        .N_91_i_0(N_91_i_0), .N_48_i_0(N_48_i_0), .N_89_i_0(N_89_i_0), 
        .N_87_i_0(N_87_i_0), .N_85_i_0(N_85_i_0), .N_83_i_0(N_83_i_0), 
        .N_81_i_0(N_81_i_0), .N_79_i_0(N_79_i_0), .N_77_i_0(N_77_i_0), 
        .N_75_i_0(N_75_i_0), .N_73_i_0(N_73_i_0), .N_71_i_0(N_71_i_0), 
        .N_69_i_0(N_69_i_0), .N_67_i_0(N_67_i_0), .N_65_i_0(N_65_i_0), 
        .N_63_i_0(N_63_i_0), .N_61_i_0(N_61_i_0), .N_59_i_0(N_59_i_0), 
        .N_57_i_0(N_57_i_0), .N_55_i_0(N_55_i_0), .N_53_i_0(N_53_i_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_CCC_0_FCCC(
       eSRAM_eNVM_access_0_FIC_0_CLK,
       LOCK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output eSRAM_eNVM_access_0_FIC_0_CLK;
output LOCK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST (.A(GL0_net), .Y(eSRAM_eNVM_access_0_FIC_0_CLK));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6318C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(LOCK), 
        .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), .CLK2(VCC_net_1), 
        .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), .NGMUX1_SEL(
        GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(GND_net_1), 
        .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(VCC_net_1), 
        .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(VCC_net_1), 
        .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(VCC_net_1), 
        .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(VCC_net_1), 
        .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(VCC_net_1), 
        .PLL_POWERDOWN_N(VCC_net_1), .GPD0_ARST_N(VCC_net_1), 
        .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(VCC_net_1), .GPD3_ARST_N(
        VCC_net_1), .PRESET_N(GND_net_1), .PCLK(VCC_net_1), .PSEL(
        VCC_net_1), .PENABLE(VCC_net_1), .PWRITE(VCC_net_1), .PADDR({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .CLK0_PAD(GND_net_1), .CLK1_PAD(GND_net_1), .CLK2_PAD(
        GND_net_1), .CLK3_PAD(GND_net_1), .GL0(GL0_net), .GL1(), .GL2()
        , .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module eSRAM_eNVM_access_MSS(
       AHB_IF_0_BIF_1_HRDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       defSlaveSMNextState_0_o2,
       m0s16DataSel,
       eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N,
       CoreAHBLite_0_AHBmslave16_HREADY,
       eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F,
       N_53_i_0,
       N_55_i_0,
       N_57_i_0,
       N_59_i_0,
       N_61_i_0,
       N_63_i_0,
       N_65_i_0,
       N_67_i_0,
       N_69_i_0,
       N_71_i_0,
       N_73_i_0,
       N_75_i_0,
       N_77_i_0,
       N_79_i_0,
       N_81_i_0,
       N_83_i_0,
       N_85_i_0,
       N_87_i_0,
       N_89_i_0,
       N_48_i_0,
       N_91_i_0,
       N_93_i_0,
       N_50_i_0,
       N_152,
       N_95_i_0,
       N_51_i_0,
       CoreAHBLite_0_AHBmslave16_HWRITE,
       LOCK,
       eSRAM_eNVM_access_0_FIC_0_CLK
    );
output [31:0] AHB_IF_0_BIF_1_HRDATA;
input  [27:21] CoreAHBLite_0_AHBmslave16_HADDR;
input  [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  defSlaveSMNextState_0_o2;
input  m0s16DataSel;
output eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N;
inout  CoreAHBLite_0_AHBmslave16_HREADY;
output eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F;
input  N_53_i_0;
input  N_55_i_0;
input  N_57_i_0;
input  N_59_i_0;
input  N_61_i_0;
input  N_63_i_0;
input  N_65_i_0;
input  N_67_i_0;
input  N_69_i_0;
input  N_71_i_0;
input  N_73_i_0;
input  N_75_i_0;
input  N_77_i_0;
input  N_79_i_0;
input  N_81_i_0;
input  N_83_i_0;
input  N_85_i_0;
input  N_87_i_0;
input  N_89_i_0;
input  N_48_i_0;
input  N_91_i_0;
input  N_93_i_0;
input  N_50_i_0;
input  N_152;
input  N_95_i_0;
input  N_51_i_0;
input  CoreAHBLite_0_AHBmslave16_HWRITE;
input  LOCK;
input  eSRAM_eNVM_access_0_FIC_0_CLK;

    wire \CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] , VCC_net_1, GND_net_1;
    
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_24 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[25]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_18 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[19]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_12 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[13]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_23 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[24]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_19 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[20]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_16 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[17]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_2 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[3]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_10 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[11]));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_30 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[31] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[31]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_15 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[16]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_8 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[9]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_28 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[29]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_22 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[23]));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_29 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[30]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_26 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[27]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_20 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[21]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_11 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[12]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_9 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[10] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[10]));
    MSS_075 #( .INIT(1438'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104003FFFFE400000000000010000000000F11C000001FEDFFC010842108421000001FE34001FF8000000400000000000891007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(0.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(), .CAN_TX_EBL_MGPIO4A_H2F_A(), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(), .CLK_CONFIG_APB(), .COMMS_INT(), 
        .CONFIG_PRESET_N(
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N), .EDAC_ERROR({
        nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .F_FM0_RDATA({
        \CoreAHBLite_0_AHBmslave16_HRDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] }), .F_FM0_READYOUT(
        CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_RESP(), .F_HM0_ADDR({
        nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, 
        nc19, nc20, nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, 
        nc29, nc30, nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, 
        nc39}), .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc40, nc41})
        , .F_HM0_TRANS1(), .F_HM0_WDATA({nc42, nc43, nc44, nc45, nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63, nc64, nc65, nc66, 
        nc67, nc68, nc69, nc70, nc71, nc72, nc73}), .F_HM0_WRITE(), 
        .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc74, nc75}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc76, nc77, nc78, nc79}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc80, nc81}), 
        .FAB_XDATAOUT({nc82, nc83, nc84, nc85, nc86, nc87, nc88, nc89})
        , .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc90, nc91}), 
        .FIC32_1_MASTER({nc92, nc93}), .FPGA_RESET_N(
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), 
        .H2F_INTERRUPT({nc94, nc95, nc96, nc97, nc98, nc99, nc100, 
        nc101, nc102, nc103, nc104, nc105, nc106, nc107, nc108, nc109})
        , .H2F_NMI(), .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({nc110, nc111, nc112, nc113, nc114, nc115, 
        nc116, nc117, nc118, nc119, nc120, nc121, nc122, nc123}), 
        .PER2_FABRIC_PENABLE(), .PER2_FABRIC_PSEL(), 
        .PER2_FABRIC_PWDATA({nc124, nc125, nc126, nc127, nc128, nc129, 
        nc130, nc131, nc132, nc133, nc134, nc135, nc136, nc137, nc138, 
        nc139, nc140, nc141, nc142, nc143, nc144, nc145, nc146, nc147, 
        nc148, nc149, nc150, nc151, nc152, nc153, nc154, nc155}), 
        .PER2_FABRIC_PWRITE(), .RTC_MATCH(), .SLEEPDEEP(), 
        .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), .SMBALERT_NO1(), 
        .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc156, nc157, nc158, nc159, 
        nc160, nc161, nc162, nc163, nc164, nc165}), .TRACECLK(), 
        .TRACEDATA({nc166, nc167, nc168, nc169}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc170, nc171, nc172, 
        nc173}), .TXDF({nc174, nc175, nc176, nc177, nc178, nc179, 
        nc180, nc181}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        ), .F_AWREADY_HREADYOUT0(), .F_BID({nc182, nc183, nc184, nc185})
        , .F_BRESP_HRESP0({nc186, nc187}), .F_BVALID(), 
        .F_RDATA_HRDATA01({nc188, nc189, nc190, nc191, nc192, nc193, 
        nc194, nc195, nc196, nc197, nc198, nc199, nc200, nc201, nc202, 
        nc203, nc204, nc205, nc206, nc207, nc208, nc209, nc210, nc211, 
        nc212, nc213, nc214, nc215, nc216, nc217, nc218, nc219, nc220, 
        nc221, nc222, nc223, nc224, nc225, nc226, nc227, nc228, nc229, 
        nc230, nc231, nc232, nc233, nc234, nc235, nc236, nc237, nc238, 
        nc239, nc240, nc241, nc242, nc243, nc244, nc245, nc246, nc247, 
        nc248, nc249, nc250, nc251}), .F_RID({nc252, nc253, nc254, 
        nc255}), .F_RLAST(), .F_RRESP_HRESP1({nc256, nc257}), 
        .F_RVALID(), .F_WREADY(), .MDDR_FABRIC_PRDATA({nc258, nc259, 
        nc260, nc261, nc262, nc263, nc264, nc265, nc266, nc267, nc268, 
        nc269, nc270, nc271, nc272, nc273}), .MDDR_FABRIC_PREADY(), 
        .MDDR_FABRIC_PSLVERR(), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({N_50_i_0, 
        N_93_i_0, N_91_i_0, N_48_i_0, 
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], N_89_i_0, N_87_i_0, 
        N_85_i_0, N_83_i_0, N_81_i_0, N_79_i_0, N_77_i_0, N_75_i_0, 
        N_73_i_0, N_71_i_0, N_69_i_0, N_67_i_0, N_65_i_0, N_63_i_0, 
        N_61_i_0, N_59_i_0, N_57_i_0, N_55_i_0, N_53_i_0, GND_net_1, 
        GND_net_1}), .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(
        GND_net_1), .F_FM0_READY(CoreAHBLite_0_AHBmslave16_HREADY), 
        .F_FM0_SEL(N_152), .F_FM0_SIZE({N_95_i_0, GND_net_1}), 
        .F_FM0_TRANS1(N_51_i_0), .F_FM0_WDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[31], 
        CoreAHBLite_0_AHBmslave16_HWDATA[30], 
        CoreAHBLite_0_AHBmslave16_HWDATA[29], 
        CoreAHBLite_0_AHBmslave16_HWDATA[28], 
        CoreAHBLite_0_AHBmslave16_HWDATA[27], 
        CoreAHBLite_0_AHBmslave16_HWDATA[26], 
        CoreAHBLite_0_AHBmslave16_HWDATA[25], 
        CoreAHBLite_0_AHBmslave16_HWDATA[24], 
        CoreAHBLite_0_AHBmslave16_HWDATA[23], 
        CoreAHBLite_0_AHBmslave16_HWDATA[22], 
        CoreAHBLite_0_AHBmslave16_HWDATA[21], 
        CoreAHBLite_0_AHBmslave16_HWDATA[20], 
        CoreAHBLite_0_AHBmslave16_HWDATA[19], 
        CoreAHBLite_0_AHBmslave16_HWDATA[18], 
        CoreAHBLite_0_AHBmslave16_HWDATA[17], 
        CoreAHBLite_0_AHBmslave16_HWDATA[16], 
        CoreAHBLite_0_AHBmslave16_HWDATA[15], 
        CoreAHBLite_0_AHBmslave16_HWDATA[14], 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .F_FM0_WRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .F_HM0_RDATA({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_HM0_READY(VCC_net_1), .F_HM0_RESP(GND_net_1), 
        .FAB_AVALID(VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(
        VCC_net_1), .FAB_LINESTATE({VCC_net_1, VCC_net_1}), 
        .FAB_M3_RESET_N(VCC_net_1), .FAB_PLL_LOCK(LOCK), .FAB_RXACTIVE(
        VCC_net_1), .FAB_RXERROR(VCC_net_1), .FAB_RXVALID(VCC_net_1), 
        .FAB_RXVALIDH(GND_net_1), .FAB_SESSEND(VCC_net_1), 
        .FAB_TXREADY(VCC_net_1), .FAB_VBUSVALID(VCC_net_1), 
        .FAB_VSTATUS({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .FAB_XDATAIN({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .GTX_CLKPF(VCC_net_1), 
        .I2C0_BCLK(VCC_net_1), .I2C0_SCL_F2H_SCP(VCC_net_1), 
        .I2C0_SDA_F2H_SCP(VCC_net_1), .I2C1_BCLK(VCC_net_1), 
        .I2C1_SCL_F2H_SCP(VCC_net_1), .I2C1_SDA_F2H_SCP(VCC_net_1), 
        .MDIF(VCC_net_1), .MGPIO0A_F2H_GPIN(VCC_net_1), 
        .MGPIO10A_F2H_GPIN(VCC_net_1), .MGPIO11A_F2H_GPIN(VCC_net_1), 
        .MGPIO11B_F2H_GPIN(VCC_net_1), .MGPIO12A_F2H_GPIN(VCC_net_1), 
        .MGPIO13A_F2H_GPIN(VCC_net_1), .MGPIO14A_F2H_GPIN(VCC_net_1), 
        .MGPIO15A_F2H_GPIN(VCC_net_1), .MGPIO16A_F2H_GPIN(VCC_net_1), 
        .MGPIO17B_F2H_GPIN(VCC_net_1), .MGPIO18B_F2H_GPIN(VCC_net_1), 
        .MGPIO19B_F2H_GPIN(VCC_net_1), .MGPIO1A_F2H_GPIN(VCC_net_1), 
        .MGPIO20B_F2H_GPIN(VCC_net_1), .MGPIO21B_F2H_GPIN(VCC_net_1), 
        .MGPIO22B_F2H_GPIN(VCC_net_1), .MGPIO24B_F2H_GPIN(VCC_net_1), 
        .MGPIO25B_F2H_GPIN(VCC_net_1), .MGPIO26B_F2H_GPIN(VCC_net_1), 
        .MGPIO27B_F2H_GPIN(VCC_net_1), .MGPIO28B_F2H_GPIN(VCC_net_1), 
        .MGPIO29B_F2H_GPIN(VCC_net_1), .MGPIO2A_F2H_GPIN(VCC_net_1), 
        .MGPIO30B_F2H_GPIN(VCC_net_1), .MGPIO31B_F2H_GPIN(VCC_net_1), 
        .MGPIO3A_F2H_GPIN(VCC_net_1), .MGPIO4A_F2H_GPIN(VCC_net_1), 
        .MGPIO5A_F2H_GPIN(VCC_net_1), .MGPIO6A_F2H_GPIN(VCC_net_1), 
        .MGPIO7A_F2H_GPIN(VCC_net_1), .MGPIO8A_F2H_GPIN(VCC_net_1), 
        .MGPIO9A_F2H_GPIN(VCC_net_1), .MMUART0_CTS_F2H_SCP(VCC_net_1), 
        .MMUART0_DCD_F2H_SCP(VCC_net_1), .MMUART0_DSR_F2H_SCP(
        VCC_net_1), .MMUART0_DTR_F2H_SCP(VCC_net_1), 
        .MMUART0_RI_F2H_SCP(VCC_net_1), .MMUART0_RTS_F2H_SCP(VCC_net_1)
        , .MMUART0_RXD_F2H_SCP(VCC_net_1), .MMUART0_SCK_F2H_SCP(
        VCC_net_1), .MMUART0_TXD_F2H_SCP(VCC_net_1), 
        .MMUART1_CTS_F2H_SCP(VCC_net_1), .MMUART1_DCD_F2H_SCP(
        VCC_net_1), .MMUART1_DSR_F2H_SCP(VCC_net_1), 
        .MMUART1_RI_F2H_SCP(VCC_net_1), .MMUART1_RTS_F2H_SCP(VCC_net_1)
        , .MMUART1_RXD_F2H_SCP(VCC_net_1), .MMUART1_SCK_F2H_SCP(
        VCC_net_1), .MMUART1_TXD_F2H_SCP(VCC_net_1), 
        .PER2_FABRIC_PRDATA({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .PER2_FABRIC_PREADY(VCC_net_1), .PER2_FABRIC_PSLVERR(GND_net_1)
        , .RCGF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .RX_CLKPF(VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), 
        .RX_EV(VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .SLEEPHOLDREQ(GND_net_1), .SMBALERT_NI0(VCC_net_1), 
        .SMBALERT_NI1(VCC_net_1), .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(
        VCC_net_1), .SPI0_CLK_IN(VCC_net_1), .SPI0_SDI_F2H_SCP(
        VCC_net_1), .SPI0_SDO_F2H_SCP(VCC_net_1), .SPI0_SS0_F2H_SCP(
        VCC_net_1), .SPI0_SS1_F2H_SCP(VCC_net_1), .SPI0_SS2_F2H_SCP(
        VCC_net_1), .SPI0_SS3_F2H_SCP(VCC_net_1), .SPI1_CLK_IN(
        VCC_net_1), .SPI1_SDI_F2H_SCP(VCC_net_1), .SPI1_SDO_F2H_SCP(
        VCC_net_1), .SPI1_SS0_F2H_SCP(VCC_net_1), .SPI1_SS1_F2H_SCP(
        VCC_net_1), .SPI1_SS2_F2H_SCP(VCC_net_1), .SPI1_SS3_F2H_SCP(
        VCC_net_1), .TX_CLKPF(VCC_net_1), .USER_MSS_GPIO_RESET_N(
        VCC_net_1), .USER_MSS_RESET_N(VCC_net_1), .XCLK_FAB(VCC_net_1), 
        .CLK_BASE(eSRAM_eNVM_access_0_FIC_0_CLK), .CLK_MDDR_APB(
        VCC_net_1), .F_ARADDR_HADDR1({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .F_ARBURST_HTRANS1({GND_net_1, GND_net_1}), .F_ARID_HSEL1({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_ARLEN_HBURST1({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLOCK_HMASTLOCK1({GND_net_1, GND_net_1}), .F_ARSIZE_HSIZE1({
        GND_net_1, GND_net_1}), .F_ARVALID_HWRITE1(GND_net_1), 
        .F_AWADDR_HADDR0({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .F_AWBURST_HTRANS0({
        GND_net_1, GND_net_1}), .F_AWID_HSEL0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLEN_HBURST0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLOCK_HMASTLOCK0({GND_net_1, 
        GND_net_1}), .F_AWSIZE_HSIZE0({GND_net_1, GND_net_1}), 
        .F_AWVALID_HWRITE0(GND_net_1), .F_BREADY(GND_net_1), 
        .F_RMW_AXI(GND_net_1), .F_RREADY(GND_net_1), .F_WDATA_HWDATA01({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .F_WID_HREADY01({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_WLAST(
        GND_net_1), .F_WSTRB({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_WVALID(GND_net_1), .FPGA_MDDR_ARESET_N(VCC_net_1), 
        .MDDR_FABRIC_PADDR({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .MDDR_FABRIC_PENABLE(VCC_net_1), .MDDR_FABRIC_PSEL(VCC_net_1), 
        .MDDR_FABRIC_PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .MDDR_FABRIC_PWRITE(
        VCC_net_1), .PRESET_N(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1}), 
        .DRAM_FIFO_WE_IN({GND_net_1, GND_net_1}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND_net_1), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({nc274, nc275, 
        nc276, nc277, nc278, nc279, nc280, nc281, nc282, nc283, nc284, 
        nc285, nc286, nc287, nc288, nc289}), .DRAM_BA({nc290, nc291, 
        nc292}), .DRAM_CASN(), .DRAM_CKE(), .DRAM_CLK(), .DRAM_CSN(), 
        .DRAM_DM_RDQS_OUT({nc293, nc294, nc295}), .DRAM_DQ_OUT({nc296, 
        nc297, nc298, nc299, nc300, nc301, nc302, nc303, nc304, nc305, 
        nc306, nc307, nc308, nc309, nc310, nc311, nc312, nc313}), 
        .DRAM_DQS_OUT({nc314, nc315, nc316}), .DRAM_FIFO_WE_OUT({nc317, 
        nc318}), .DRAM_ODT(), .DRAM_RASN(), .DRAM_RSTN(), .DRAM_WEN(), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc319, nc320, 
        nc321}), .DRAM_DQ_OE({nc322, nc323, nc324, nc325, nc326, nc327, 
        nc328, nc329, nc330, nc331, nc332, nc333, nc334, nc335, nc336, 
        nc337, nc338, nc339}), .DRAM_DQS_OE({nc340, nc341, nc342}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), .MMUART1_CTS_MGPIO13B_OE()
        , .MMUART1_DCD_MGPIO16B_OE(), .MMUART1_DSR_MGPIO14B_OE(), 
        .MMUART1_DTR_MGPIO12B_OE(), .MMUART1_RI_MGPIO15B_OE(), 
        .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_17 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[18] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[18]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_14 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[15] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[15]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_5 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[6] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[6]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_25 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[26] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[26]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_13 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[14] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[14]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_1 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[2] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[2]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_4 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[5] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[5]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[0] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[0]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_6 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[7] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[7]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_7 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[8] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[8]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_21 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[22] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[22]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_0 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[1] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[1]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_27 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[28] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[28]));
    CFG3 #( .INIT(8'h40) )  MSS_ADLIB_INST_RNID1FG_3 (.A(
        defSlaveSMNextState_0_o2), .B(
        \CoreAHBLite_0_AHBmslave16_HRDATA[4] ), .C(m0s16DataSel), .Y(
        AHB_IF_0_BIF_1_HRDATA[4]));
    
endmodule


module eSRAM_eNVM_access(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HWDATA,
       AHB_IF_0_BIF_1_HRDATA,
       DEVRST_N,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_access_0_MSS_READY,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_iv
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:0] AHB_IF_0_BIF_1_HRDATA;
input  DEVRST_N;
output eSRAM_eNVM_access_0_FIC_0_CLK;
output eSRAM_eNVM_access_0_MSS_READY;
input  AHB_IF_0_BIF_1_HWRITE;
output HREADY_M_iv;

    wire SYSRESET_POR_net_1, LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , m0s16DataSel, 
        CoreAHBLite_0_AHBmslave16_HREADY, defSlaveSMNextState_0_o2, 
        N_152, CoreAHBLite_0_AHBmslave16_HWRITE, N_95_i_0, N_51_i_0, 
        N_50_i_0, N_93_i_0, N_91_i_0, N_48_i_0, N_89_i_0, N_87_i_0, 
        N_85_i_0, N_83_i_0, N_81_i_0, N_79_i_0, N_77_i_0, N_75_i_0, 
        N_73_i_0, N_71_i_0, N_69_i_0, N_67_i_0, N_65_i_0, N_63_i_0, 
        N_61_i_0, N_59_i_0, N_57_i_0, N_55_i_0, N_53_i_0, 
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F, 
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N, GND_net_1, 
        VCC_net_1;
    
    eSRAM_eNVM_access_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z6 CORERESETP_0 (.eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .SYSRESET_POR(
        SYSRESET_POR_net_1), 
        .eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F(
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F), 
        .eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N(
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N));
    CoreAHBLite_Z5 CoreAHBLite_0 (.AHB_IF_0_BIF_1_HTRANS({
        AHB_IF_0_BIF_1_HTRANS[1]}), .AHB_IF_0_BIF_1_HADDR({
        AHB_IF_0_BIF_1_HADDR[31], AHB_IF_0_BIF_1_HADDR[30], 
        AHB_IF_0_BIF_1_HADDR[29], AHB_IF_0_BIF_1_HADDR[28], 
        AHB_IF_0_BIF_1_HADDR[27], AHB_IF_0_BIF_1_HADDR[26], 
        AHB_IF_0_BIF_1_HADDR[25], AHB_IF_0_BIF_1_HADDR[24], 
        AHB_IF_0_BIF_1_HADDR[23], AHB_IF_0_BIF_1_HADDR[22], 
        AHB_IF_0_BIF_1_HADDR[21], AHB_IF_0_BIF_1_HADDR[20], 
        AHB_IF_0_BIF_1_HADDR[19], AHB_IF_0_BIF_1_HADDR[18], 
        AHB_IF_0_BIF_1_HADDR[17], AHB_IF_0_BIF_1_HADDR[16], 
        AHB_IF_0_BIF_1_HADDR[15], AHB_IF_0_BIF_1_HADDR[14], 
        AHB_IF_0_BIF_1_HADDR[13], AHB_IF_0_BIF_1_HADDR[12], 
        AHB_IF_0_BIF_1_HADDR[11], AHB_IF_0_BIF_1_HADDR[10], 
        AHB_IF_0_BIF_1_HADDR[9], AHB_IF_0_BIF_1_HADDR[8], 
        AHB_IF_0_BIF_1_HADDR[7], AHB_IF_0_BIF_1_HADDR[6], 
        AHB_IF_0_BIF_1_HADDR[5], AHB_IF_0_BIF_1_HADDR[4], 
        AHB_IF_0_BIF_1_HADDR[3], AHB_IF_0_BIF_1_HADDR[2]}), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[31], 
        AHB_IF_0_BIF_1_HWDATA[30], AHB_IF_0_BIF_1_HWDATA[29], 
        AHB_IF_0_BIF_1_HWDATA[28], AHB_IF_0_BIF_1_HWDATA[27], 
        AHB_IF_0_BIF_1_HWDATA[26], AHB_IF_0_BIF_1_HWDATA[25], 
        AHB_IF_0_BIF_1_HWDATA[24], AHB_IF_0_BIF_1_HWDATA[23], 
        AHB_IF_0_BIF_1_HWDATA[22], AHB_IF_0_BIF_1_HWDATA[21], 
        AHB_IF_0_BIF_1_HWDATA[20], AHB_IF_0_BIF_1_HWDATA[19], 
        AHB_IF_0_BIF_1_HWDATA[18], AHB_IF_0_BIF_1_HWDATA[17], 
        AHB_IF_0_BIF_1_HWDATA[16], AHB_IF_0_BIF_1_HWDATA[15], 
        AHB_IF_0_BIF_1_HWDATA[14], AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] }), 
        .eSRAM_eNVM_access_0_MSS_READY(eSRAM_eNVM_access_0_MSS_READY), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .m0s16DataSel(m0s16DataSel), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_iv(HREADY_M_iv), 
        .defSlaveSMNextState_0_o2(defSlaveSMNextState_0_o2), .N_152(
        N_152), .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .N_95_i_0(N_95_i_0), 
        .N_51_i_0(N_51_i_0), .N_50_i_0(N_50_i_0), .N_93_i_0(N_93_i_0), 
        .N_91_i_0(N_91_i_0), .N_48_i_0(N_48_i_0), .N_89_i_0(N_89_i_0), 
        .N_87_i_0(N_87_i_0), .N_85_i_0(N_85_i_0), .N_83_i_0(N_83_i_0), 
        .N_81_i_0(N_81_i_0), .N_79_i_0(N_79_i_0), .N_77_i_0(N_77_i_0), 
        .N_75_i_0(N_75_i_0), .N_73_i_0(N_73_i_0), .N_71_i_0(N_71_i_0), 
        .N_69_i_0(N_69_i_0), .N_67_i_0(N_67_i_0), .N_65_i_0(N_65_i_0), 
        .N_63_i_0(N_63_i_0), .N_61_i_0(N_61_i_0), .N_59_i_0(N_59_i_0), 
        .N_57_i_0(N_57_i_0), .N_55_i_0(N_55_i_0), .N_53_i_0(N_53_i_0));
    VCC VCC (.Y(VCC_net_1));
    eSRAM_eNVM_access_CCC_0_FCCC CCC_0 (.eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .LOCK(LOCK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    GND GND (.Y(GND_net_1));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(SYSRESET_POR_net_1), 
        .DEVRST_N(DEVRST_N));
    eSRAM_eNVM_access_MSS eSRAM_eNVM_access_MSS_0 (
        .AHB_IF_0_BIF_1_HRDATA({AHB_IF_0_BIF_1_HRDATA[31], 
        AHB_IF_0_BIF_1_HRDATA[30], AHB_IF_0_BIF_1_HRDATA[29], 
        AHB_IF_0_BIF_1_HRDATA[28], AHB_IF_0_BIF_1_HRDATA[27], 
        AHB_IF_0_BIF_1_HRDATA[26], AHB_IF_0_BIF_1_HRDATA[25], 
        AHB_IF_0_BIF_1_HRDATA[24], AHB_IF_0_BIF_1_HRDATA[23], 
        AHB_IF_0_BIF_1_HRDATA[22], AHB_IF_0_BIF_1_HRDATA[21], 
        AHB_IF_0_BIF_1_HRDATA[20], AHB_IF_0_BIF_1_HRDATA[19], 
        AHB_IF_0_BIF_1_HRDATA[18], AHB_IF_0_BIF_1_HRDATA[17], 
        AHB_IF_0_BIF_1_HRDATA[16], AHB_IF_0_BIF_1_HRDATA[15], 
        AHB_IF_0_BIF_1_HRDATA[14], AHB_IF_0_BIF_1_HRDATA[13], 
        AHB_IF_0_BIF_1_HRDATA[12], AHB_IF_0_BIF_1_HRDATA[11], 
        AHB_IF_0_BIF_1_HRDATA[10], AHB_IF_0_BIF_1_HRDATA[9], 
        AHB_IF_0_BIF_1_HRDATA[8], AHB_IF_0_BIF_1_HRDATA[7], 
        AHB_IF_0_BIF_1_HRDATA[6], AHB_IF_0_BIF_1_HRDATA[5], 
        AHB_IF_0_BIF_1_HRDATA[4], AHB_IF_0_BIF_1_HRDATA[3], 
        AHB_IF_0_BIF_1_HRDATA[2], AHB_IF_0_BIF_1_HRDATA[1], 
        AHB_IF_0_BIF_1_HRDATA[0]}), .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] }), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[31] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[30] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[29] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[28] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[27] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[26] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[25] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[24] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[23] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[22] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[21] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[20] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[19] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[18] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[17] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[16] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[15] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[14] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .defSlaveSMNextState_0_o2(defSlaveSMNextState_0_o2), 
        .m0s16DataSel(m0s16DataSel), 
        .eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N(
        eSRAM_eNVM_access_MSS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), 
        .eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F(
        eSRAM_eNVM_access_MSS_TMP_0_MSS_RESET_N_M2F), .N_53_i_0(
        N_53_i_0), .N_55_i_0(N_55_i_0), .N_57_i_0(N_57_i_0), .N_59_i_0(
        N_59_i_0), .N_61_i_0(N_61_i_0), .N_63_i_0(N_63_i_0), .N_65_i_0(
        N_65_i_0), .N_67_i_0(N_67_i_0), .N_69_i_0(N_69_i_0), .N_71_i_0(
        N_71_i_0), .N_73_i_0(N_73_i_0), .N_75_i_0(N_75_i_0), .N_77_i_0(
        N_77_i_0), .N_79_i_0(N_79_i_0), .N_81_i_0(N_81_i_0), .N_83_i_0(
        N_83_i_0), .N_85_i_0(N_85_i_0), .N_87_i_0(N_87_i_0), .N_89_i_0(
        N_89_i_0), .N_48_i_0(N_48_i_0), .N_91_i_0(N_91_i_0), .N_93_i_0(
        N_93_i_0), .N_50_i_0(N_50_i_0), .N_152(N_152), .N_95_i_0(
        N_95_i_0), .N_51_i_0(N_51_i_0), 
        .CoreAHBLite_0_AHBmslave16_HWRITE(
        CoreAHBLite_0_AHBmslave16_HWRITE), .LOCK(LOCK), 
        .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK));
    
endmodule


module eSRAM_eNVM_RW_Z7(
       eSRAM_eNVM_RW_0_ram_waddr,
       eSRAM_eNVM_RW_0_ram_wdata,
       AHB_IF_0_DATAOUT,
       eSRAM_eNVM_RW_0_ADDR,
       eSRAM_eNVM_RW_0_DATAOUT,
       eSRAM_eNVM_access_0_MSS_READY,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ,
       eSRAM_eNVM_RW_0_ram_wen,
       start_envm_c,
       start_esram_c,
       AHB_IF_0_AHB_BUSY,
       AHB_IF_0_VALID
    );
output [4:0] eSRAM_eNVM_RW_0_ram_waddr;
output [31:0] eSRAM_eNVM_RW_0_ram_wdata;
input  [31:0] AHB_IF_0_DATAOUT;
output [31:2] eSRAM_eNVM_RW_0_ADDR;
output [31:0] eSRAM_eNVM_RW_0_DATAOUT;
input  eSRAM_eNVM_access_0_MSS_READY;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
output eSRAM_eNVM_RW_0_WRITE;
output eSRAM_eNVM_RW_0_READ;
output eSRAM_eNVM_RW_0_ram_wen;
input  start_envm_c;
input  start_esram_c;
input  AHB_IF_0_AHB_BUSY;
input  AHB_IF_0_VALID;

    wire VCC_net_1, N_363_i_0, ram_waddre, GND_net_1, N_366_i_0, 
        N_359_i_0, N_362_i_0, \data_cnt[3]_net_1 , N_330_i_0, 
        data_cnte, \data_cnt[4]_net_1 , N_331_i_0, N_9_i_0, 
        \data_cnt[0]_net_1 , N_423, \data_cnt[1]_net_1 , N_328_i_0, 
        \data_cnt[2]_net_1 , N_329_i_0, N_204_i_0, N_792_i_0, 
        N_392_i_0, N_378_i_0, N_390_i_0, envm_release_reg_net_1, 
        \current_state[9]_net_1 , un40_0_0_0_net_1, N_360_i_0, 
        N_387_i_0, \current_state[6]_net_1 , N_330_i_0_0, 
        \current_state[7]_net_1 , \current_state_ns[7] , 
        \current_state[8]_net_1 , \current_state_ns[8] , 
        \current_state_ns[9] , \data_13[31] , \current_state_ns[10] , 
        \current_state[11]_net_1 , N_336_i_0, 
        \current_state[12]_net_1 , \current_state_ns[12] , 
        \current_state[13]_net_1 , \current_state_ns_i_i_0[13]_net_1 , 
        \current_state[14]_net_1 , N_341_i_0, 
        \current_state[15]_net_1 , \current_state_ns[15] , 
        \current_state[16]_net_1 , \current_state_ns[16] , 
        \current_state[0]_net_1 , \current_state_ns[0] , 
        \current_state[1]_net_1 , \current_state_ns_i_i_0[1]_net_1 , 
        \current_state[2]_net_1 , \current_state_ns[2] , 
        \current_state[3]_net_1 , \current_state_ns[3] , 
        \current_state[4]_net_1 , \current_state_ns_i_i_0[4]_net_1 , 
        \current_state[5]_net_1 , \current_state_ns[5] , 
        start_envm_reg_net_1, start_esram_reg_net_1, 
        start_envm_reg1_net_1, start_esram_reg1_net_1, 
        start_envm_reg2_net_1, start_esram_reg2_net_1, 
        \addr_temp_lm[2] , N_164_i_0, \addr_temp_lm[3] , 
        \addr_temp_lm[4] , \addr_temp_lm[5] , \addr_temp_lm[6] , 
        \addr_temp_lm[7] , \addr_temp_lm[8] , \addr_temp_lm[9] , 
        \addr_temp_lm[10] , \addr_temp_lm[11] , \addr_temp_lm[12] , 
        \addr_temp_lm[13] , \addr_temp_lm[14] , \addr_temp_lm[15] , 
        \addr_temp_lm[16] , \addr_temp_lm[17] , \addr_temp_lm[18] , 
        \addr_temp_lm[19] , \addr_temp_lm[20] , \addr_temp_lm[21] , 
        \addr_temp_lm[22] , \addr_temp_lm[23] , \addr_temp_lm[24] , 
        \addr_temp_lm[25] , \addr_temp_lm[26] , \addr_temp_lm[27] , 
        \addr_temp_lm[28] , \addr_temp_lm[29] , \addr_temp_lm[30] , 
        \addr_temp_lm[31] , \data_s[0] , N_45_i_0, \data_s[1] , 
        \data_s[2] , \data_s[3] , \data_s[4] , \data_s[5] , 
        \data_s[6] , \data_s[7] , \data_s[8] , \data_s[9] , 
        \data_s[10] , \data_s[11] , \data_s[12] , \data_s[13] , 
        \data_s[14] , \data_s[15] , \data_s[16] , \data_s[17] , 
        \data_s[18] , \data_s[19] , \data_s[20] , \data_s[21] , 
        \data_s[22] , \data_s[23] , \data_s[24] , \data_s[25] , 
        \data_s[26] , \data_s[27] , \data_s[28] , \data_s[29] , 
        \data_s[30] , \data_s[31]_net_1 , data_cry_cy, 
        \data_cry_cy_Y[0] , N_335, un1_READ6_3_0_0_1_3, 
        \data_cry[0]_net_1 , \data_cnst_i_i_0[0]_net_1 , 
        \data_cry[1]_net_1 , \data_cry[2]_net_1 , \data_cry[3]_net_1 , 
        \data_cry[4]_net_1 , N_121, \data_cry[5]_net_1 , 
        \data_cry[6]_net_1 , \data_cry[7]_net_1 , N_217_i, 
        \data_cry[8]_net_1 , \data_13[9] , \data_cry[9]_net_1 , 
        \data_cry[10]_net_1 , \data_13[7] , \data_cry[11]_net_1 , 
        \data_cry[12]_net_1 , \data_cry[13]_net_1 , 
        \data_cry[14]_net_1 , \data_cry[15]_net_1 , 
        \data_cry[16]_net_1 , \data_cry[17]_net_1 , 
        \data_cry[18]_net_1 , \data_cry[19]_net_1 , 
        \data_cry[20]_net_1 , \data_cry[21]_net_1 , 
        \data_cry[22]_net_1 , \data_cry[23]_net_1 , 
        \data_cry[24]_net_1 , \data_cry[25]_net_1 , 
        \data_cry[26]_net_1 , \data_cry[27]_net_1 , 
        \data_cry[28]_net_1 , \data_cry[29]_net_1 , 
        \data_cry[30]_net_1 , addr_temp_s_34_FCO, 
        \addr_temp_cry[3]_net_1 , \addr_temp_s[3] , 
        \addr_temp_cry[4]_net_1 , \addr_temp_s[4] , 
        \addr_temp_cry[5]_net_1 , \addr_temp_s[5] , 
        \addr_temp_cry[6]_net_1 , \addr_temp_s[6] , 
        \addr_temp_cry[7]_net_1 , \addr_temp_s[7] , 
        \addr_temp_cry[8]_net_1 , \addr_temp_s[8] , 
        \addr_temp_cry[9]_net_1 , \addr_temp_s[9] , 
        \addr_temp_cry[10]_net_1 , \addr_temp_s[10] , 
        \addr_temp_cry[11]_net_1 , \addr_temp_s[11] , 
        \addr_temp_cry[12]_net_1 , \addr_temp_s[12] , 
        \addr_temp_cry[13]_net_1 , \addr_temp_s[13] , 
        \addr_temp_cry[14]_net_1 , \addr_temp_s[14] , 
        \addr_temp_cry[15]_net_1 , \addr_temp_s[15] , 
        \addr_temp_cry[16]_net_1 , \addr_temp_s[16] , 
        \addr_temp_cry[17]_net_1 , \addr_temp_s[17] , 
        \addr_temp_cry[18]_net_1 , \addr_temp_s[18] , 
        \addr_temp_cry[19]_net_1 , \addr_temp_s[19] , 
        \addr_temp_cry[20]_net_1 , \addr_temp_s[20] , 
        \addr_temp_cry[21]_net_1 , \addr_temp_s[21] , 
        \addr_temp_cry[22]_net_1 , \addr_temp_s[22] , 
        \addr_temp_cry[23]_net_1 , \addr_temp_s[23] , 
        \addr_temp_cry[24]_net_1 , \addr_temp_s[24] , 
        \addr_temp_cry[25]_net_1 , \addr_temp_s[25] , 
        \addr_temp_cry[26]_net_1 , \addr_temp_s[26] , 
        \addr_temp_cry[27]_net_1 , \addr_temp_s[27] , 
        \addr_temp_cry[28]_net_1 , \addr_temp_s[28] , 
        \addr_temp_cry[29]_net_1 , \addr_temp_s[29] , 
        \addr_temp_s[31]_net_1 , \addr_temp_cry[30]_net_1 , 
        \addr_temp_s[30] , N_474, N_459, N_377, N_340, N_821, 
        un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1, N_334, 
        un1_READ6_3_0_0_1_1, un1_READ6_3_0_0_1_2, N_346, N_479, N_252, 
        un1_current_state_20_i_0_0_0_net_1, 
        un1_current_state_20_i_0_0_a3_2_net_1, N_390_i_1, 
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1, N_344, N_473, N_337, 
        \addr_temp_lm_0_1[7]_net_1 , ram_wdata_0_sqmuxa_i_0_a3_5_net_1, 
        N_204_i_1, N_338, N_412, ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1, 
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1, N_389, 
        un1_READ_1_sqmuxa_2_i_0_0_0_net_1, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_a2_0_0, N_469, N_333, N_339, 
        N_342, N_467, N_341, N_152, N_119, N_457, esram_select_net_1, 
        ram_wdata_0_sqmuxa_i_0_a3_3_net_1, 
        un1_current_state_16_0_0_i_0_0_a3_2_2, 
        un1_current_state_16_0_0_i_0_0_a3_1_1, 
        ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1, 
        \addr_temp_cnst_i_a2_0_0_a3_1[8]_net_1 , N_368, 
        ram_waddrlde_0_0_0, N_254, N_262, N_476, N_117, N_477, 
        N_478_i_0, N_351, un1_current_state_20_i_0_0_a3_1_net_1, 
        un1_current_state_16_0_0_i_0_0_a3_2_3, 
        un1_current_state_19_i_0_0_a3_0_1_net_1, 
        un1_current_state_16_0_0_i_0_0_a3_0, N_369_i_i_0_a3_0_1, N_461, 
        N_447, N_444, N_269, N_481, N_354, N_466, N_266, 
        un1_current_state_16_0_0_i_0_0_0, 
        un1_current_state_19_i_0_0_0_net_1, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2, N_264, N_569, N_260, 
        N_290, un1_current_state_19_i_0_0_1_net_1, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_3, N_380, 
        \addr_temp_cnst_i_a2_0_0[8]_net_1 , N_475, N_369_i_i_0_1, 
        un1_addr_temp_8_sqmuxa_2_i_i_0_1, 
        un1_current_state_16_0_0_i_0_0_2;
    
    CFG2 #( .INIT(4'h7) )  ram_waddr_n2_0_o2 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[0]), .B(eSRAM_eNVM_RW_0_ram_waddr[1])
        , .Y(N_342));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[24]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[24]), .FCI(\data_cry[23]_net_1 ), .S(
        \data_s[24] ), .Y(), .FCO(\data_cry[24]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \current_state_ns_0_0[9]  (.A(
        \current_state[8]_net_1 ), .B(\current_state[9]_net_1 ), .C(
        AHB_IF_0_DATAOUT[0]), .D(N_338), .Y(\current_state_ns[9] ));
    CFG4 #( .INIT(16'hA0CC) )  \addr_temp_lm_0[4]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(\addr_temp_s[4] ), .C(N_340)
        , .D(N_821), .Y(\addr_temp_lm[4] ));
    CFG4 #( .INIT(16'h74FC) )  un1_current_state_19_i_0_0_o2 (.A(
        AHB_IF_0_DATAOUT[2]), .B(\current_state[4]_net_1 ), .C(N_335), 
        .D(AHB_IF_0_DATAOUT[1]), .Y(N_337));
    CFG4 #( .INIT(16'hEAC0) )  \current_state_ns_0_0[7]  (.A(
        \current_state[6]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_475), .Y(\current_state_ns[7] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[26]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[26]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[25]_net_1 ), .S(\addr_temp_s[26] ), .Y(), .FCO(
        \addr_temp_cry[26]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[12]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[12]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[11]_net_1 ), .S(\addr_temp_s[12] ), .Y(), .FCO(
        \addr_temp_cry[12]_net_1 ));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[16]  (.A(
        \addr_temp_s[16] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_121), .Y(\addr_temp_lm[16] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[20]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[20]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[19]_net_1 ), .S(\addr_temp_s[20] ), .Y(), .FCO(
        \addr_temp_cry[20]_net_1 ));
    CFG3 #( .INIT(8'h20) )  un1_READ_1_sqmuxa_2_i_0_a3_0 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[2]), .B(eSRAM_eNVM_RW_0_ram_waddr[0])
        , .C(un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1), .Y(N_389));
    SLE \data[5]  (.D(\data_s[5] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[5]));
    SLE \addr_temp[25]  (.D(\addr_temp_lm[25] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[25]));
    CFG4 #( .INIT(16'h8C88) )  \current_state_RNITV9F3[2]  (.A(N_461), 
        .B(N_334), .C(\current_state[2]_net_1 ), .D(
        AHB_IF_0_DATAOUT[0]), .Y(un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_3)
        );
    SLE \ram_wdata[9]  (.D(AHB_IF_0_DATAOUT[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[9]));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[4]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[4]), 
        .C(N_354), .D(N_569), .Y(N_366_i_0));
    CFG4 #( .INIT(16'h0800) )  \current_state_RNIQCEP1[1]  (.A(N_473), 
        .B(N_466), .C(\current_state[1]_net_1 ), .D(N_333), .Y(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2));
    CFG4 #( .INIT(16'h0B00) )  \current_state_ns_0_0_a3_0[0]  (.A(
        start_envm_reg1_net_1), .B(start_envm_reg2_net_1), .C(
        esram_select_net_1), .D(\current_state[0]_net_1 ), .Y(N_447));
    CFG4 #( .INIT(16'h88F0) )  \addr_temp_lm_0[10]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(\current_state[9]_net_1 ), 
        .C(\addr_temp_s[10] ), .D(N_821), .Y(\addr_temp_lm[10] ));
    SLE \addr_temp[16]  (.D(\addr_temp_lm[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[16]));
    CFG2 #( .INIT(4'h7) )  envm_release_reg_RNIPKA7 (.A(
        \current_state[16]_net_1 ), .B(envm_release_reg_net_1), .Y(
        N_333));
    ARI1 #( .INIT(20'h4E200) )  \data_cry[0]  (.A(VCC_net_1), .B(
        \data_cnst_i_i_0[0]_net_1 ), .C(\data_cry_cy_Y[0] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[0]), .FCI(data_cry_cy), .S(\data_s[0] )
        , .Y(), .FCO(\data_cry[0]_net_1 ));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[29]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[29]), .FCI(\data_cry[28]_net_1 ), .S(
        \data_s[29] ), .Y(), .FCO(\data_cry[29]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[28]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[28]), .D(
        GND_net_1), .FCI(\data_cry[27]_net_1 ), .S(\data_s[28] ), .Y(), 
        .FCO(\data_cry[28]_net_1 ));
    CFG4 #( .INIT(16'hFACC) )  \addr_temp_lm_0[3]  (.A(N_254), .B(
        \addr_temp_s[3] ), .C(N_252), .D(N_821), .Y(\addr_temp_lm[3] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[3]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[3]), .C(GND_net_1), .D(GND_net_1), .FCI(
        addr_temp_s_34_FCO), .S(\addr_temp_s[3] ), .Y(), .FCO(
        \addr_temp_cry[3]_net_1 ));
    SLE \current_state[2]  (.D(\current_state_ns[2] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[2]_net_1 ));
    CFG4 #( .INIT(16'h00DF) )  WRITE_RNO (.A(\data_cnt[4]_net_1 ), .B(
        N_346), .C(un1_current_state_16_0_0_i_0_0_a3_2_3), .D(
        un1_current_state_16_0_0_i_0_0_2), .Y(N_792_i_0));
    ARI1 #( .INIT(20'h41500) )  \data_cry_cy[0]  (.A(N_335), .B(
        un1_READ6_3_0_0_1_3), .C(\current_state[16]_net_1 ), .D(
        envm_release_reg_net_1), .FCI(VCC_net_1), .S(), .Y(
        \data_cry_cy_Y[0] ), .FCO(data_cry_cy));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[15]  (.A(
        \addr_temp_s[15] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_121), .Y(\addr_temp_lm[15] ));
    SLE \ram_wdata[23]  (.D(AHB_IF_0_DATAOUT[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[23]));
    CFG3 #( .INIT(8'hA8) )  \addr_temp_cnst_i_a2_0_i_a3[5]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(N_340), .C(
        \current_state[1]_net_1 ), .Y(N_260));
    SLE \data[9]  (.D(\data_s[9] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[9]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[27]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[27]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[26]_net_1 ), .S(\addr_temp_s[27] ), .Y(), .FCO(
        \addr_temp_cry[27]_net_1 ));
    SLE \addr_temp[26]  (.D(\addr_temp_lm[26] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[26]));
    CFG3 #( .INIT(8'h1F) )  \data_cnst_i_i_0[0]  (.A(
        \current_state[4]_net_1 ), .B(N_335), .C(N_121), .Y(
        \data_cnst_i_i_0[0]_net_1 ));
    SLE \data[10]  (.D(\data_s[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[10]));
    CFG4 #( .INIT(16'hFF5D) )  \addr_temp_cnst_i_a2_0_0[8]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(N_469), .C(N_340), .D(N_269)
        , .Y(\addr_temp_cnst_i_a2_0_0[8]_net_1 ));
    SLE \addr_temp[3]  (.D(\addr_temp_lm[3] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[3]));
    CFG3 #( .INIT(8'h20) )  un1_current_state_20_i_0_0_a3_0 (.A(N_481), 
        .B(\current_state[14]_net_1 ), .C(N_469), .Y(N_290));
    SLE \current_state[6]  (.D(N_330_i_0_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[6]_net_1 ));
    SLE \addr_temp[13]  (.D(\addr_temp_lm[13] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[13]));
    SLE \data_cnt[2]  (.D(N_329_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[2]_net_1 ));
    CFG2 #( .INIT(4'h1) )  un1_READ_1_sqmuxa_2_i_0_a3_1_0 (.A(
        \current_state[12]_net_1 ), .B(AHB_IF_0_VALID), .Y(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1));
    SLE \ram_wdata[17]  (.D(AHB_IF_0_DATAOUT[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[17]));
    CFG2 #( .INIT(4'h1) )  \current_state_RNILB9K[8]  (.A(
        AHB_IF_0_DATAOUT[0]), .B(\current_state[8]_net_1 ), .Y(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a2_0_0));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[24]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[24]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[23]_net_1 ), .S(\addr_temp_s[24] ), .Y(), .FCO(
        \addr_temp_cry[24]_net_1 ));
    SLE \data[13]  (.D(\data_s[13] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[13]));
    SLE \ram_wdata[8]  (.D(AHB_IF_0_DATAOUT[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[8]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[12]  (.A(N_821), .B(
        \addr_temp_s[12] ), .Y(\addr_temp_lm[12] ));
    SLE \addr_temp[6]  (.D(\addr_temp_lm[6] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[6]));
    SLE start_envm_reg (.D(start_envm_c), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg_net_1));
    SLE \addr_temp[23]  (.D(\addr_temp_lm[23] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[23]));
    CFG4 #( .INIT(16'h0008) )  ram_wdata_0_sqmuxa_i_0_a3_5 (.A(N_467), 
        .B(ram_wdata_0_sqmuxa_i_0_a3_3_net_1), .C(
        \current_state[13]_net_1 ), .D(\current_state[9]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_5_net_1));
    CFG3 #( .INIT(8'h01) )  \current_state_RNI7BUF[13]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        \current_state[9]_net_1 ), .Y(N_473));
    CFG4 #( .INIT(16'hCE0A) )  \current_state_ns_i_i_0[4]  (.A(
        \current_state[3]_net_1 ), .B(\current_state[4]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_368), .Y(
        \current_state_ns_i_i_0[4]_net_1 ));
    CFG4 #( .INIT(16'hFA3A) )  \addr_temp_lm_0[30]  (.A(
        \addr_temp_s[30] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_477), .Y(\addr_temp_lm[30] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[16]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[16]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[15]_net_1 ), .S(\addr_temp_s[16] ), .Y(), .FCO(
        \addr_temp_cry[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[10]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[10]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[9]_net_1 ), .S(\addr_temp_s[10] ), .Y(), .FCO(
        \addr_temp_cry[10]_net_1 ));
    SLE \addr_temp[7]  (.D(\addr_temp_lm[7] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[7]));
    CFG4 #( .INIT(16'h0004) )  \current_state_ns_i_0_0_a2_RNISPHK[6]  
        (.A(\data_13[31] ), .B(N_457), .C(\current_state[11]_net_1 ), 
        .D(\current_state[7]_net_1 ), .Y(N_466));
    CFG3 #( .INIT(8'h40) )  ram_wdata_0_sqmuxa_i_0_a3_0 (.A(N_119), .B(
        N_457), .C(ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1), .Y(N_412));
    CFG2 #( .INIT(4'h1) )  \current_state_RNIK0PE[9]  (.A(
        \current_state[9]_net_1 ), .B(\data_13[31] ), .Y(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0));
    SLE \data[4]  (.D(\data_s[4] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[4]));
    CFG4 #( .INIT(16'h0DDD) )  READ_RNO_1 (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1), .B(N_344), .C(N_473), 
        .D(N_337), .Y(N_390_i_1));
    SLE start_esram_reg1 (.D(start_esram_reg_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg1_net_1));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[17]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[17]), .FCI(\data_cry[16]_net_1 ), .S(
        \data_s[17] ), .Y(), .FCO(\data_cry[17]_net_1 ));
    SLE \data[11]  (.D(\data_s[11] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[11]));
    CFG3 #( .INIT(8'h04) )  envm_release_reg_RNIPUH21 (.A(
        envm_release_reg_net_1), .B(\current_state[16]_net_1 ), .C(
        N_344), .Y(N_476));
    CFG3 #( .INIT(8'h10) )  \current_state_RNIMG5G1[0]  (.A(N_344), .B(
        \current_state[0]_net_1 ), .C(N_333), .Y(N_369_i_i_0_a3_0_1));
    CFG2 #( .INIT(4'hB) )  \current_state_ns_i_i_0_o2[13]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[12]_net_1 ), .Y(N_341));
    ARI1 #( .INIT(20'h4AA00) )  addr_temp_s_34 (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[2]), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(addr_temp_s_34_FCO));
    SLE \ram_waddr[4]  (.D(N_366_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[4]));
    CFG2 #( .INIT(4'h4) )  ram_wdata_0_sqmuxa_i_0_o2_RNIDIA2 (.A(N_338)
        , .B(N_119), .Y(N_360_i_0));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[2]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[2]), 
        .C(N_342), .D(N_569), .Y(N_362_i_0));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[9]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[9] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[9]), .FCI(\data_cry[8]_net_1 ), .S(
        \data_s[9] ), .Y(), .FCO(\data_cry[9]_net_1 ));
    GND GND (.Y(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[17]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[17]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[16]_net_1 ), .S(\addr_temp_s[17] ), .Y(), .FCO(
        \addr_temp_cry[17]_net_1 ));
    SLE \ram_wdata[4]  (.D(AHB_IF_0_DATAOUT[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[4]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[7]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[7]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[6]_net_1 ), .S(\addr_temp_s[7] ), .Y(), .FCO(
        \addr_temp_cry[7]_net_1 ));
    CFG4 #( .INIT(16'hF800) )  \current_state_RNINL4L3[0]  (.A(N_459), 
        .B(N_351), .C(N_369_i_i_0_a3_0_1), .D(N_466), .Y(N_369_i_i_0_1)
        );
    CFG4 #( .INIT(16'hFF7F) )  \current_state_RNIKDK11[4]  (.A(
        \current_state[4]_net_1 ), .B(AHB_IF_0_DATAOUT[2]), .C(
        AHB_IF_0_DATAOUT[1]), .D(AHB_IF_0_DATAOUT[0]), .Y(N_121));
    CFG4 #( .INIT(16'hF2FA) )  \current_state_ns_0_0[0]  (.A(
        \current_state[16]_net_1 ), .B(envm_release_reg_net_1), .C(
        N_447), .D(AHB_IF_0_AHB_BUSY), .Y(\current_state_ns[0] ));
    CFG3 #( .INIT(8'h41) )  \data_cnt_RNO[2]  (.A(N_478_i_0), .B(
        \data_cnt[2]_net_1 ), .C(N_339), .Y(N_329_i_0));
    SLE \data_cnt[4]  (.D(N_331_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[4]_net_1 ));
    SLE \current_state[5]  (.D(\current_state_ns[5] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[14]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[14]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[13]_net_1 ), .S(\addr_temp_s[14] ), .Y(), .FCO(
        \addr_temp_cry[14]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[24]  (.A(N_821), .B(
        \addr_temp_s[24] ), .Y(\addr_temp_lm[24] ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[9]  (.A(N_821), .B(
        \addr_temp_s[9] ), .Y(\addr_temp_lm[9] ));
    CFG4 #( .INIT(16'h0C0E) )  \current_state_RNO[14]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[14]_net_1 ), .C(
        N_389), .D(N_338), .Y(N_341_i_0));
    SLE \data_cnt[1]  (.D(N_328_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[1]_net_1 ));
    SLE \ram_wdata[11]  (.D(AHB_IF_0_DATAOUT[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[11]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[16]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[16]), .D(
        GND_net_1), .FCI(\data_cry[15]_net_1 ), .S(\data_s[16] ), .Y(), 
        .FCO(\data_cry[16]_net_1 ));
    SLE \data[24]  (.D(\data_s[24] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[24]));
    CFG3 #( .INIT(8'h51) )  READ_RNO_0 (.A(
        un1_current_state_20_i_0_0_0_net_1), .B(
        un1_current_state_20_i_0_0_a3_2_net_1), .C(N_390_i_1), .Y(
        N_390_i_0));
    SLE \ram_wdata[31]  (.D(AHB_IF_0_DATAOUT[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[31]));
    SLE \addr_temp[30]  (.D(\addr_temp_lm[30] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[30]));
    SLE \data[30]  (.D(\data_s[30] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[30]));
    SLE \ram_wdata[6]  (.D(AHB_IF_0_DATAOUT[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[6]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[10]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[7] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[10]), .FCI(\data_cry[9]_net_1 ), .S(
        \data_s[10] ), .Y(), .FCO(\data_cry[10]_net_1 ));
    CFG4 #( .INIT(16'hCCAE) )  \current_state_ns_0_0[2]  (.A(
        \current_state[1]_net_1 ), .B(\current_state[2]_net_1 ), .C(
        AHB_IF_0_DATAOUT[0]), .D(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns[2] ));
    SLE start_esram_reg2 (.D(start_esram_reg1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg2_net_1));
    ARI1 #( .INIT(20'h4E200) )  \data_cry[27]  (.A(VCC_net_1), .B(
        N_217_i), .C(\data_cry_cy_Y[0] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[27]), .FCI(\data_cry[26]_net_1 ), .S(
        \data_s[27] ), .Y(), .FCO(\data_cry[27]_net_1 ));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[6]  (.A(VCC_net_1), .B(N_121)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[6]), .FCI(
        \data_cry[5]_net_1 ), .S(\data_s[6] ), .Y(), .FCO(
        \data_cry[6]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \current_state_ns_i_0_0_a2[6]  (.A(
        \current_state[5]_net_1 ), .B(\current_state[6]_net_1 ), .Y(
        N_457));
    CFG4 #( .INIT(16'h7FFF) )  data_cnt_n3_i_o2 (.A(
        \data_cnt[3]_net_1 ), .B(\data_cnt[1]_net_1 ), .C(
        \data_cnt[2]_net_1 ), .D(\data_cnt[0]_net_1 ), .Y(N_346));
    CFG4 #( .INIT(16'h353A) )  \ram_waddr_RNO[1]  (.A(
        eSRAM_eNVM_RW_0_ram_waddr[1]), .B(\current_state[0]_net_1 ), 
        .C(N_569), .D(eSRAM_eNVM_RW_0_ram_waddr[0]), .Y(N_359_i_0));
    CFG4 #( .INIT(16'hF5C5) )  \ram_waddr_RNO[0]  (.A(
        eSRAM_eNVM_RW_0_ram_waddr[0]), .B(\current_state[12]_net_1 ), 
        .C(N_569), .D(\current_state[9]_net_1 ), .Y(N_9_i_0));
    SLE \data[1]  (.D(\data_s[1] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[1]));
    CFG4 #( .INIT(16'hCECC) )  WRITE_RNO_5 (.A(N_474), .B(N_476), .C(
        \current_state[16]_net_1 ), .D(AHB_IF_0_AHB_BUSY), .Y(
        un1_current_state_16_0_0_i_0_0_0));
    SLE \current_state[16]  (.D(\current_state_ns[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[16]_net_1 ));
    SLE \data[6]  (.D(\data_s[6] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[6]));
    SLE \addr_temp[31]  (.D(\addr_temp_lm[31] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[31]));
    SLE \data[25]  (.D(\data_s[25] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[25]));
    CFG3 #( .INIT(8'hD5) )  \current_state_ns_0_0[5]  (.A(N_121), .B(
        \current_state[5]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns[5] ));
    SLE \ram_wdata[5]  (.D(AHB_IF_0_DATAOUT[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[5]));
    CFG3 #( .INIT(8'h40) )  un1_current_state_19_i_0_0_a3_0_1 (.A(
        \current_state[12]_net_1 ), .B(N_479), .C(N_459), .Y(
        un1_current_state_19_i_0_0_a3_0_1_net_1));
    SLE start_envm_reg2 (.D(start_envm_reg1_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg2_net_1));
    CFG4 #( .INIT(16'hFFC8) )  \data_cry_cy_RNO_0[0]  (.A(
        \current_state[2]_net_1 ), .B(\current_state[16]_net_1 ), .C(
        \current_state[4]_net_1 ), .D(un1_READ6_3_0_0_1_1), .Y(
        un1_READ6_3_0_0_1_2));
    CFG4 #( .INIT(16'hFFFE) )  \data_cry_cy_RNO_1[0]  (.A(
        \current_state[0]_net_1 ), .B(\data_13[31] ), .C(
        \current_state[5]_net_1 ), .D(\current_state[7]_net_1 ), .Y(
        un1_READ6_3_0_0_1_1));
    CFG4 #( .INIT(16'hEAC0) )  \current_state_ns_0_0[12]  (.A(
        \current_state[11]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_475), .Y(\current_state_ns[12] ));
    CFG4 #( .INIT(16'h0ACA) )  \addr_temp_lm_0[17]  (.A(
        \addr_temp_s[17] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_121), .Y(\addr_temp_lm[17] ));
    CFG4 #( .INIT(16'h4CCC) )  \current_state_RNIP78F1[4]  (.A(
        AHB_IF_0_DATAOUT[1]), .B(un1_addr_temp_8_sqmuxa_2_i_i_0_a2_0_0)
        , .C(\current_state[4]_net_1 ), .D(AHB_IF_0_DATAOUT[2]), .Y(
        N_461));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[8]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[9] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[8]), .FCI(\data_cry[7]_net_1 ), .S(
        \data_s[8] ), .Y(), .FCO(\data_cry[8]_net_1 ));
    SLE start_esram_reg (.D(start_esram_c), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_esram_reg_net_1));
    CFG3 #( .INIT(8'h04) )  \current_state_ns_i_0_0_a2_0[6]  (.A(N_346)
        , .B(\data_cnt[4]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(N_475));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[18]  (.A(N_821), .B(
        \addr_temp_s[18] ), .Y(\addr_temp_lm[18] ));
    SLE \ram_wdata[14]  (.D(AHB_IF_0_DATAOUT[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[14]));
    CFG4 #( .INIT(16'hFECC) )  WRITE_RNO_2 (.A(
        un1_current_state_16_0_0_i_0_0_a3_0), .B(
        un1_current_state_16_0_0_i_0_0_0), .C(
        un1_current_state_16_0_0_i_0_0_a3_1_1), .D(N_466), .Y(
        un1_current_state_16_0_0_i_0_0_2));
    VCC VCC (.Y(VCC_net_1));
    SLE \data[31]  (.D(\data_s[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[31]));
    SLE \ram_wdata[28]  (.D(AHB_IF_0_DATAOUT[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[28]));
    SLE \data[8]  (.D(\data_s[8] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[8]));
    SLE \data[26]  (.D(\data_s[26] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[26]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[26]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[26]), .D(
        GND_net_1), .FCI(\data_cry[25]_net_1 ), .S(\data_s[26] ), .Y(), 
        .FCO(\data_cry[26]_net_1 ));
    CFG4 #( .INIT(16'h0ACC) )  \addr_temp_lm_0[7]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(\addr_temp_s[7] ), .C(
        \addr_temp_lm_0_1[7]_net_1 ), .D(N_821), .Y(\addr_temp_lm[7] ));
    CFG2 #( .INIT(4'h2) )  \current_state_RNI1LPH[1]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[1]_net_1 ), .Y(N_469));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[29]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[29]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[28]_net_1 ), .S(\addr_temp_s[29] ), .Y(), .FCO(
        \addr_temp_cry[29]_net_1 ));
    CFG4 #( .INIT(16'h0100) )  WRITE_RNO_1 (.A(
        \current_state[5]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        \current_state[16]_net_1 ), .D(
        un1_current_state_16_0_0_i_0_0_a3_2_2), .Y(
        un1_current_state_16_0_0_i_0_0_a3_2_3));
    CFG3 #( .INIT(8'h01) )  WRITE_RNO_3 (.A(\data_13[31] ), .B(N_344), 
        .C(\current_state[11]_net_1 ), .Y(
        un1_current_state_16_0_0_i_0_0_a3_2_2));
    SLE \ram_wdata[12]  (.D(AHB_IF_0_DATAOUT[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[12]));
    SLE \ram_waddr[1]  (.D(N_359_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[1]));
    SLE \current_state[13]  (.D(\current_state_ns_i_i_0[13]_net_1 ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[13]_net_1 ));
    CFG4 #( .INIT(16'hAFCF) )  \current_state_ns_i_i_0[13]  (.A(
        \current_state[13]_net_1 ), .B(\current_state[9]_net_1 ), .C(
        N_341), .D(N_338), .Y(\current_state_ns_i_i_0[13]_net_1 ));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[20]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[20]), .FCI(\data_cry[19]_net_1 ), .S(
        \data_s[20] ), .Y(), .FCO(\data_cry[20]_net_1 ));
    CFG2 #( .INIT(4'hD) )  \data_cnst_o5_0_0[7]  (.A(N_121), .B(
        N_217_i), .Y(\data_13[7] ));
    CFG2 #( .INIT(4'hE) )  \current_state_RNIIUOE[6]  (.A(
        \current_state[11]_net_1 ), .B(\current_state[6]_net_1 ), .Y(
        N_152));
    CFG4 #( .INIT(16'hFA3A) )  \addr_temp_lm_0[29]  (.A(
        \addr_temp_s[29] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_121), .Y(\addr_temp_lm[29] ));
    SLE \ram_wdata[26]  (.D(AHB_IF_0_DATAOUT[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[26]));
    CFG3 #( .INIT(8'h06) )  \data_cnt_RNO[1]  (.A(\data_cnt[1]_net_1 ), 
        .B(\data_cnt[0]_net_1 ), .C(N_478_i_0), .Y(N_328_i_0));
    CFG2 #( .INIT(4'hE) )  ram_wdata_0_sqmuxa_i_0_o2 (.A(
        \current_state[14]_net_1 ), .B(\current_state[15]_net_1 ), .Y(
        N_119));
    CFG2 #( .INIT(4'h1) )  data_cnt_n0_i_a3 (.A(N_478_i_0), .B(
        \data_cnt[0]_net_1 ), .Y(N_423));
    CFG4 #( .INIT(16'h08F8) )  \current_state_ns_0_0[16]  (.A(
        AHB_IF_0_VALID), .B(\current_state[15]_net_1 ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_333), .Y(\current_state_ns[16] ));
    CFG3 #( .INIT(8'h8C) )  \addr_temp_cnst_i_a2_0_i_a3[2]  (.A(N_340), 
        .B(eSRAM_eNVM_access_0_MSS_READY), .C(N_121), .Y(N_252));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[4]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[4]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[3]_net_1 ), .S(\addr_temp_s[4] ), .Y(), .FCO(
        \addr_temp_cry[4]_net_1 ));
    SLE \addr_temp[2]  (.D(\addr_temp_lm[2] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[2]));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[4]  (.A(VCC_net_1), .B(N_121)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[4]), .FCI(
        \data_cry[3]_net_1 ), .S(\data_s[4] ), .Y(), .FCO(
        \data_cry[4]_net_1 ));
    CFG3 #( .INIT(8'h20) )  \addr_temp_cnst_i_a2_0_i_a3[3]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(AHB_IF_0_AHB_BUSY), .C(
        \current_state[7]_net_1 ), .Y(N_254));
    SLE \data[7]  (.D(\data_s[7] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[7]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[25]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[25]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[24]_net_1 ), .S(\addr_temp_s[25] ), .Y(), .FCO(
        \addr_temp_cry[25]_net_1 ));
    CFG4 #( .INIT(16'h55C3) )  \ram_waddr_RNO[3]  (.A(
        \current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ram_waddr[3]), 
        .C(N_117), .D(N_569), .Y(N_363_i_0));
    SLE \data[14]  (.D(\data_s[14] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[14]));
    SLE \data[0]  (.D(\data_s[0] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[0]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[9]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[9]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[8]_net_1 ), .S(\addr_temp_s[9] ), .Y(), .FCO(
        \addr_temp_cry[9]_net_1 ));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[5]  (.A(VCC_net_1), .B(N_121)
        , .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[5]), .FCI(
        \data_cry[4]_net_1 ), .S(\data_s[5] ), .Y(), .FCO(
        \data_cry[5]_net_1 ));
    CFG4 #( .INIT(16'h0008) )  \addr_temp_cnst_i_a2_0_i_a3_0[5]  (.A(
        \current_state[8]_net_1 ), .B(eSRAM_eNVM_access_0_MSS_READY), 
        .C(AHB_IF_0_AHB_BUSY), .D(AHB_IF_0_DATAOUT[0]), .Y(N_262));
    CFG4 #( .INIT(16'hFF04) )  \current_state_RNIRRSV1[13]  (.A(N_152), 
        .B(N_334), .C(\current_state[13]_net_1 ), .D(AHB_IF_0_AHB_BUSY)
        , .Y(N_821));
    SLE \ram_waddr[3]  (.D(N_363_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[3]));
    CFG3 #( .INIT(8'hF4) )  \current_state_RNI6JBF1[6]  (.A(
        AHB_IF_0_AHB_BUSY), .B(N_152), .C(N_478_i_0), .Y(data_cnte));
    CFG2 #( .INIT(4'h7) )  data_cnt_n1_i_o2 (.A(\data_cnt[0]_net_1 ), 
        .B(\data_cnt[1]_net_1 ), .Y(N_339));
    SLE \data_cnt[3]  (.D(N_330_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(data_cnte), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \data_cnt[3]_net_1 ));
    CFG4 #( .INIT(16'h88F0) )  \addr_temp_lm_0[11]  (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(\current_state[9]_net_1 ), 
        .C(\addr_temp_s[11] ), .D(N_821), .Y(\addr_temp_lm[11] ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[26]  (.A(N_821), .B(
        \addr_temp_s[26] ), .Y(\addr_temp_lm[26] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[19]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[19]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[18]_net_1 ), .S(\addr_temp_s[19] ), .Y(), .FCO(
        \addr_temp_cry[19]_net_1 ));
    SLE \ram_wdata[13]  (.D(AHB_IF_0_DATAOUT[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[13]));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_3 (.A(
        \current_state[11]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        \current_state[15]_net_1 ), .D(\current_state[5]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_3_net_1));
    SLE \ram_wdata[3]  (.D(AHB_IF_0_DATAOUT[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[3]));
    SLE \data_cnt[0]  (.D(N_423), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .EN(data_cnte), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\data_cnt[0]_net_1 ));
    SLE \current_state[12]  (.D(\current_state_ns[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[6]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[6]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[5]_net_1 ), .S(\addr_temp_s[6] ), .Y(), .FCO(
        \addr_temp_cry[6]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_1_1 (.A(
        \data_13[31] ), .B(N_119), .C(\current_state[11]_net_1 ), .D(
        \current_state[8]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1));
    SLE \data[15]  (.D(\data_s[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[15]));
    CFG3 #( .INIT(8'hFE) )  \current_state_RNIJKCS[12]  (.A(
        \current_state[9]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        \current_state[0]_net_1 ), .Y(ram_waddrlde_0_0_0));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[13]  (.A(N_821), .B(
        \addr_temp_s[13] ), .Y(\addr_temp_lm[13] ));
    CFG2 #( .INIT(4'h8) )  \current_state_RNIVC5B1[10]  (.A(N_474), .B(
        N_459), .Y(N_481));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[20]  (.A(N_821), .B(
        \addr_temp_s[20] ), .Y(\addr_temp_lm[20] ));
    CFG4 #( .INIT(16'h3010) )  un1_READ_1_sqmuxa_2_i_0_0_a3_1 (.A(
        \current_state[8]_net_1 ), .B(\current_state[14]_net_1 ), .C(
        N_467), .D(AHB_IF_0_DATAOUT[0]), .Y(
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1));
    CFG2 #( .INIT(4'h1) )  \current_state_RNIEFCS[10]  (.A(N_344), .B(
        \data_13[31] ), .Y(N_474));
    CFG4 #( .INIT(16'h000D) )  \addr_temp_lm_0_1[7]  (.A(
        \current_state[5]_net_1 ), .B(AHB_IF_0_AHB_BUSY), .C(
        \current_state[9]_net_1 ), .D(N_340), .Y(
        \addr_temp_lm_0_1[7]_net_1 ));
    CFG4 #( .INIT(16'h0103) )  ram_wdata_0_sqmuxa_i_0_a3_1_1_RNIFATP (
        .A(N_473), .B(N_338), .C(N_412), .D(
        ram_wdata_0_sqmuxa_i_0_a3_1_1_net_1), .Y(N_204_i_1));
    SLE \ram_wdata[25]  (.D(AHB_IF_0_DATAOUT[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[25]));
    SLE \data[29]  (.D(\data_s[29] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[29]));
    CFG2 #( .INIT(4'h1) )  un1_READ_1_sqmuxa_2_i_0_a2_0 (.A(
        \current_state[1]_net_1 ), .B(\current_state[3]_net_1 ), .Y(
        N_467));
    ARI1 #( .INIT(20'h4B8BB) )  \data_cry[7]  (.A(N_121), .B(
        eSRAM_eNVM_RW_0_DATAOUT[7]), .C(\data_cry_cy_Y[0] ), .D(
        N_217_i), .FCI(\data_cry[6]_net_1 ), .S(\data_s[7] ), .Y(), 
        .FCO(\data_cry[7]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \current_state_ns_0_0_o2[3]  (.A(
        AHB_IF_0_DATAOUT[0]), .B(\current_state[2]_net_1 ), .Y(N_335));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[25]  (.A(N_821), .B(
        \addr_temp_s[25] ), .Y(\addr_temp_lm[25] ));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[11]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[7] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[11]), .FCI(\data_cry[10]_net_1 ), .S(
        \data_s[11] ), .Y(), .FCO(\data_cry[11]_net_1 ));
    SLE \data[16]  (.D(\data_s[16] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[16]));
    SLE \ram_wdata[20]  (.D(AHB_IF_0_DATAOUT[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[20]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[15]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[15]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[14]_net_1 ), .S(\addr_temp_s[15] ), .Y(), .FCO(
        \addr_temp_cry[15]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[31]  (.A(N_821), .B(
        \addr_temp_s[31]_net_1 ), .Y(\addr_temp_lm[31] ));
    CFG3 #( .INIT(8'h01) )  un1_READ_1_sqmuxa_2_i_0_a2_1 (.A(
        \current_state[1]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        \current_state[3]_net_1 ), .Y(N_479));
    CFG2 #( .INIT(4'h8) )  \addr_temp_cnst_i_a2_0_i_a3[6]  (.A(N_340), 
        .B(eSRAM_eNVM_access_0_MSS_READY), .Y(N_266));
    CFG4 #( .INIT(16'h0007) )  ram_wdata_0_sqmuxa_i_0_o3_RNI07FK9 (.A(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_3), .B(
        un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0_2), .C(N_380), .D(
        un1_addr_temp_8_sqmuxa_2_i_i_0_1), .Y(N_164_i_0));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[8]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[8]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[7]_net_1 ), .S(\addr_temp_s[8] ), .Y(), .FCO(
        \addr_temp_cry[8]_net_1 ));
    SLE \ram_wdata[29]  (.D(AHB_IF_0_DATAOUT[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[29]));
    CFG4 #( .INIT(16'hFE30) )  un1_current_state_19_i_0_0_0 (.A(
        \current_state[4]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        N_476), .D(AHB_IF_0_DATAOUT[0]), .Y(
        un1_current_state_19_i_0_0_0_net_1));
    CFG3 #( .INIT(8'hFE) )  \current_state_RNIHICS[12]  (.A(
        \current_state[12]_net_1 ), .B(\current_state[7]_net_1 ), .C(
        \current_state[0]_net_1 ), .Y(N_478_i_0));
    CFG4 #( .INIT(16'hECCC) )  \data_cry_cy_RNO[0]  (.A(
        AHB_IF_0_DATAOUT[1]), .B(un1_READ6_3_0_0_1_2), .C(
        \current_state[4]_net_1 ), .D(AHB_IF_0_DATAOUT[2]), .Y(
        un1_READ6_3_0_0_1_3));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[22]  (.A(N_821), .B(
        \addr_temp_s[22] ), .Y(\addr_temp_lm[22] ));
    SLE start_envm_reg1 (.D(start_envm_reg_net_1), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        start_envm_reg1_net_1));
    CFG2 #( .INIT(4'hB) )  ram_waddr_n3_0_o2 (.A(N_342), .B(
        eSRAM_eNVM_RW_0_ram_waddr[2]), .Y(N_117));
    CFG4 #( .INIT(16'h0080) )  \current_state_RNI03DL2[9]  (.A(N_469), 
        .B(un1_addr_temp_8_sqmuxa_2_i_i_0_a3_0), .C(N_121), .D(N_340), 
        .Y(N_380));
    SLE \addr_temp[14]  (.D(\addr_temp_lm[14] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[14]));
    SLE \current_state[7]  (.D(\current_state_ns[7] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[7]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[13]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[13]), .D(
        GND_net_1), .FCI(\data_cry[12]_net_1 ), .S(\data_s[13] ), .Y(), 
        .FCO(\data_cry[13]_net_1 ));
    CFG3 #( .INIT(8'h40) )  \addr_temp_cnst_0_a2_0_0_a3[19]  (.A(
        \current_state[9]_net_1 ), .B(N_477), .C(N_121), .Y(N_264));
    CFG2 #( .INIT(4'hE) )  un1_ram_wen_0_sqmuxa_i_0_0_0 (.A(N_389), .B(
        ram_waddrlde_0_0_0), .Y(N_569));
    CFG4 #( .INIT(16'hFEF0) )  un1_current_state_20_i_0_0_0 (.A(
        \current_state[4]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        N_290), .D(AHB_IF_0_DATAOUT[0]), .Y(
        un1_current_state_20_i_0_0_0_net_1));
    SLE READ (.D(N_378_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_390_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_READ));
    SLE \addr_temp[24]  (.D(\addr_temp_lm[24] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[24]));
    CFG2 #( .INIT(4'hE) )  \current_state_RNI0A7R[2]  (.A(
        \current_state[4]_net_1 ), .B(\current_state[2]_net_1 ), .Y(
        N_344));
    SLE \data[2]  (.D(\data_s[2] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[2]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[2]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[2]), .D(
        GND_net_1), .FCI(\data_cry[1]_net_1 ), .S(\data_s[2] ), .Y(), 
        .FCO(\data_cry[2]_net_1 ));
    CFG4 #( .INIT(16'h0111) )  \current_state_RNIACPO5[4]  (.A(N_377), 
        .B(N_369_i_i_0_1), .C(\current_state[4]_net_1 ), .D(
        AHB_IF_0_DATAOUT[0]), .Y(N_45_i_0));
    CFG3 #( .INIT(8'h04) )  \addr_temp_cnst_i_a2_0_0_a3_1[8]  (.A(
        \current_state[7]_net_1 ), .B(N_333), .C(
        \current_state[1]_net_1 ), .Y(
        \addr_temp_cnst_i_a2_0_0_a3_1[8]_net_1 ));
    SLE ram_wen (.D(N_360_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), 
        .EN(N_387_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_ram_wen));
    SLE \addr_temp[4]  (.D(\addr_temp_lm[4] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[4]));
    CFG3 #( .INIT(8'hFE) )  un1_READ_1_sqmuxa_2_i_0_a3_0_RNIPF9V (.A(
        N_389), .B(ram_waddrlde_0_0_0), .C(N_360_i_0), .Y(ram_waddre));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[21]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[21]), .FCI(\data_cry[20]_net_1 ), .S(
        \data_s[21] ), .Y(), .FCO(\data_cry[21]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \current_state_RNIHTOE[16]  (.A(
        \current_state[0]_net_1 ), .B(\current_state[16]_net_1 ), .Y(
        N_459));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[23]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[23]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[22]_net_1 ), .S(\addr_temp_s[23] ), .Y(), .FCO(
        \addr_temp_cry[23]_net_1 ));
    SLE \data[27]  (.D(\data_s[27] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[27]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_s[31]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[31]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[30]_net_1 ), .S(\addr_temp_s[31]_net_1 ), .Y(), 
        .FCO());
    SLE \ram_wdata[27]  (.D(AHB_IF_0_DATAOUT[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[27]));
    SLE \data[28]  (.D(\data_s[28] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[28]));
    CFG2 #( .INIT(4'h2) )  \addr_temp_cnst_0_a2_0_0_a2[30]  (.A(N_341), 
        .B(\data_13[31] ), .Y(N_477));
    ARI1 #( .INIT(20'h48800) )  \data_cry[3]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[3]), .D(
        GND_net_1), .FCI(\data_cry[2]_net_1 ), .S(\data_s[3] ), .Y(), 
        .FCO(\data_cry[3]_net_1 ));
    CFG2 #( .INIT(4'h4) )  esram_select (.A(start_esram_reg1_net_1), 
        .B(start_esram_reg2_net_1), .Y(esram_select_net_1));
    CFG3 #( .INIT(8'hB3) )  envm_release_reg_RNINV5J (.A(
        \current_state[16]_net_1 ), .B(N_335), .C(
        envm_release_reg_net_1), .Y(N_340));
    CFG4 #( .INIT(16'h0C2E) )  \current_state_RNO[11]  (.A(
        \current_state[11]_net_1 ), .B(\data_13[31] ), .C(
        AHB_IF_0_AHB_BUSY), .D(N_475), .Y(N_336_i_0));
    ARI1 #( .INIT(20'h4D100) )  \data_cry[12]  (.A(VCC_net_1), .B(
        N_121), .C(\data_cry_cy_Y[0] ), .D(eSRAM_eNVM_RW_0_DATAOUT[12])
        , .FCI(\data_cry[11]_net_1 ), .S(\data_s[12] ), .Y(), .FCO(
        \data_cry[12]_net_1 ));
    CFG2 #( .INIT(4'hB) )  ram_waddr_n4_0_o2 (.A(N_117), .B(
        eSRAM_eNVM_RW_0_ram_waddr[3]), .Y(N_354));
    SLE envm_release_reg (.D(\current_state[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(un40_0_0_0_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        envm_release_reg_net_1));
    CFG3 #( .INIT(8'hB1) )  \addr_temp_lm_0[2]  (.A(N_821), .B(
        eSRAM_eNVM_RW_0_ADDR[2]), .C(N_252), .Y(\addr_temp_lm[2] ));
    SLE \data[19]  (.D(\data_s[19] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[19]));
    SLE \ram_waddr[0]  (.D(N_9_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[0]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[23]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[23]), .FCI(\data_cry[22]_net_1 ), .S(
        \data_s[23] ), .Y(), .FCO(\data_cry[23]_net_1 ));
    CFG3 #( .INIT(8'h80) )  \current_state_RNI2FBF1[10]  (.A(N_474), 
        .B(AHB_IF_0_AHB_BUSY), .C(N_459), .Y(N_377));
    SLE \current_state[4]  (.D(\current_state_ns_i_i_0[4]_net_1 ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[4]_net_1 ));
    SLE \data[22]  (.D(\data_s[22] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[22]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[30]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[30]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[29]_net_1 ), .S(\addr_temp_s[30] ), .Y(), .FCO(
        \addr_temp_cry[30]_net_1 ));
    CFG4 #( .INIT(16'h5D55) )  un1_READ_1_sqmuxa_2_i_0_a3_0_3_RNILIOB1 
        (.A(\current_state[14]_net_1 ), .B(
        eSRAM_eNVM_RW_0_ram_waddr[2]), .C(eSRAM_eNVM_RW_0_ram_waddr[0])
        , .D(un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1), .Y(N_334));
    CFG4 #( .INIT(16'hDF55) )  ram_wdata_0_sqmuxa_i_0_o3_RNI9N9M1 (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(\current_state[13]_net_1 ), 
        .C(N_334), .D(N_338), .Y(un1_addr_temp_8_sqmuxa_2_i_i_0_1));
    CFG4 #( .INIT(16'h8000) )  un1_READ_1_sqmuxa_2_i_0_a3_0_3 (.A(
        eSRAM_eNVM_RW_0_ram_waddr[3]), .B(eSRAM_eNVM_RW_0_ram_waddr[1])
        , .C(\current_state[14]_net_1 ), .D(
        eSRAM_eNVM_RW_0_ram_waddr[4]), .Y(
        un1_READ_1_sqmuxa_2_i_0_a3_0_3_net_1));
    SLE \addr_temp[10]  (.D(\addr_temp_lm[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[10]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[15]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[15]), .FCI(\data_cry[14]_net_1 ), .S(
        \data_s[15] ), .Y(), .FCO(\data_cry[15]_net_1 ));
    SLE \ram_waddr[2]  (.D(N_362_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(ram_waddre), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_ram_waddr[2]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[14]  (.A(N_821), .B(
        \addr_temp_s[14] ), .Y(\addr_temp_lm[14] ));
    SLE \addr_temp[8]  (.D(\addr_temp_lm[8] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[8]));
    ARI1 #( .INIT(20'h4E400) )  \data_s[31]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[31]), .FCI(\data_cry[30]_net_1 ), .S(
        \data_s[31]_net_1 ), .Y(), .FCO());
    CFG4 #( .INIT(16'h0151) )  \current_state_RNO[6]  (.A(N_457), .B(
        N_475), .C(\current_state[5]_net_1 ), .D(AHB_IF_0_AHB_BUSY), 
        .Y(N_330_i_0_0));
    SLE \current_state[10]  (.D(\current_state_ns[10] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(\data_13[31] ));
    SLE \current_state[0]  (.D(\current_state_ns[0] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[0]_net_1 ));
    SLE \ram_wdata[18]  (.D(AHB_IF_0_DATAOUT[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[18]));
    SLE \addr_temp[9]  (.D(\addr_temp_lm[9] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[9]));
    SLE \ram_wdata[7]  (.D(AHB_IF_0_DATAOUT[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[7]));
    SLE \addr_temp[20]  (.D(\addr_temp_lm[20] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[20]));
    SLE \addr_temp[17]  (.D(\addr_temp_lm[17] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[17]));
    CFG4 #( .INIT(16'h2A7F) )  \current_state_RNIKDK11_0[4]  (.A(
        \current_state[4]_net_1 ), .B(AHB_IF_0_DATAOUT[2]), .C(
        AHB_IF_0_DATAOUT[1]), .D(AHB_IF_0_DATAOUT[0]), .Y(N_351));
    SLE \addr_temp[5]  (.D(\addr_temp_lm[5] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[5]));
    CFG2 #( .INIT(4'hD) )  \data_cnst_o5_0_0[8]  (.A(N_121), .B(
        \data_13[31] ), .Y(\data_13[9] ));
    CFG4 #( .INIT(16'hF4F0) )  \current_state_ns_i_i_0[1]  (.A(
        \current_state[0]_net_1 ), .B(\current_state[1]_net_1 ), .C(
        N_444), .D(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns_i_i_0[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[13]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[13]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[12]_net_1 ), .S(\addr_temp_s[13] ), .Y(), .FCO(
        \addr_temp_cry[13]_net_1 ));
    SLE \addr_temp[11]  (.D(\addr_temp_lm[11] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[11]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[28]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[28]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[27]_net_1 ), .S(\addr_temp_s[28] ), .Y(), .FCO(
        \addr_temp_cry[28]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[1]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[1]), .D(
        GND_net_1), .FCI(\data_cry[0]_net_1 ), .S(\data_s[1] ), .Y(), 
        .FCO(\data_cry[1]_net_1 ));
    CFG4 #( .INIT(16'h40C0) )  ram_wdata_0_sqmuxa_i_0_a3_5_RNID0JJ2 (
        .A(ram_wdata_0_sqmuxa_i_0_a3_5_net_1), .B(
        eSRAM_eNVM_access_0_MSS_READY), .C(N_204_i_1), .D(N_334), .Y(
        N_204_i_0));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[27]  (.A(N_821), .B(
        \addr_temp_s[27] ), .Y(\addr_temp_lm[27] ));
    SLE \ram_wdata[2]  (.D(AHB_IF_0_DATAOUT[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[2]));
    CFG3 #( .INIT(8'h40) )  un1_current_state_20_i_0_0_a3_1 (.A(
        \current_state[14]_net_1 ), .B(N_479), .C(N_459), .Y(
        un1_current_state_20_i_0_0_a3_1_net_1));
    SLE \addr_temp[27]  (.D(\addr_temp_lm[27] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[27]));
    CFG4 #( .INIT(16'hF2F0) )  un1_current_state_19_i_0_0_1 (.A(N_469), 
        .B(\current_state[12]_net_1 ), .C(
        un1_current_state_19_i_0_0_0_net_1), .D(N_481), .Y(
        un1_current_state_19_i_0_0_1_net_1));
    SLE \ram_wdata[16]  (.D(AHB_IF_0_DATAOUT[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[16]));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[28]  (.A(N_821), .B(
        \addr_temp_s[28] ), .Y(\addr_temp_lm[28] ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[22]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[22]), .D(
        GND_net_1), .FCI(\data_cry[21]_net_1 ), .S(\data_s[22] ), .Y(), 
        .FCO(\data_cry[22]_net_1 ));
    CFG4 #( .INIT(16'h0400) )  \current_state_ns_i_i_0_a3_0[1]  (.A(
        start_envm_reg1_net_1), .B(start_envm_reg2_net_1), .C(
        esram_select_net_1), .D(\current_state[0]_net_1 ), .Y(N_444));
    CFG3 #( .INIT(8'hAE) )  \current_state_ns_0_0[8]  (.A(N_217_i), .B(
        \current_state[8]_net_1 ), .C(AHB_IF_0_DATAOUT[0]), .Y(
        \current_state_ns[8] ));
    SLE \addr_temp[21]  (.D(\addr_temp_lm[21] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[21]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[5]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[5]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[4]_net_1 ), .S(\addr_temp_s[5] ), .Y(), .FCO(
        \addr_temp_cry[5]_net_1 ));
    SLE \current_state[14]  (.D(N_341_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[14]_net_1 ));
    SLE \addr_temp[19]  (.D(\addr_temp_lm[19] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[19]));
    SLE \ram_wdata[21]  (.D(AHB_IF_0_DATAOUT[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[21]));
    SLE \current_state[11]  (.D(N_336_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[11]_net_1 ));
    CFG4 #( .INIT(16'hFBC8) )  \addr_temp_lm_0[6]  (.A(N_266), .B(
        N_821), .C(N_254), .D(\addr_temp_s[6] ), .Y(\addr_temp_lm[6] ));
    CFG4 #( .INIT(16'h0111) )  WRITE_RNO_6 (.A(
        \current_state[16]_net_1 ), .B(\current_state[2]_net_1 ), .C(
        AHB_IF_0_DATAOUT[1]), .D(AHB_IF_0_DATAOUT[2]), .Y(
        un1_current_state_16_0_0_i_0_0_a3_1_1));
    CFG4 #( .INIT(16'h0008) )  un1_current_state_20_i_0_0_a3_2 (.A(
        N_457), .B(un1_current_state_20_i_0_0_a3_1_net_1), .C(
        \current_state[11]_net_1 ), .D(\data_13[31] ), .Y(
        un1_current_state_20_i_0_0_a3_2_net_1));
    CFG4 #( .INIT(16'hFCAC) )  \addr_temp_lm_0[5]  (.A(N_262), .B(
        \addr_temp_s[5] ), .C(N_821), .D(N_260), .Y(\addr_temp_lm[5] ));
    CFG4 #( .INIT(16'hFFBF) )  \current_state_ns_i_i_0_o2[4]  (.A(
        \current_state[3]_net_1 ), .B(AHB_IF_0_DATAOUT[2]), .C(
        AHB_IF_0_DATAOUT[1]), .D(AHB_IF_0_DATAOUT[0]), .Y(N_368));
    ARI1 #( .INIT(20'h48800) )  \data_cry[25]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[25]), .D(
        GND_net_1), .FCI(\data_cry[24]_net_1 ), .S(\data_s[25] ), .Y(), 
        .FCO(\data_cry[25]_net_1 ));
    SLE \data[17]  (.D(\data_s[17] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[17]));
    SLE \addr_temp[29]  (.D(\addr_temp_lm[29] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[29]));
    CFG4 #( .INIT(16'h3230) )  un1_READ_1_sqmuxa_2_i_0_0_0 (.A(
        un1_READ_1_sqmuxa_2_i_0_a3_1_0_net_1), .B(
        \current_state[14]_net_1 ), .C(N_469), .D(N_479), .Y(
        un1_READ_1_sqmuxa_2_i_0_0_0_net_1));
    SLE \current_state[8]  (.D(\current_state_ns[8] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[8]_net_1 ));
    SLE \current_state[1]  (.D(\current_state_ns_i_i_0[1]_net_1 ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[1]_net_1 ));
    SLE \current_state[15]  (.D(\current_state_ns[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[21]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[21]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[20]_net_1 ), .S(\addr_temp_s[21] ), .Y(), .FCO(
        \addr_temp_cry[21]_net_1 ));
    SLE WRITE (.D(N_792_i_0), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_392_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_WRITE));
    CFG3 #( .INIT(8'h41) )  \data_cnt_RNO[4]  (.A(N_478_i_0), .B(
        \data_cnt[4]_net_1 ), .C(N_346), .Y(N_331_i_0));
    SLE \data[18]  (.D(\data_s[18] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[18]));
    ARI1 #( .INIT(20'h4E400) )  \data_cry[14]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(\data_13[31] ), .D(
        eSRAM_eNVM_RW_0_DATAOUT[14]), .FCI(\data_cry[13]_net_1 ), .S(
        \data_s[14] ), .Y(), .FCO(\data_cry[14]_net_1 ));
    SLE \data[20]  (.D(\data_s[20] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[20]));
    CFG3 #( .INIT(8'hEA) )  \current_state_ns_0_0[15]  (.A(N_389), .B(
        \current_state[15]_net_1 ), .C(N_338), .Y(
        \current_state_ns[15] ));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[22]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[22]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[21]_net_1 ), .S(\addr_temp_s[22] ), .Y(), .FCO(
        \addr_temp_cry[22]_net_1 ));
    CFG4 #( .INIT(16'h5300) )  \addr_temp_cnst_i_a2_0_0_a3[8]  (.A(
        \current_state[2]_net_1 ), .B(\current_state[8]_net_1 ), .C(
        AHB_IF_0_DATAOUT[0]), .D(
        \addr_temp_cnst_i_a2_0_0_a3_1[8]_net_1 ), .Y(N_269));
    SLE \current_state[3]  (.D(\current_state_ns[3] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[3]_net_1 ));
    SLE \current_state[9]  (.D(\current_state_ns[9] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \current_state[9]_net_1 ));
    SLE \data[23]  (.D(\data_s[23] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[23]));
    CFG3 #( .INIT(8'hC5) )  \current_state_ns_0_0[3]  (.A(N_335), .B(
        \current_state[3]_net_1 ), .C(AHB_IF_0_AHB_BUSY), .Y(
        \current_state_ns[3] ));
    CFG3 #( .INIT(8'h10) )  WRITE_RNO_4 (.A(\current_state[16]_net_1 ), 
        .B(\current_state[4]_net_1 ), .C(N_335), .Y(
        un1_current_state_16_0_0_i_0_0_a3_0));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[18]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[18]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[17]_net_1 ), .S(\addr_temp_s[18] ), .Y(), .FCO(
        \addr_temp_cry[18]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \current_state_RNI7RPH[7]  (.A(
        AHB_IF_0_AHB_BUSY), .B(\current_state[7]_net_1 ), .Y(N_217_i));
    CFG4 #( .INIT(16'h007F) )  WRITE_RNO_0 (.A(N_466), .B(
        un1_current_state_19_i_0_0_a3_0_1_net_1), .C(N_337), .D(
        un1_current_state_19_i_0_0_1_net_1), .Y(N_392_i_0));
    CFG4 #( .INIT(16'h0F0D) )  ram_wen_RNO (.A(N_459), .B(
        \current_state[13]_net_1 ), .C(N_389), .D(N_360_i_0), .Y(
        N_387_i_0));
    CFG4 #( .INIT(16'hFA3A) )  \addr_temp_lm_0[19]  (.A(
        \addr_temp_s[19] ), .B(eSRAM_eNVM_access_0_MSS_READY), .C(
        N_821), .D(N_264), .Y(\addr_temp_lm[19] ));
    SLE \addr_temp[12]  (.D(\addr_temp_lm[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[12]));
    CFG4 #( .INIT(16'h0001) )  ram_wdata_0_sqmuxa_i_0_a3_0_2 (.A(
        \current_state[13]_net_1 ), .B(\current_state[12]_net_1 ), .C(
        \current_state[7]_net_1 ), .D(\current_state[4]_net_1 ), .Y(
        ram_wdata_0_sqmuxa_i_0_a3_0_2_net_1));
    SLE \ram_wdata[24]  (.D(AHB_IF_0_DATAOUT[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[24]));
    CFG4 #( .INIT(16'hEAC0) )  \current_state_ns_0_0[10]  (.A(
        AHB_IF_0_AHB_BUSY), .B(esram_select_net_1), .C(
        \current_state[0]_net_1 ), .D(\data_13[31] ), .Y(
        \current_state_ns[10] ));
    SLE \data[12]  (.D(\data_s[12] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[12]));
    SLE \addr_temp[18]  (.D(\addr_temp_lm[18] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[18]));
    CFG4 #( .INIT(16'h0007) )  READ_RNO (.A(
        un1_READ_1_sqmuxa_2_i_0_0_a3_1_net_1), .B(N_473), .C(N_389), 
        .D(un1_READ_1_sqmuxa_2_i_0_0_0_net_1), .Y(N_378_i_0));
    SLE \ram_wdata[15]  (.D(AHB_IF_0_DATAOUT[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[15]));
    SLE \ram_wdata[1]  (.D(AHB_IF_0_DATAOUT[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[1]));
    ARI1 #( .INIT(20'h48800) )  \data_cry[19]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[19]), .D(
        GND_net_1), .FCI(\data_cry[18]_net_1 ), .S(\data_s[19] ), .Y(), 
        .FCO(\data_cry[19]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[18]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[18]), .D(
        GND_net_1), .FCI(\data_cry[17]_net_1 ), .S(\data_s[18] ), .Y(), 
        .FCO(\data_cry[18]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \data_cry[30]  (.A(VCC_net_1), .B(
        \data_cry_cy_Y[0] ), .C(eSRAM_eNVM_RW_0_DATAOUT[30]), .D(
        GND_net_1), .FCI(\data_cry[29]_net_1 ), .S(\data_s[30] ), .Y(), 
        .FCO(\data_cry[30]_net_1 ));
    CFG2 #( .INIT(4'hB) )  ram_wdata_0_sqmuxa_i_0_o3 (.A(
        AHB_IF_0_AHB_BUSY), .B(AHB_IF_0_VALID), .Y(N_338));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[21]  (.A(N_821), .B(
        \addr_temp_s[21] ), .Y(\addr_temp_lm[21] ));
    SLE \addr_temp[22]  (.D(\addr_temp_lm[22] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[22]));
    SLE \ram_wdata[22]  (.D(AHB_IF_0_DATAOUT[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[22]));
    SLE \ram_wdata[10]  (.D(AHB_IF_0_DATAOUT[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[10]));
    CFG3 #( .INIT(8'h4E) )  \addr_temp_lm_0[8]  (.A(N_821), .B(
        \addr_temp_s[8] ), .C(\addr_temp_cnst_i_a2_0_0[8]_net_1 ), .Y(
        \addr_temp_lm[8] ));
    SLE \data[21]  (.D(\data_s[21] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_45_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eSRAM_eNVM_RW_0_DATAOUT[21]));
    SLE \addr_temp[28]  (.D(\addr_temp_lm[28] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[28]));
    CFG3 #( .INIT(8'hF1) )  un40_0_0_0 (.A(N_333), .B(
        AHB_IF_0_AHB_BUSY), .C(\current_state[9]_net_1 ), .Y(
        un40_0_0_0_net_1));
    CFG4 #( .INIT(16'h0C06) )  \data_cnt_RNO[3]  (.A(
        \data_cnt[2]_net_1 ), .B(\data_cnt[3]_net_1 ), .C(N_478_i_0), 
        .D(N_339), .Y(N_330_i_0));
    CFG2 #( .INIT(4'h4) )  \addr_temp_lm_0[23]  (.A(N_821), .B(
        \addr_temp_s[23] ), .Y(\addr_temp_lm[23] ));
    SLE \addr_temp[15]  (.D(\addr_temp_lm[15] ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_164_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ADDR[15]));
    SLE \ram_wdata[19]  (.D(AHB_IF_0_DATAOUT[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[19]));
    SLE \ram_wdata[0]  (.D(AHB_IF_0_DATAOUT[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[0]));
    SLE \ram_wdata[30]  (.D(AHB_IF_0_DATAOUT[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_204_i_0), .ALn(VCC_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(eSRAM_eNVM_RW_0_ram_wdata[30]));
    ARI1 #( .INIT(20'h4AA00) )  \addr_temp_cry[11]  (.A(VCC_net_1), .B(
        eSRAM_eNVM_RW_0_ADDR[11]), .C(GND_net_1), .D(GND_net_1), .FCI(
        \addr_temp_cry[10]_net_1 ), .S(\addr_temp_s[11] ), .Y(), .FCO(
        \addr_temp_cry[11]_net_1 ));
    SLE \data[3]  (.D(\data_s[3] ), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .EN(N_45_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(eSRAM_eNVM_RW_0_DATAOUT[3]));
    
endmodule


module AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(
       eSRAM_eNVM_RW_0_DATAOUT,
       AHB_IF_0_DATAOUT,
       AHB_IF_0_BIF_1_HRDATA,
       AHB_IF_0_BIF_1_HWDATA,
       AHB_IF_0_BIF_1_HADDR,
       AHB_IF_0_BIF_1_HTRANS,
       eSRAM_eNVM_RW_0_ADDR,
       eSRAM_eNVM_access_0_FIC_0_CLK,
       eSRAM_eNVM_access_0_MSS_READY,
       AHB_IF_0_VALID,
       AHB_IF_0_AHB_BUSY,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_iv,
       eSRAM_eNVM_RW_0_WRITE,
       eSRAM_eNVM_RW_0_READ
    );
input  [31:0] eSRAM_eNVM_RW_0_DATAOUT;
output [31:0] AHB_IF_0_DATAOUT;
input  [31:0] AHB_IF_0_BIF_1_HRDATA;
output [31:0] AHB_IF_0_BIF_1_HWDATA;
output [31:2] AHB_IF_0_BIF_1_HADDR;
output [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] eSRAM_eNVM_RW_0_ADDR;
input  eSRAM_eNVM_access_0_FIC_0_CLK;
input  eSRAM_eNVM_access_0_MSS_READY;
output AHB_IF_0_VALID;
output AHB_IF_0_AHB_BUSY;
output AHB_IF_0_BIF_1_HWRITE;
input  HREADY_M_iv;
input  eSRAM_eNVM_RW_0_WRITE;
input  eSRAM_eNVM_RW_0_READ;

    wire \HWDATA_int[20]_net_1 , VCC_net_1, HWDATA_int_0_sqmuxa, 
        GND_net_1, \HWDATA_int[21]_net_1 , \HWDATA_int[22]_net_1 , 
        \HWDATA_int[23]_net_1 , \HWDATA_int[24]_net_1 , 
        \HWDATA_int[25]_net_1 , \HWDATA_int[26]_net_1 , 
        \HWDATA_int[27]_net_1 , \HWDATA_int[28]_net_1 , 
        \HWDATA_int[29]_net_1 , \HWDATA_int[30]_net_1 , 
        \HWDATA_int[31]_net_1 , \HWDATA_int[5]_net_1 , 
        \HWDATA_int[6]_net_1 , \HWDATA_int[7]_net_1 , 
        \HWDATA_int[8]_net_1 , \HWDATA_int[9]_net_1 , 
        \HWDATA_int[10]_net_1 , \HWDATA_int[11]_net_1 , 
        \HWDATA_int[12]_net_1 , \HWDATA_int[13]_net_1 , 
        \HWDATA_int[14]_net_1 , \HWDATA_int[15]_net_1 , 
        \HWDATA_int[16]_net_1 , \HWDATA_int[17]_net_1 , 
        \HWDATA_int[18]_net_1 , \HWDATA_int[19]_net_1 , 
        DATAOUT_1_sqmuxa, \HWDATA_int[0]_net_1 , \HWDATA_int[1]_net_1 , 
        \HWDATA_int[2]_net_1 , \HWDATA_int[3]_net_1 , 
        \HWDATA_int[4]_net_1 , HWDATA_1_sqmuxa, \HADDR_6[26]_net_1 , 
        N_101_i_0, \HADDR_6[27]_net_1 , \HADDR_6[28]_net_1 , 
        \HADDR_6[29]_net_1 , \HADDR_6[30]_net_1 , \HADDR_6[31]_net_1 , 
        \HADDR_6[11]_net_1 , \HADDR_6[12]_net_1 , \HADDR_6[13]_net_1 , 
        \HADDR_6[14]_net_1 , \HADDR_6[15]_net_1 , \HADDR_6[16]_net_1 , 
        \HADDR_6[17]_net_1 , \HADDR_6[18]_net_1 , \HADDR_6[19]_net_1 , 
        \HADDR_6[20]_net_1 , \HADDR_6[21]_net_1 , \HADDR_6[22]_net_1 , 
        \HADDR_6[23]_net_1 , \HADDR_6[24]_net_1 , \HADDR_6[25]_net_1 , 
        \HADDR_6[2]_net_1 , \HADDR_6[3]_net_1 , \HADDR_6[4]_net_1 , 
        \HADDR_6[5]_net_1 , \HADDR_6[6]_net_1 , \HADDR_6[7]_net_1 , 
        \HADDR_6[8]_net_1 , \HADDR_6[9]_net_1 , \HADDR_6[10]_net_1 , 
        un18_0_0_net_1, N_107, N_106_i_0, N_126_i_0, 
        un1_ahb_fsm_current_state_8_0_0_net_1, 
        \ahb_fsm_current_state[1]_net_1 , 
        un1_ahb_fsm_current_state_4_0_0_net_1, 
        \ahb_fsm_current_state[0]_net_1 , 
        \ahb_fsm_current_state_ns[0] , N_94_i_0, 
        \ahb_fsm_current_state[2]_net_1 , 
        \ahb_fsm_current_state_ns[2]_net_1 , 
        \ahb_fsm_current_state[3]_net_1 , 
        \ahb_fsm_current_state[4]_net_1 , 
        \ahb_fsm_current_state_ns[4] , 
        \ahb_fsm_current_state[5]_net_1 , 
        \ahb_fsm_current_state_ns[5] , 
        \ahb_fsm_current_state[6]_net_1 , N_185, N_163, N_40, 
        un1_HADDR_0_sqmuxa_i_0_0_net_1;
    
    SLE \HADDR[9]  (.D(\HADDR_6[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[9]));
    SLE \HADDR[19]  (.D(\HADDR_6[19]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[19]));
    SLE \DATAOUT[2]  (.D(AHB_IF_0_BIF_1_HRDATA[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[2]));
    SLE \HADDR[8]  (.D(\HADDR_6[8]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[8]));
    SLE \HWDATA_int[0]  (.D(eSRAM_eNVM_RW_0_DATAOUT[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[0]_net_1 ));
    SLE \HWDATA_int[29]  (.D(eSRAM_eNVM_RW_0_DATAOUT[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[29]_net_1 ));
    SLE \HWDATA[5]  (.D(\HWDATA_int[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[5]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[10]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[10])
        , .Y(\HADDR_6[10]_net_1 ));
    SLE \ahb_fsm_current_state[3]  (.D(
        \ahb_fsm_current_state[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HREADY_M_iv), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[3]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[3]), 
        .Y(\HADDR_6[3]_net_1 ));
    SLE \DATAOUT[1]  (.D(AHB_IF_0_BIF_1_HRDATA[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[1]));
    SLE \DATAOUT[21]  (.D(AHB_IF_0_BIF_1_HRDATA[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[21]));
    SLE \DATAOUT[22]  (.D(AHB_IF_0_BIF_1_HRDATA[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[22]));
    SLE \HWDATA_int[9]  (.D(eSRAM_eNVM_RW_0_DATAOUT[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[9]_net_1 ));
    SLE \ahb_fsm_current_state[5]  (.D(\ahb_fsm_current_state_ns[5] ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[5]_net_1 ));
    SLE \HADDR[6]  (.D(\HADDR_6[6]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[6]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[29]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[29])
        , .Y(\HADDR_6[29]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[28]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[28])
        , .Y(\HADDR_6[28]_net_1 ));
    SLE \DATAOUT[23]  (.D(AHB_IF_0_BIF_1_HRDATA[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[23]));
    SLE \HADDR[18]  (.D(\HADDR_6[18]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[18]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[5]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[5]), 
        .Y(\HADDR_6[5]_net_1 ));
    CFG4 #( .INIT(16'hCCCD) )  un1_HADDR_0_sqmuxa_i_0_0 (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(N_40), .C(
        \ahb_fsm_current_state[5]_net_1 ), .D(
        \ahb_fsm_current_state[2]_net_1 ), .Y(
        un1_HADDR_0_sqmuxa_i_0_0_net_1));
    SLE \HWDATA_int[7]  (.D(eSRAM_eNVM_RW_0_DATAOUT[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[7]_net_1 ));
    SLE \HWDATA_int[18]  (.D(eSRAM_eNVM_RW_0_DATAOUT[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[18]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[27]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[27])
        , .Y(\HADDR_6[27]_net_1 ));
    SLE \HADDR[3]  (.D(\HADDR_6[3]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[3]));
    SLE \DATAOUT[0]  (.D(AHB_IF_0_BIF_1_HRDATA[0]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[0]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[15]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[15])
        , .Y(\HADDR_6[15]_net_1 ));
    SLE \DATAOUT[14]  (.D(AHB_IF_0_BIF_1_HRDATA[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[14]));
    SLE \DATAOUT[28]  (.D(AHB_IF_0_BIF_1_HRDATA[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[28]));
    SLE \HWDATA[2]  (.D(\HWDATA_int[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[2]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[30]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[30])
        , .Y(\HADDR_6[30]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[8]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[8]), 
        .Y(\HADDR_6[8]_net_1 ));
    SLE \DATAOUT[3]  (.D(AHB_IF_0_BIF_1_HRDATA[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[3]));
    CFG2 #( .INIT(4'h8) )  \ahb_fsm_current_state_RNO[1]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_WRITE), 
        .Y(N_94_i_0));
    SLE \HWDATA_int[16]  (.D(eSRAM_eNVM_RW_0_DATAOUT[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[16]_net_1 ));
    SLE \HADDR[29]  (.D(\HADDR_6[29]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[29]));
    SLE \ahb_fsm_current_state[1]  (.D(N_94_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[1]_net_1 ));
    SLE \HWDATA[3]  (.D(\HWDATA_int[3]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[3]));
    CFG2 #( .INIT(4'hE) )  \ahb_fsm_current_state_ns_0_o3[0]  (.A(
        \ahb_fsm_current_state[6]_net_1 ), .B(
        \ahb_fsm_current_state[3]_net_1 ), .Y(N_163));
    SLE \DATAOUT[30]  (.D(AHB_IF_0_BIF_1_HRDATA[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[30]));
    SLE \HWDATA_int[1]  (.D(eSRAM_eNVM_RW_0_DATAOUT[1]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[1]_net_1 ));
    GND GND (.Y(GND_net_1));
    SLE \HADDR[12]  (.D(\HADDR_6[12]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[12]));
    CFG3 #( .INIT(8'h37) )  \HTRANS_1_RNO[1]  (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(HREADY_M_iv), .C(
        \ahb_fsm_current_state[5]_net_1 ), .Y(N_126_i_0));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[14]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[14])
        , .Y(\HADDR_6[14]_net_1 ));
    CFG2 #( .INIT(4'hD) )  AHB_BUSY_RNO (.A(HREADY_M_iv), .B(
        \ahb_fsm_current_state[0]_net_1 ), .Y(N_107));
    SLE \HWDATA[17]  (.D(\HWDATA_int[17]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[17]));
    SLE \DATAOUT[17]  (.D(AHB_IF_0_BIF_1_HRDATA[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[17]));
    SLE \HADDR[28]  (.D(\HADDR_6[28]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[28]));
    SLE \HADDR[13]  (.D(\HADDR_6[13]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[13]));
    SLE \DATAOUT[26]  (.D(AHB_IF_0_BIF_1_HRDATA[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[26]));
    SLE AHB_BUSY (.D(N_107), .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        N_106_i_0), .ALn(eSRAM_eNVM_access_0_MSS_READY), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(AHB_IF_0_AHB_BUSY));
    SLE \ahb_fsm_current_state[4]  (.D(\ahb_fsm_current_state_ns[4] ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[4]_net_1 ));
    CFG4 #( .INIT(16'hC0CA) )  \ahb_fsm_current_state_ns_0[0]  (.A(
        N_40), .B(HREADY_M_iv), .C(N_163), .D(N_185), .Y(
        \ahb_fsm_current_state_ns[0] ));
    CFG3 #( .INIT(8'hAE) )  \ahb_fsm_current_state_ns_0[5]  (.A(
        \ahb_fsm_current_state[4]_net_1 ), .B(
        \ahb_fsm_current_state[5]_net_1 ), .C(HREADY_M_iv), .Y(
        \ahb_fsm_current_state_ns[5] ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[11]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[11])
        , .Y(\HADDR_6[11]_net_1 ));
    SLE \HWDATA_int[28]  (.D(eSRAM_eNVM_RW_0_DATAOUT[28]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[28]_net_1 ));
    SLE \DATAOUT[29]  (.D(AHB_IF_0_BIF_1_HRDATA[29]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[29]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[12]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[12])
        , .Y(\HADDR_6[12]_net_1 ));
    SLE \DATAOUT[10]  (.D(AHB_IF_0_BIF_1_HRDATA[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[10]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[2]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[2]), 
        .Y(\HADDR_6[2]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[20]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[20])
        , .Y(\HADDR_6[20]_net_1 ));
    SLE \DATAOUT[6]  (.D(AHB_IF_0_BIF_1_HRDATA[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[6]));
    SLE \HWDATA_int[26]  (.D(eSRAM_eNVM_RW_0_DATAOUT[26]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[26]_net_1 ));
    SLE \HWDATA[27]  (.D(\HWDATA_int[27]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[27]));
    VCC VCC (.Y(VCC_net_1));
    SLE \HWDATA[8]  (.D(\HWDATA_int[8]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[8]));
    SLE \HWDATA_int[5]  (.D(eSRAM_eNVM_RW_0_DATAOUT[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[5]_net_1 ));
    SLE \HWDATA_int[11]  (.D(eSRAM_eNVM_RW_0_DATAOUT[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[11]_net_1 ));
    SLE \HADDR[22]  (.D(\HADDR_6[22]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[22]));
    CFG3 #( .INIT(8'hFE) )  un1_ahb_fsm_current_state_4_0_0 (.A(
        \ahb_fsm_current_state[1]_net_1 ), .B(HWDATA_1_sqmuxa), .C(
        \ahb_fsm_current_state[4]_net_1 ), .Y(
        un1_ahb_fsm_current_state_4_0_0_net_1));
    SLE \HWDATA[18]  (.D(\HWDATA_int[18]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[18]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[31]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[31])
        , .Y(\HADDR_6[31]_net_1 ));
    SLE \HWDATA[15]  (.D(\HWDATA_int[15]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[15]));
    CFG3 #( .INIT(8'hAE) )  \ahb_fsm_current_state_ns[2]  (.A(
        \ahb_fsm_current_state[1]_net_1 ), .B(
        \ahb_fsm_current_state[2]_net_1 ), .C(HREADY_M_iv), .Y(
        \ahb_fsm_current_state_ns[2]_net_1 ));
    SLE \HWDATA[14]  (.D(\HWDATA_int[14]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[14]));
    SLE \HADDR[23]  (.D(\HADDR_6[23]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[23]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[25]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[25])
        , .Y(\HADDR_6[25]_net_1 ));
    SLE \DATAOUT[5]  (.D(AHB_IF_0_BIF_1_HRDATA[5]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[5]));
    SLE \HWDATA_int[13]  (.D(eSRAM_eNVM_RW_0_DATAOUT[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[13]_net_1 ));
    CFG2 #( .INIT(4'h8) )  un18_0_0_a2 (.A(HREADY_M_iv), .B(
        \ahb_fsm_current_state[6]_net_1 ), .Y(DATAOUT_1_sqmuxa));
    SLE \HWDATA[4]  (.D(\HWDATA_int[4]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[4]));
    SLE \DATAOUT[7]  (.D(AHB_IF_0_BIF_1_HRDATA[7]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[7]));
    SLE \HWDATA[7]  (.D(\HWDATA_int[7]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[7]));
    SLE \HWDATA[0]  (.D(\HWDATA_int[0]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[0]));
    SLE \HADDR[15]  (.D(\HADDR_6[15]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[15]));
    SLE \HWDATA[28]  (.D(\HWDATA_int[28]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[28]));
    SLE \HADDR[17]  (.D(\HADDR_6[17]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[17]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[16]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[16])
        , .Y(\HADDR_6[16]_net_1 ));
    SLE \HWDATA[11]  (.D(\HWDATA_int[11]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[11]));
    SLE \HWDATA[25]  (.D(\HWDATA_int[25]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[25]));
    SLE \DATAOUT[24]  (.D(AHB_IF_0_BIF_1_HRDATA[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[24]));
    SLE \HWDATA_int[10]  (.D(eSRAM_eNVM_RW_0_DATAOUT[10]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[10]_net_1 ));
    SLE \HADDR[11]  (.D(\HADDR_6[11]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[11]));
    SLE \DATAOUT[31]  (.D(AHB_IF_0_BIF_1_HRDATA[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[31]));
    SLE \HWDATA[24]  (.D(\HWDATA_int[24]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[24]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[24]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[24])
        , .Y(\HADDR_6[24]_net_1 ));
    SLE \HWDATA_int[21]  (.D(eSRAM_eNVM_RW_0_DATAOUT[21]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[21]_net_1 ));
    SLE \HWDATA_int[14]  (.D(eSRAM_eNVM_RW_0_DATAOUT[14]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[14]_net_1 ));
    SLE \HADDR[16]  (.D(\HADDR_6[16]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[16]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[4]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[4]), 
        .Y(\HADDR_6[4]_net_1 ));
    SLE \HTRANS_1[1]  (.D(N_126_i_0), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        un1_ahb_fsm_current_state_8_0_0_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HTRANS[1]));
    SLE \HWDATA_int[2]  (.D(eSRAM_eNVM_RW_0_DATAOUT[2]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[2]_net_1 ));
    CFG3 #( .INIT(8'h80) )  HWDATA_int_0_sqmuxa_0_a2 (.A(
        eSRAM_eNVM_access_0_MSS_READY), .B(
        \ahb_fsm_current_state[0]_net_1 ), .C(eSRAM_eNVM_RW_0_WRITE), 
        .Y(HWDATA_int_0_sqmuxa));
    SLE \HWDATA[31]  (.D(\HWDATA_int[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[31]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[21]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[21])
        , .Y(\HADDR_6[21]_net_1 ));
    SLE \HWDATA_int[6]  (.D(eSRAM_eNVM_RW_0_DATAOUT[6]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[6]_net_1 ));
    SLE \HWDATA[13]  (.D(\HWDATA_int[13]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[13]));
    CFG4 #( .INIT(16'hFFEA) )  un1_ahb_fsm_current_state_8_0_0 (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(
        \ahb_fsm_current_state[5]_net_1 ), .C(HREADY_M_iv), .D(N_185), 
        .Y(un1_ahb_fsm_current_state_8_0_0_net_1));
    CFG3 #( .INIT(8'h32) )  un1_HADDR_0_sqmuxa_i_0_0_RNI10IJ (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(
        un1_HADDR_0_sqmuxa_i_0_0_net_1), .C(HREADY_M_iv), .Y(N_101_i_0)
        );
    SLE \DATAOUT[15]  (.D(AHB_IF_0_BIF_1_HRDATA[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[15]));
    SLE \HWDATA_int[8]  (.D(eSRAM_eNVM_RW_0_DATAOUT[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[8]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[13]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[13])
        , .Y(\HADDR_6[13]_net_1 ));
    SLE \HADDR[31]  (.D(\HADDR_6[31]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[31]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[22]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[22])
        , .Y(\HADDR_6[22]_net_1 ));
    SLE \HWDATA_int[23]  (.D(eSRAM_eNVM_RW_0_DATAOUT[23]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[23]_net_1 ));
    SLE \HWDATA[21]  (.D(\HWDATA_int[21]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[21]));
    SLE \DATAOUT[27]  (.D(AHB_IF_0_BIF_1_HRDATA[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[27]));
    SLE \HADDR[5]  (.D(\HADDR_6[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[5]));
    SLE \HADDR[25]  (.D(\HADDR_6[25]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[25]));
    SLE \HWDATA_int[31]  (.D(eSRAM_eNVM_RW_0_DATAOUT[31]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[31]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[6]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[6]), 
        .Y(\HADDR_6[6]_net_1 ));
    SLE \DATAOUT[4]  (.D(AHB_IF_0_BIF_1_HRDATA[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[4]));
    SLE \HWDATA[16]  (.D(\HWDATA_int[16]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[16]));
    SLE \HADDR[27]  (.D(\HADDR_6[27]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[27]));
    CFG2 #( .INIT(4'hE) )  un1_ahb_fsm_current_state_8_0_0_o2 (.A(
        \ahb_fsm_current_state[1]_net_1 ), .B(
        \ahb_fsm_current_state[4]_net_1 ), .Y(N_185));
    SLE \DATAOUT[11]  (.D(AHB_IF_0_BIF_1_HRDATA[11]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[11]));
    SLE \DATAOUT[12]  (.D(AHB_IF_0_BIF_1_HRDATA[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[12]));
    SLE \HWDATA_int[3]  (.D(eSRAM_eNVM_RW_0_DATAOUT[3]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[3]_net_1 ));
    SLE \HADDR[21]  (.D(\HADDR_6[21]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[21]));
    SLE \HWDATA_int[20]  (.D(eSRAM_eNVM_RW_0_DATAOUT[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[20]_net_1 ));
    SLE \HWDATA[1]  (.D(\HWDATA_int[1]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[1]));
    SLE HWRITE (.D(\ahb_fsm_current_state[1]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(
        un1_ahb_fsm_current_state_4_0_0_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWRITE));
    CFG2 #( .INIT(4'h8) )  un1_ahb_fsm_current_state_4_0_0_a2 (.A(
        HREADY_M_iv), .B(\ahb_fsm_current_state[2]_net_1 ), .Y(
        HWDATA_1_sqmuxa));
    SLE \HADDR[26]  (.D(\HADDR_6[26]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[26]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[9]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[9]), 
        .Y(\HADDR_6[9]_net_1 ));
    SLE \HWDATA[23]  (.D(\HWDATA_int[23]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[23]));
    SLE \DATAOUT[9]  (.D(AHB_IF_0_BIF_1_HRDATA[9]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[9]));
    SLE \ahb_fsm_current_state[2]  (.D(
        \ahb_fsm_current_state_ns[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[2]_net_1 ));
    SLE \HWDATA_int[24]  (.D(eSRAM_eNVM_RW_0_DATAOUT[24]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[24]_net_1 ));
    SLE \DATAOUT[13]  (.D(AHB_IF_0_BIF_1_HRDATA[13]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[13]));
    SLE \HWDATA_int[15]  (.D(eSRAM_eNVM_RW_0_DATAOUT[15]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[15]_net_1 ));
    SLE \HADDR[2]  (.D(\HADDR_6[2]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[2]));
    SLE \DATAOUT[20]  (.D(AHB_IF_0_BIF_1_HRDATA[20]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[20]));
    CFG4 #( .INIT(16'h0001) )  un1_HADDR_0_sqmuxa_i_0_a2_1 (.A(
        eSRAM_eNVM_RW_0_WRITE), .B(eSRAM_eNVM_RW_0_READ), .C(
        \ahb_fsm_current_state[2]_net_1 ), .D(
        \ahb_fsm_current_state[5]_net_1 ), .Y(N_40));
    SLE \HWDATA_int[17]  (.D(eSRAM_eNVM_RW_0_DATAOUT[17]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[17]_net_1 ));
    SLE \HADDR[4]  (.D(\HADDR_6[4]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[4]));
    SLE \DATAOUT[18]  (.D(AHB_IF_0_BIF_1_HRDATA[18]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[18]));
    SLE \HWDATA[12]  (.D(\HWDATA_int[12]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[12]));
    SLE \HWDATA[26]  (.D(\HWDATA_int[26]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[26]));
    SLE \HWDATA_int[30]  (.D(eSRAM_eNVM_RW_0_DATAOUT[30]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[30]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[19]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[19])
        , .Y(\HADDR_6[19]_net_1 ));
    SLE \HWDATA_int[4]  (.D(eSRAM_eNVM_RW_0_DATAOUT[4]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[4]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[26]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[26])
        , .Y(\HADDR_6[26]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[18]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[18])
        , .Y(\HADDR_6[18]_net_1 ));
    SLE \HWDATA_int[12]  (.D(eSRAM_eNVM_RW_0_DATAOUT[12]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[17]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[17])
        , .Y(\HADDR_6[17]_net_1 ));
    SLE \HWDATA[10]  (.D(\HWDATA_int[10]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[10]));
    SLE \HADDR[14]  (.D(\HADDR_6[14]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[14]));
    SLE \HWDATA[19]  (.D(\HWDATA_int[19]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[19]));
    SLE \HADDR[10]  (.D(\HADDR_6[10]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[10]));
    CFG3 #( .INIT(8'h40) )  \ahb_fsm_current_state_ns_a3_0_a2[4]  (.A(
        eSRAM_eNVM_RW_0_WRITE), .B(\ahb_fsm_current_state[0]_net_1 ), 
        .C(eSRAM_eNVM_RW_0_READ), .Y(\ahb_fsm_current_state_ns[4] ));
    SLE \HWDATA_int[19]  (.D(eSRAM_eNVM_RW_0_DATAOUT[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[19]_net_1 ));
    SLE \HWDATA[22]  (.D(\HWDATA_int[22]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[22]));
    SLE \DATAOUT[16]  (.D(AHB_IF_0_BIF_1_HRDATA[16]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[16]));
    SLE \HWDATA[30]  (.D(\HWDATA_int[30]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[30]));
    SLE \HWDATA_int[25]  (.D(eSRAM_eNVM_RW_0_DATAOUT[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[25]_net_1 ));
    SLE \HWDATA[6]  (.D(\HWDATA_int[6]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[6]));
    CFG3 #( .INIT(8'hF8) )  un18_0_0 (.A(HREADY_M_iv), .B(
        \ahb_fsm_current_state[6]_net_1 ), .C(
        \ahb_fsm_current_state[0]_net_1 ), .Y(un18_0_0_net_1));
    SLE \HWDATA_int[27]  (.D(eSRAM_eNVM_RW_0_DATAOUT[27]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[27]_net_1 ));
    SLE \DATAOUT[8]  (.D(AHB_IF_0_BIF_1_HRDATA[8]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[8]));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[23]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[23])
        , .Y(\HADDR_6[23]_net_1 ));
    SLE \DATAOUT[19]  (.D(AHB_IF_0_BIF_1_HRDATA[19]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[19]));
    SLE \HADDR[30]  (.D(\HADDR_6[30]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[30]));
    SLE \HADDR[7]  (.D(\HADDR_6[7]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[7]));
    SLE \HWDATA[20]  (.D(\HWDATA_int[20]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[20]));
    SLE \HWDATA[29]  (.D(\HWDATA_int[29]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[29]));
    CFG4 #( .INIT(16'hEFE0) )  AHB_BUSY_RNO_0 (.A(eSRAM_eNVM_RW_0_READ)
        , .B(eSRAM_eNVM_RW_0_WRITE), .C(
        \ahb_fsm_current_state[0]_net_1 ), .D(N_163), .Y(N_106_i_0));
    SLE VALID (.D(DATAOUT_1_sqmuxa), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(un18_0_0_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_VALID)
        );
    SLE \ahb_fsm_current_state[0]  (.D(\ahb_fsm_current_state_ns[0] ), 
        .CLK(eSRAM_eNVM_access_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[0]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \HADDR_6[7]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(eSRAM_eNVM_RW_0_ADDR[7]), 
        .Y(\HADDR_6[7]_net_1 ));
    SLE \HADDR[24]  (.D(\HADDR_6[24]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[24]));
    SLE \HWDATA[9]  (.D(\HWDATA_int[9]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HWDATA[9]));
    SLE \HWDATA_int[22]  (.D(eSRAM_eNVM_RW_0_DATAOUT[22]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HWDATA_int_0_sqmuxa), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\HWDATA_int[22]_net_1 ));
    SLE \HADDR[20]  (.D(\HADDR_6[20]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(N_101_i_0), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_BIF_1_HADDR[20]));
    SLE \DATAOUT[25]  (.D(AHB_IF_0_BIF_1_HRDATA[25]), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(DATAOUT_1_sqmuxa), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        AHB_IF_0_DATAOUT[25]));
    SLE \ahb_fsm_current_state[6]  (.D(
        \ahb_fsm_current_state[5]_net_1 ), .CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .EN(HREADY_M_iv), .ALn(
        eSRAM_eNVM_access_0_MSS_READY), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[6]_net_1 ));
    
endmodule


module eSRAM_eNVM_access_top(
       RD,
       DEVRST_N,
       start_envm,
       start_esram
    );
output [7:0] RD;
input  DEVRST_N;
input  start_envm;
input  start_esram;

    wire eSRAM_eNVM_access_0_FIC_0_CLK, eSRAM_eNVM_access_0_MSS_READY, 
        eSRAM_eNVM_RW_0_READ, eSRAM_eNVM_RW_0_WRITE, 
        \eSRAM_eNVM_RW_0_ADDR[2] , \eSRAM_eNVM_RW_0_DATAOUT[0] , 
        \eSRAM_eNVM_RW_0_DATAOUT[1] , \eSRAM_eNVM_RW_0_DATAOUT[2] , 
        \eSRAM_eNVM_RW_0_DATAOUT[3] , \eSRAM_eNVM_RW_0_DATAOUT[4] , 
        \eSRAM_eNVM_RW_0_DATAOUT[5] , \eSRAM_eNVM_RW_0_DATAOUT[6] , 
        \eSRAM_eNVM_RW_0_DATAOUT[7] , \eSRAM_eNVM_RW_0_DATAOUT[8] , 
        \eSRAM_eNVM_RW_0_DATAOUT[9] , \eSRAM_eNVM_RW_0_DATAOUT[10] , 
        \eSRAM_eNVM_RW_0_DATAOUT[11] , \eSRAM_eNVM_RW_0_DATAOUT[12] , 
        \eSRAM_eNVM_RW_0_DATAOUT[13] , \eSRAM_eNVM_RW_0_DATAOUT[14] , 
        \eSRAM_eNVM_RW_0_DATAOUT[15] , \eSRAM_eNVM_RW_0_DATAOUT[16] , 
        \eSRAM_eNVM_RW_0_DATAOUT[17] , \eSRAM_eNVM_RW_0_DATAOUT[18] , 
        \eSRAM_eNVM_RW_0_DATAOUT[19] , \eSRAM_eNVM_RW_0_DATAOUT[20] , 
        \eSRAM_eNVM_RW_0_DATAOUT[21] , \eSRAM_eNVM_RW_0_DATAOUT[22] , 
        \eSRAM_eNVM_RW_0_DATAOUT[23] , \eSRAM_eNVM_RW_0_DATAOUT[24] , 
        \eSRAM_eNVM_RW_0_DATAOUT[25] , \eSRAM_eNVM_RW_0_DATAOUT[26] , 
        \eSRAM_eNVM_RW_0_DATAOUT[27] , \eSRAM_eNVM_RW_0_DATAOUT[28] , 
        \eSRAM_eNVM_RW_0_DATAOUT[29] , \eSRAM_eNVM_RW_0_DATAOUT[30] , 
        \eSRAM_eNVM_RW_0_DATAOUT[31] , GND_net_1, VCC_net_1, 
        \AHB_IF_0_DATAOUT[0] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_BIF_1_HADDR[2] , \AHB_IF_0_BIF_1_HADDR[3] , 
        \AHB_IF_0_BIF_1_HADDR[4] , \AHB_IF_0_BIF_1_HADDR[5] , 
        \AHB_IF_0_BIF_1_HADDR[6] , \AHB_IF_0_BIF_1_HADDR[7] , 
        \AHB_IF_0_BIF_1_HADDR[8] , \AHB_IF_0_BIF_1_HADDR[9] , 
        \AHB_IF_0_BIF_1_HADDR[10] , \AHB_IF_0_BIF_1_HADDR[11] , 
        \AHB_IF_0_BIF_1_HADDR[12] , \AHB_IF_0_BIF_1_HADDR[13] , 
        \AHB_IF_0_BIF_1_HADDR[14] , \AHB_IF_0_BIF_1_HADDR[15] , 
        \AHB_IF_0_BIF_1_HADDR[16] , \AHB_IF_0_BIF_1_HADDR[17] , 
        \AHB_IF_0_BIF_1_HADDR[18] , \AHB_IF_0_BIF_1_HADDR[19] , 
        \AHB_IF_0_BIF_1_HADDR[20] , \AHB_IF_0_BIF_1_HADDR[21] , 
        \AHB_IF_0_BIF_1_HADDR[22] , \AHB_IF_0_BIF_1_HADDR[23] , 
        \AHB_IF_0_BIF_1_HADDR[24] , \AHB_IF_0_BIF_1_HADDR[25] , 
        \AHB_IF_0_BIF_1_HADDR[26] , \AHB_IF_0_BIF_1_HADDR[27] , 
        \AHB_IF_0_BIF_1_HADDR[28] , \AHB_IF_0_BIF_1_HADDR[29] , 
        \AHB_IF_0_BIF_1_HADDR[30] , \AHB_IF_0_BIF_1_HADDR[31] , 
        \AHB_IF_0_BIF_1_HTRANS[1] , AHB_IF_0_BIF_1_HWRITE, 
        \AHB_IF_0_BIF_1_HWDATA[0] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HRDATA[0] , \AHB_IF_0_BIF_1_HRDATA[1] , 
        \AHB_IF_0_BIF_1_HRDATA[2] , \AHB_IF_0_BIF_1_HRDATA[3] , 
        \AHB_IF_0_BIF_1_HRDATA[4] , \AHB_IF_0_BIF_1_HRDATA[5] , 
        \AHB_IF_0_BIF_1_HRDATA[6] , \AHB_IF_0_BIF_1_HRDATA[7] , 
        \AHB_IF_0_BIF_1_HRDATA[8] , \AHB_IF_0_BIF_1_HRDATA[9] , 
        \AHB_IF_0_BIF_1_HRDATA[17] , \AHB_IF_0_BIF_1_HRDATA[18] , 
        \AHB_IF_0_BIF_1_HRDATA[19] , \AHB_IF_0_BIF_1_HRDATA[20] , 
        \AHB_IF_0_BIF_1_HRDATA[21] , \AHB_IF_0_BIF_1_HRDATA[22] , 
        \AHB_IF_0_BIF_1_HRDATA[23] , \AHB_IF_0_BIF_1_HRDATA[24] , 
        \AHB_IF_0_BIF_1_HRDATA[25] , \AHB_IF_0_BIF_1_HRDATA[26] , 
        \AHB_IF_0_BIF_1_HRDATA[27] , \AHB_IF_0_BIF_1_HRDATA[28] , 
        \AHB_IF_0_BIF_1_HRDATA[29] , \AHB_IF_0_BIF_1_HRDATA[30] , 
        \AHB_IF_0_BIF_1_HRDATA[31] , AHB_IF_0_AHB_BUSY, AHB_IF_0_VALID, 
        eSRAM_eNVM_RW_0_ram_wen, \eSRAM_eNVM_RW_0_ram_waddr[0] , 
        \eSRAM_eNVM_RW_0_ram_waddr[1] , \eSRAM_eNVM_RW_0_ram_waddr[2] , 
        \eSRAM_eNVM_RW_0_ram_waddr[3] , \eSRAM_eNVM_RW_0_ram_waddr[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[0] , \eSRAM_eNVM_RW_0_ram_wdata[1] , 
        \eSRAM_eNVM_RW_0_ram_wdata[2] , \eSRAM_eNVM_RW_0_ram_wdata[3] , 
        \eSRAM_eNVM_RW_0_ram_wdata[4] , \eSRAM_eNVM_RW_0_ram_wdata[5] , 
        \eSRAM_eNVM_RW_0_ram_wdata[6] , \eSRAM_eNVM_RW_0_ram_wdata[7] , 
        \eSRAM_eNVM_RW_0_ram_wdata[8] , \eSRAM_eNVM_RW_0_ram_wdata[9] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv , 
        start_envm_c, start_esram_c, \RD_c[0] , \RD_c[1] , \RD_c[2] , 
        \RD_c[3] , \RD_c[4] , \RD_c[5] , \RD_c[6] , \RD_c[7] , 
        \AHB_IF_0_BIF_1_HRDATA[16] , \AHB_IF_0_BIF_1_HRDATA[15] , 
        \AHB_IF_0_BIF_1_HRDATA[14] , \AHB_IF_0_BIF_1_HRDATA[13] , 
        \AHB_IF_0_BIF_1_HRDATA[12] , \AHB_IF_0_BIF_1_HRDATA[11] , 
        \AHB_IF_0_BIF_1_HRDATA[10] , \eSRAM_eNVM_RW_0_ADDR[3] , 
        \eSRAM_eNVM_RW_0_ADDR[4] , \eSRAM_eNVM_RW_0_ADDR[5] , 
        \eSRAM_eNVM_RW_0_ADDR[6] , \eSRAM_eNVM_RW_0_ADDR[7] , 
        \eSRAM_eNVM_RW_0_ADDR[8] , \eSRAM_eNVM_RW_0_ADDR[9] , 
        \eSRAM_eNVM_RW_0_ADDR[10] , \eSRAM_eNVM_RW_0_ADDR[11] , 
        \eSRAM_eNVM_RW_0_ADDR[12] , \eSRAM_eNVM_RW_0_ADDR[13] , 
        \eSRAM_eNVM_RW_0_ADDR[14] , \eSRAM_eNVM_RW_0_ADDR[15] , 
        \eSRAM_eNVM_RW_0_ADDR[16] , \eSRAM_eNVM_RW_0_ADDR[17] , 
        \eSRAM_eNVM_RW_0_ADDR[18] , \eSRAM_eNVM_RW_0_ADDR[19] , 
        \eSRAM_eNVM_RW_0_ADDR[20] , \eSRAM_eNVM_RW_0_ADDR[21] , 
        \eSRAM_eNVM_RW_0_ADDR[22] , \eSRAM_eNVM_RW_0_ADDR[23] , 
        \eSRAM_eNVM_RW_0_ADDR[24] , \eSRAM_eNVM_RW_0_ADDR[25] , 
        \eSRAM_eNVM_RW_0_ADDR[26] , \eSRAM_eNVM_RW_0_ADDR[27] , 
        \eSRAM_eNVM_RW_0_ADDR[28] , \eSRAM_eNVM_RW_0_ADDR[29] , 
        \eSRAM_eNVM_RW_0_ADDR[30] , \eSRAM_eNVM_RW_0_ADDR[31] ;
    
    eSRAM_eNVM_access_top_TPSRAM_0_TPSRAM TPSRAM_0 (.RD_c({\RD_c[7] , 
        \RD_c[6] , \RD_c[5] , \RD_c[4] , \RD_c[3] , \RD_c[2] , 
        \RD_c[1] , \RD_c[0] }), .eSRAM_eNVM_RW_0_ram_wdata({
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[9] , \eSRAM_eNVM_RW_0_ram_wdata[8] , 
        \eSRAM_eNVM_RW_0_ram_wdata[7] , \eSRAM_eNVM_RW_0_ram_wdata[6] , 
        \eSRAM_eNVM_RW_0_ram_wdata[5] , \eSRAM_eNVM_RW_0_ram_wdata[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[3] , \eSRAM_eNVM_RW_0_ram_wdata[2] , 
        \eSRAM_eNVM_RW_0_ram_wdata[1] , \eSRAM_eNVM_RW_0_ram_wdata[0] })
        , .eSRAM_eNVM_RW_0_ram_waddr({\eSRAM_eNVM_RW_0_ram_waddr[4] , 
        \eSRAM_eNVM_RW_0_ram_waddr[3] , \eSRAM_eNVM_RW_0_ram_waddr[2] , 
        \eSRAM_eNVM_RW_0_ram_waddr[1] , \eSRAM_eNVM_RW_0_ram_waddr[0] })
        , .eSRAM_eNVM_access_0_FIC_0_CLK(eSRAM_eNVM_access_0_FIC_0_CLK)
        , .eSRAM_eNVM_RW_0_ram_wen(eSRAM_eNVM_RW_0_ram_wen));
    INBUF start_esram_ibuf (.PAD(start_esram), .Y(start_esram_c));
    OUTBUF \RD_obuf[2]  (.D(\RD_c[2] ), .PAD(RD[2]));
    eSRAM_eNVM_access eSRAM_eNVM_access_0 (.AHB_IF_0_BIF_1_HTRANS({
        \AHB_IF_0_BIF_1_HTRANS[1] }), .AHB_IF_0_BIF_1_HADDR({
        \AHB_IF_0_BIF_1_HADDR[31] , \AHB_IF_0_BIF_1_HADDR[30] , 
        \AHB_IF_0_BIF_1_HADDR[29] , \AHB_IF_0_BIF_1_HADDR[28] , 
        \AHB_IF_0_BIF_1_HADDR[27] , \AHB_IF_0_BIF_1_HADDR[26] , 
        \AHB_IF_0_BIF_1_HADDR[25] , \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[23] , \AHB_IF_0_BIF_1_HADDR[22] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[12] , 
        \AHB_IF_0_BIF_1_HADDR[11] , \AHB_IF_0_BIF_1_HADDR[10] , 
        \AHB_IF_0_BIF_1_HADDR[9] , \AHB_IF_0_BIF_1_HADDR[8] , 
        \AHB_IF_0_BIF_1_HADDR[7] , \AHB_IF_0_BIF_1_HADDR[6] , 
        \AHB_IF_0_BIF_1_HADDR[5] , \AHB_IF_0_BIF_1_HADDR[4] , 
        \AHB_IF_0_BIF_1_HADDR[3] , \AHB_IF_0_BIF_1_HADDR[2] }), 
        .AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .AHB_IF_0_BIF_1_HRDATA({
        \AHB_IF_0_BIF_1_HRDATA[31] , \AHB_IF_0_BIF_1_HRDATA[30] , 
        \AHB_IF_0_BIF_1_HRDATA[29] , \AHB_IF_0_BIF_1_HRDATA[28] , 
        \AHB_IF_0_BIF_1_HRDATA[27] , \AHB_IF_0_BIF_1_HRDATA[26] , 
        \AHB_IF_0_BIF_1_HRDATA[25] , \AHB_IF_0_BIF_1_HRDATA[24] , 
        \AHB_IF_0_BIF_1_HRDATA[23] , \AHB_IF_0_BIF_1_HRDATA[22] , 
        \AHB_IF_0_BIF_1_HRDATA[21] , \AHB_IF_0_BIF_1_HRDATA[20] , 
        \AHB_IF_0_BIF_1_HRDATA[19] , \AHB_IF_0_BIF_1_HRDATA[18] , 
        \AHB_IF_0_BIF_1_HRDATA[17] , \AHB_IF_0_BIF_1_HRDATA[16] , 
        \AHB_IF_0_BIF_1_HRDATA[15] , \AHB_IF_0_BIF_1_HRDATA[14] , 
        \AHB_IF_0_BIF_1_HRDATA[13] , \AHB_IF_0_BIF_1_HRDATA[12] , 
        \AHB_IF_0_BIF_1_HRDATA[11] , \AHB_IF_0_BIF_1_HRDATA[10] , 
        \AHB_IF_0_BIF_1_HRDATA[9] , \AHB_IF_0_BIF_1_HRDATA[8] , 
        \AHB_IF_0_BIF_1_HRDATA[7] , \AHB_IF_0_BIF_1_HRDATA[6] , 
        \AHB_IF_0_BIF_1_HRDATA[5] , \AHB_IF_0_BIF_1_HRDATA[4] , 
        \AHB_IF_0_BIF_1_HRDATA[3] , \AHB_IF_0_BIF_1_HRDATA[2] , 
        \AHB_IF_0_BIF_1_HRDATA[1] , \AHB_IF_0_BIF_1_HRDATA[0] }), 
        .DEVRST_N(DEVRST_N), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .HREADY_M_iv(
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv )
        );
    INBUF start_envm_ibuf (.PAD(start_envm), .Y(start_envm_c));
    OUTBUF \RD_obuf[7]  (.D(\RD_c[7] ), .PAD(RD[7]));
    GND GND (.Y(GND_net_1));
    OUTBUF \RD_obuf[6]  (.D(\RD_c[6] ), .PAD(RD[6]));
    OUTBUF \RD_obuf[0]  (.D(\RD_c[0] ), .PAD(RD[0]));
    eSRAM_eNVM_RW_Z7 eSRAM_eNVM_RW_0 (.eSRAM_eNVM_RW_0_ram_waddr({
        \eSRAM_eNVM_RW_0_ram_waddr[4] , \eSRAM_eNVM_RW_0_ram_waddr[3] , 
        \eSRAM_eNVM_RW_0_ram_waddr[2] , \eSRAM_eNVM_RW_0_ram_waddr[1] , 
        \eSRAM_eNVM_RW_0_ram_waddr[0] }), .eSRAM_eNVM_RW_0_ram_wdata({
        \eSRAM_eNVM_RW_0_ram_wdata[31] , 
        \eSRAM_eNVM_RW_0_ram_wdata[30] , 
        \eSRAM_eNVM_RW_0_ram_wdata[29] , 
        \eSRAM_eNVM_RW_0_ram_wdata[28] , 
        \eSRAM_eNVM_RW_0_ram_wdata[27] , 
        \eSRAM_eNVM_RW_0_ram_wdata[26] , 
        \eSRAM_eNVM_RW_0_ram_wdata[25] , 
        \eSRAM_eNVM_RW_0_ram_wdata[24] , 
        \eSRAM_eNVM_RW_0_ram_wdata[23] , 
        \eSRAM_eNVM_RW_0_ram_wdata[22] , 
        \eSRAM_eNVM_RW_0_ram_wdata[21] , 
        \eSRAM_eNVM_RW_0_ram_wdata[20] , 
        \eSRAM_eNVM_RW_0_ram_wdata[19] , 
        \eSRAM_eNVM_RW_0_ram_wdata[18] , 
        \eSRAM_eNVM_RW_0_ram_wdata[17] , 
        \eSRAM_eNVM_RW_0_ram_wdata[16] , 
        \eSRAM_eNVM_RW_0_ram_wdata[15] , 
        \eSRAM_eNVM_RW_0_ram_wdata[14] , 
        \eSRAM_eNVM_RW_0_ram_wdata[13] , 
        \eSRAM_eNVM_RW_0_ram_wdata[12] , 
        \eSRAM_eNVM_RW_0_ram_wdata[11] , 
        \eSRAM_eNVM_RW_0_ram_wdata[10] , 
        \eSRAM_eNVM_RW_0_ram_wdata[9] , \eSRAM_eNVM_RW_0_ram_wdata[8] , 
        \eSRAM_eNVM_RW_0_ram_wdata[7] , \eSRAM_eNVM_RW_0_ram_wdata[6] , 
        \eSRAM_eNVM_RW_0_ram_wdata[5] , \eSRAM_eNVM_RW_0_ram_wdata[4] , 
        \eSRAM_eNVM_RW_0_ram_wdata[3] , \eSRAM_eNVM_RW_0_ram_wdata[2] , 
        \eSRAM_eNVM_RW_0_ram_wdata[1] , \eSRAM_eNVM_RW_0_ram_wdata[0] })
        , .AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[0] }), .eSRAM_eNVM_RW_0_ADDR({
        \eSRAM_eNVM_RW_0_ADDR[31] , \eSRAM_eNVM_RW_0_ADDR[30] , 
        \eSRAM_eNVM_RW_0_ADDR[29] , \eSRAM_eNVM_RW_0_ADDR[28] , 
        \eSRAM_eNVM_RW_0_ADDR[27] , \eSRAM_eNVM_RW_0_ADDR[26] , 
        \eSRAM_eNVM_RW_0_ADDR[25] , \eSRAM_eNVM_RW_0_ADDR[24] , 
        \eSRAM_eNVM_RW_0_ADDR[23] , \eSRAM_eNVM_RW_0_ADDR[22] , 
        \eSRAM_eNVM_RW_0_ADDR[21] , \eSRAM_eNVM_RW_0_ADDR[20] , 
        \eSRAM_eNVM_RW_0_ADDR[19] , \eSRAM_eNVM_RW_0_ADDR[18] , 
        \eSRAM_eNVM_RW_0_ADDR[17] , \eSRAM_eNVM_RW_0_ADDR[16] , 
        \eSRAM_eNVM_RW_0_ADDR[15] , \eSRAM_eNVM_RW_0_ADDR[14] , 
        \eSRAM_eNVM_RW_0_ADDR[13] , \eSRAM_eNVM_RW_0_ADDR[12] , 
        \eSRAM_eNVM_RW_0_ADDR[11] , \eSRAM_eNVM_RW_0_ADDR[10] , 
        \eSRAM_eNVM_RW_0_ADDR[9] , \eSRAM_eNVM_RW_0_ADDR[8] , 
        \eSRAM_eNVM_RW_0_ADDR[7] , \eSRAM_eNVM_RW_0_ADDR[6] , 
        \eSRAM_eNVM_RW_0_ADDR[5] , \eSRAM_eNVM_RW_0_ADDR[4] , 
        \eSRAM_eNVM_RW_0_ADDR[3] , \eSRAM_eNVM_RW_0_ADDR[2] }), 
        .eSRAM_eNVM_RW_0_DATAOUT({\eSRAM_eNVM_RW_0_DATAOUT[31] , 
        \eSRAM_eNVM_RW_0_DATAOUT[30] , \eSRAM_eNVM_RW_0_DATAOUT[29] , 
        \eSRAM_eNVM_RW_0_DATAOUT[28] , \eSRAM_eNVM_RW_0_DATAOUT[27] , 
        \eSRAM_eNVM_RW_0_DATAOUT[26] , \eSRAM_eNVM_RW_0_DATAOUT[25] , 
        \eSRAM_eNVM_RW_0_DATAOUT[24] , \eSRAM_eNVM_RW_0_DATAOUT[23] , 
        \eSRAM_eNVM_RW_0_DATAOUT[22] , \eSRAM_eNVM_RW_0_DATAOUT[21] , 
        \eSRAM_eNVM_RW_0_DATAOUT[20] , \eSRAM_eNVM_RW_0_DATAOUT[19] , 
        \eSRAM_eNVM_RW_0_DATAOUT[18] , \eSRAM_eNVM_RW_0_DATAOUT[17] , 
        \eSRAM_eNVM_RW_0_DATAOUT[16] , \eSRAM_eNVM_RW_0_DATAOUT[15] , 
        \eSRAM_eNVM_RW_0_DATAOUT[14] , \eSRAM_eNVM_RW_0_DATAOUT[13] , 
        \eSRAM_eNVM_RW_0_DATAOUT[12] , \eSRAM_eNVM_RW_0_DATAOUT[11] , 
        \eSRAM_eNVM_RW_0_DATAOUT[10] , \eSRAM_eNVM_RW_0_DATAOUT[9] , 
        \eSRAM_eNVM_RW_0_DATAOUT[8] , \eSRAM_eNVM_RW_0_DATAOUT[7] , 
        \eSRAM_eNVM_RW_0_DATAOUT[6] , \eSRAM_eNVM_RW_0_DATAOUT[5] , 
        \eSRAM_eNVM_RW_0_DATAOUT[4] , \eSRAM_eNVM_RW_0_DATAOUT[3] , 
        \eSRAM_eNVM_RW_0_DATAOUT[2] , \eSRAM_eNVM_RW_0_DATAOUT[1] , 
        \eSRAM_eNVM_RW_0_DATAOUT[0] }), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .eSRAM_eNVM_RW_0_WRITE(
        eSRAM_eNVM_RW_0_WRITE), .eSRAM_eNVM_RW_0_READ(
        eSRAM_eNVM_RW_0_READ), .eSRAM_eNVM_RW_0_ram_wen(
        eSRAM_eNVM_RW_0_ram_wen), .start_envm_c(start_envm_c), 
        .start_esram_c(start_esram_c), .AHB_IF_0_AHB_BUSY(
        AHB_IF_0_AHB_BUSY), .AHB_IF_0_VALID(AHB_IF_0_VALID));
    VCC VCC (.Y(VCC_net_1));
    OUTBUF \RD_obuf[5]  (.D(\RD_c[5] ), .PAD(RD[5]));
    AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1 
        AHB_IF_0 (.eSRAM_eNVM_RW_0_DATAOUT({
        \eSRAM_eNVM_RW_0_DATAOUT[31] , \eSRAM_eNVM_RW_0_DATAOUT[30] , 
        \eSRAM_eNVM_RW_0_DATAOUT[29] , \eSRAM_eNVM_RW_0_DATAOUT[28] , 
        \eSRAM_eNVM_RW_0_DATAOUT[27] , \eSRAM_eNVM_RW_0_DATAOUT[26] , 
        \eSRAM_eNVM_RW_0_DATAOUT[25] , \eSRAM_eNVM_RW_0_DATAOUT[24] , 
        \eSRAM_eNVM_RW_0_DATAOUT[23] , \eSRAM_eNVM_RW_0_DATAOUT[22] , 
        \eSRAM_eNVM_RW_0_DATAOUT[21] , \eSRAM_eNVM_RW_0_DATAOUT[20] , 
        \eSRAM_eNVM_RW_0_DATAOUT[19] , \eSRAM_eNVM_RW_0_DATAOUT[18] , 
        \eSRAM_eNVM_RW_0_DATAOUT[17] , \eSRAM_eNVM_RW_0_DATAOUT[16] , 
        \eSRAM_eNVM_RW_0_DATAOUT[15] , \eSRAM_eNVM_RW_0_DATAOUT[14] , 
        \eSRAM_eNVM_RW_0_DATAOUT[13] , \eSRAM_eNVM_RW_0_DATAOUT[12] , 
        \eSRAM_eNVM_RW_0_DATAOUT[11] , \eSRAM_eNVM_RW_0_DATAOUT[10] , 
        \eSRAM_eNVM_RW_0_DATAOUT[9] , \eSRAM_eNVM_RW_0_DATAOUT[8] , 
        \eSRAM_eNVM_RW_0_DATAOUT[7] , \eSRAM_eNVM_RW_0_DATAOUT[6] , 
        \eSRAM_eNVM_RW_0_DATAOUT[5] , \eSRAM_eNVM_RW_0_DATAOUT[4] , 
        \eSRAM_eNVM_RW_0_DATAOUT[3] , \eSRAM_eNVM_RW_0_DATAOUT[2] , 
        \eSRAM_eNVM_RW_0_DATAOUT[1] , \eSRAM_eNVM_RW_0_DATAOUT[0] }), 
        .AHB_IF_0_DATAOUT({\AHB_IF_0_DATAOUT[31] , 
        \AHB_IF_0_DATAOUT[30] , \AHB_IF_0_DATAOUT[29] , 
        \AHB_IF_0_DATAOUT[28] , \AHB_IF_0_DATAOUT[27] , 
        \AHB_IF_0_DATAOUT[26] , \AHB_IF_0_DATAOUT[25] , 
        \AHB_IF_0_DATAOUT[24] , \AHB_IF_0_DATAOUT[23] , 
        \AHB_IF_0_DATAOUT[22] , \AHB_IF_0_DATAOUT[21] , 
        \AHB_IF_0_DATAOUT[20] , \AHB_IF_0_DATAOUT[19] , 
        \AHB_IF_0_DATAOUT[18] , \AHB_IF_0_DATAOUT[17] , 
        \AHB_IF_0_DATAOUT[16] , \AHB_IF_0_DATAOUT[15] , 
        \AHB_IF_0_DATAOUT[14] , \AHB_IF_0_DATAOUT[13] , 
        \AHB_IF_0_DATAOUT[12] , \AHB_IF_0_DATAOUT[11] , 
        \AHB_IF_0_DATAOUT[10] , \AHB_IF_0_DATAOUT[9] , 
        \AHB_IF_0_DATAOUT[8] , \AHB_IF_0_DATAOUT[7] , 
        \AHB_IF_0_DATAOUT[6] , \AHB_IF_0_DATAOUT[5] , 
        \AHB_IF_0_DATAOUT[4] , \AHB_IF_0_DATAOUT[3] , 
        \AHB_IF_0_DATAOUT[2] , \AHB_IF_0_DATAOUT[1] , 
        \AHB_IF_0_DATAOUT[0] }), .AHB_IF_0_BIF_1_HRDATA({
        \AHB_IF_0_BIF_1_HRDATA[31] , \AHB_IF_0_BIF_1_HRDATA[30] , 
        \AHB_IF_0_BIF_1_HRDATA[29] , \AHB_IF_0_BIF_1_HRDATA[28] , 
        \AHB_IF_0_BIF_1_HRDATA[27] , \AHB_IF_0_BIF_1_HRDATA[26] , 
        \AHB_IF_0_BIF_1_HRDATA[25] , \AHB_IF_0_BIF_1_HRDATA[24] , 
        \AHB_IF_0_BIF_1_HRDATA[23] , \AHB_IF_0_BIF_1_HRDATA[22] , 
        \AHB_IF_0_BIF_1_HRDATA[21] , \AHB_IF_0_BIF_1_HRDATA[20] , 
        \AHB_IF_0_BIF_1_HRDATA[19] , \AHB_IF_0_BIF_1_HRDATA[18] , 
        \AHB_IF_0_BIF_1_HRDATA[17] , \AHB_IF_0_BIF_1_HRDATA[16] , 
        \AHB_IF_0_BIF_1_HRDATA[15] , \AHB_IF_0_BIF_1_HRDATA[14] , 
        \AHB_IF_0_BIF_1_HRDATA[13] , \AHB_IF_0_BIF_1_HRDATA[12] , 
        \AHB_IF_0_BIF_1_HRDATA[11] , \AHB_IF_0_BIF_1_HRDATA[10] , 
        \AHB_IF_0_BIF_1_HRDATA[9] , \AHB_IF_0_BIF_1_HRDATA[8] , 
        \AHB_IF_0_BIF_1_HRDATA[7] , \AHB_IF_0_BIF_1_HRDATA[6] , 
        \AHB_IF_0_BIF_1_HRDATA[5] , \AHB_IF_0_BIF_1_HRDATA[4] , 
        \AHB_IF_0_BIF_1_HRDATA[3] , \AHB_IF_0_BIF_1_HRDATA[2] , 
        \AHB_IF_0_BIF_1_HRDATA[1] , \AHB_IF_0_BIF_1_HRDATA[0] }), 
        .AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[31] , 
        \AHB_IF_0_BIF_1_HWDATA[30] , \AHB_IF_0_BIF_1_HWDATA[29] , 
        \AHB_IF_0_BIF_1_HWDATA[28] , \AHB_IF_0_BIF_1_HWDATA[27] , 
        \AHB_IF_0_BIF_1_HWDATA[26] , \AHB_IF_0_BIF_1_HWDATA[25] , 
        \AHB_IF_0_BIF_1_HWDATA[24] , \AHB_IF_0_BIF_1_HWDATA[23] , 
        \AHB_IF_0_BIF_1_HWDATA[22] , \AHB_IF_0_BIF_1_HWDATA[21] , 
        \AHB_IF_0_BIF_1_HWDATA[20] , \AHB_IF_0_BIF_1_HWDATA[19] , 
        \AHB_IF_0_BIF_1_HWDATA[18] , \AHB_IF_0_BIF_1_HWDATA[17] , 
        \AHB_IF_0_BIF_1_HWDATA[16] , \AHB_IF_0_BIF_1_HWDATA[15] , 
        \AHB_IF_0_BIF_1_HWDATA[14] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .AHB_IF_0_BIF_1_HADDR({
        \AHB_IF_0_BIF_1_HADDR[31] , \AHB_IF_0_BIF_1_HADDR[30] , 
        \AHB_IF_0_BIF_1_HADDR[29] , \AHB_IF_0_BIF_1_HADDR[28] , 
        \AHB_IF_0_BIF_1_HADDR[27] , \AHB_IF_0_BIF_1_HADDR[26] , 
        \AHB_IF_0_BIF_1_HADDR[25] , \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[23] , \AHB_IF_0_BIF_1_HADDR[22] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[12] , 
        \AHB_IF_0_BIF_1_HADDR[11] , \AHB_IF_0_BIF_1_HADDR[10] , 
        \AHB_IF_0_BIF_1_HADDR[9] , \AHB_IF_0_BIF_1_HADDR[8] , 
        \AHB_IF_0_BIF_1_HADDR[7] , \AHB_IF_0_BIF_1_HADDR[6] , 
        \AHB_IF_0_BIF_1_HADDR[5] , \AHB_IF_0_BIF_1_HADDR[4] , 
        \AHB_IF_0_BIF_1_HADDR[3] , \AHB_IF_0_BIF_1_HADDR[2] }), 
        .AHB_IF_0_BIF_1_HTRANS({\AHB_IF_0_BIF_1_HTRANS[1] }), 
        .eSRAM_eNVM_RW_0_ADDR({\eSRAM_eNVM_RW_0_ADDR[31] , 
        \eSRAM_eNVM_RW_0_ADDR[30] , \eSRAM_eNVM_RW_0_ADDR[29] , 
        \eSRAM_eNVM_RW_0_ADDR[28] , \eSRAM_eNVM_RW_0_ADDR[27] , 
        \eSRAM_eNVM_RW_0_ADDR[26] , \eSRAM_eNVM_RW_0_ADDR[25] , 
        \eSRAM_eNVM_RW_0_ADDR[24] , \eSRAM_eNVM_RW_0_ADDR[23] , 
        \eSRAM_eNVM_RW_0_ADDR[22] , \eSRAM_eNVM_RW_0_ADDR[21] , 
        \eSRAM_eNVM_RW_0_ADDR[20] , \eSRAM_eNVM_RW_0_ADDR[19] , 
        \eSRAM_eNVM_RW_0_ADDR[18] , \eSRAM_eNVM_RW_0_ADDR[17] , 
        \eSRAM_eNVM_RW_0_ADDR[16] , \eSRAM_eNVM_RW_0_ADDR[15] , 
        \eSRAM_eNVM_RW_0_ADDR[14] , \eSRAM_eNVM_RW_0_ADDR[13] , 
        \eSRAM_eNVM_RW_0_ADDR[12] , \eSRAM_eNVM_RW_0_ADDR[11] , 
        \eSRAM_eNVM_RW_0_ADDR[10] , \eSRAM_eNVM_RW_0_ADDR[9] , 
        \eSRAM_eNVM_RW_0_ADDR[8] , \eSRAM_eNVM_RW_0_ADDR[7] , 
        \eSRAM_eNVM_RW_0_ADDR[6] , \eSRAM_eNVM_RW_0_ADDR[5] , 
        \eSRAM_eNVM_RW_0_ADDR[4] , \eSRAM_eNVM_RW_0_ADDR[3] , 
        \eSRAM_eNVM_RW_0_ADDR[2] }), .eSRAM_eNVM_access_0_FIC_0_CLK(
        eSRAM_eNVM_access_0_FIC_0_CLK), .eSRAM_eNVM_access_0_MSS_READY(
        eSRAM_eNVM_access_0_MSS_READY), .AHB_IF_0_VALID(AHB_IF_0_VALID)
        , .AHB_IF_0_AHB_BUSY(AHB_IF_0_AHB_BUSY), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), .HREADY_M_iv(
        \eSRAM_eNVM_access_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv )
        , .eSRAM_eNVM_RW_0_WRITE(eSRAM_eNVM_RW_0_WRITE), 
        .eSRAM_eNVM_RW_0_READ(eSRAM_eNVM_RW_0_READ));
    OUTBUF \RD_obuf[4]  (.D(\RD_c[4] ), .PAD(RD[4]));
    OUTBUF \RD_obuf[3]  (.D(\RD_c[3] ), .PAD(RD[3]));
    OUTBUF \RD_obuf[1]  (.D(\RD_c[1] ), .PAD(RD[1]));
    
endmodule
