| Project Settings |
|---|
| Project Name | MDDR_TA_top_syn | Implementation Name | synthesis |
| Top Module | MDDR_TA_top | Retiming | 0 |
| Resource Sharing | 0 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
88 |
2158 |
0 |
- |
0m:04s |
- |
2/17/2016
2:55:39 PM |
| (premap) | Complete |
50 |
14 |
0 |
0m:01s |
0m:01s |
168MB |
2/17/2016
2:55:44 PM |
| (fpga_mapper) | Complete |
224 |
3535 |
0 |
0m:10s |
0m:10s |
205MB |
2/17/2016
2:55:55 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/17/2016
2:55:42 PM |
| Area Summary |
|---|
| |
| Carry Cells | 326 |
Sequential Cells | 1060 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 51 |
| Global Clock Buffers | 9 |
Block Rams (RAM1K18)
(v_ram) | 3 |
| LUTs
(total_luts) | 1702 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock | 83.0 MHz | 117.2 MHz | 3.515 |
| MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock | 83.0 MHz | 181.7 MHz | 4.934 |
| MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 83.0 MHz | 428.6 MHz | 9.715 |
| MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 83.0 MHz | 143.5 MHz | 2.836 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 3 / 1 |
| |
|