@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":254:0:254:5|Removing sequential instance AXI_IF_0.AWBURST_1[0],  because it is equivalent to instance AXI_IF_0.AWSIZE_1[0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":523:0:523:5|Removing sequential instance AXI_IF_0.ARBURST_1[0],  because it is equivalent to instance AXI_IF_0.ARSIZE_1[0]
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3567:27:3567:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3522:27:3522:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3477:27:3477:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3432:27:3432:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3387:27:3387:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3297:26:3297:37|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3252:27:3252:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3207:27:3207:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3162:27:3162:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3117:27:3117:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_5,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3072:27:3072:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_4,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3027:27:3027:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_3,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2982:27:2982:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_2,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":3342:27:3342:39|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_1
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreahblite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v":2937:27:2937:38|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_1,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_0
@W: BN132 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1031:4:1031:9|Removing sequential instance MDDR_TA_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance MDDR_TA_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigp\5.0.101\rtl\vlog\core\coreconfigp.v":433:4:433:9|Found inferred clock MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreconfigmaster\2.0.101\rtl\vlog\core\coreconfigmaster.v":541:4:541:9|Found inferred clock MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock which controls 473 sequential elements including MDDR_TA_0.ConfigMaster_0.state[20:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\component\actel\directcore\coreresetp\5.1.100\rtl\vlog\core\coreresetp.v":1562:4:1562:9|Found inferred clock MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including MDDR_TA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\learning\ddr\design\igl2\v0.4\mddr_ta\hdl\axi_if.v":523:0:523:5|Found inferred clock MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock which controls 834 sequential elements including AXI_IF_0.ARADDR_1[31:7]. This clock has no specified timing constraint which may adversely impact design performance. 
