m255
K4
z2
13
cModel Technology
Z0 dD:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/simulation
!s112 0.1
!i10d 8192
!i10e 25
!i10f 100
vAHB_IF
Z1 !s110 1455700334
!i10b 1
!s100 nk;[95F]aRB>_1GNcHE`@2
I7<=k1GUZ<O1R?aPmDP5260
Z2 VDg1SIo80bB@j0V0VzS_@n1
Z3 dF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/simulation
w1398159388
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AHB_IF.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AHB_IF.v
L0 19
Z4 OW;L;10.4c;61
r1
!s85 0
31
Z5 !s108 1455700334.000000
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AHB_IF.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AHB_IF.v|
!s101 -O0
!i113 1
Z6 o-work presynth -O0
n@a@h@b_@i@f
vaxi_feedthrough
Z7 !s110 1455700335
!i10b 1
!s100 62J]OoTWWd;NC[G7f0^Ob0
IPB`g5ER5=EF=`N6m1?mR:2
R2
R3
Z8 w1455697817
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v
Z9 L0 30
R4
r1
!s85 0
31
Z10 !s108 1455700335.000000
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v|
!s101 -O0
!i113 1
R6
vAXI_IF
R1
!i10b 1
!s100 BGcWgAdJJ^4c6b3S>]gXW1
I<>;nl>LTA^3B9SibQglGi1
R2
R3
w1446027058
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AXI_IF.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AXI_IF.v
Z11 L0 29
R4
r1
!s85 0
31
R5
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AXI_IF.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/AXI_IF.v|
!s101 -O0
!i113 1
R6
n@a@x@i_@i@f
vaxi_interconnect
Z12 !s110 1401871511
I@]FOfjUZ0;i83?m=`^Df_0
Z13 V`JN@9S9cnhjKRR_L]QIcM3
Z14 dD:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/simulation
Z15 w1395649386
8D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/axi_interconnect.v
FD:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/axi_interconnect.v
R11
Z16 OW;L;10.2c;57
r1
31
R6
!i10b 1
!s100 _[c4;M1]U?5EmNdHQ9Og@2
!s85 0
!s108 1401871511.202000
!s107 D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/axi_interconnect.v|
!s90 -reportprogress|300|-work|presynth|D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/axi_interconnect.v|
!s101 -O0
vaxi_interconnect_ntom
Z17 !s110 1455700336
!i10b 1
!s100 <WNS1dS]dBHeHJ:N4@lPH2
IQj>4ZCcz9^HmXl@>bbi5?3
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v
L0 38
R4
r1
!s85 0
31
Z18 !s108 1455700336.000000
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v|
!s101 -O0
!i113 1
R6
vaxi_master_stage
Z19 !s110 1455700337
!i10b 1
!s100 ^07T5bC:4G5F`_Z]K1]j?0
IBP5NPMBcHjb?Xa84[_D1j2
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v
Z20 L0 28
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v|
!s101 -O0
!i113 1
R6
vaxi_matrix_m
R7
!i10b 1
!s100 8<Z9dkWHB]QC^_Z<cC8aW2
I0;RIORbkKZM8K^e<3;Lk@2
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v
Z21 L0 33
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v|
!s101 -O0
!i113 1
R6
vaxi_matrix_s
R17
!i10b 1
!s100 J0RA5gMl35_ZmTRgH[U^e2
II<10NT3Rm26=`[6D^zGSH1
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v
L0 34
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v|
!s101 -O0
!i113 1
R6
vaxi_RA_ARBITER
R7
!i10b 1
!s100 2FDF6>?kXRYfm<_VcLe2b3
IODYa3OJKODBJk[mCN=Udc0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v
R20
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v|
!s101 -O0
!i113 1
R6
naxi_@r@a_@a@r@b@i@t@e@r
vaxi_ra_channel
R17
!i10b 1
!s100 jOM5_AiO;UF=zabjn2<Hb1
I_6aE]0FXf:LVm0]FC0Jnh1
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v|
!s101 -O0
!i113 1
R6
vaxi_rd_channel
R7
!i10b 1
!s100 ReEkKXHfN;2fZS>i0WJ2L3
I4^X189^[g4fn_Gl4P]Ylg0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v
R21
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v|
!s101 -O0
!i113 1
R6
vaxi_rdmatrix_16Sto1M
R7
!i10b 1
!s100 0T77n5ZEKek1`ZMnjjd6C1
IPJRSU9fMNi7m87nDlO3mJ0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v
R21
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v|
!s101 -O0
!i113 1
R6
naxi_rdmatrix_16@sto1@m
vaxi_rdmatrix_4Mto1S
R7
!i10b 1
!s100 Boal[[CR`ma8Ol<0aiJ7f0
I_i88MO;S;;Kf3Y1gXdh<D0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v
Z22 L0 32
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v|
!s101 -O0
!i113 1
R6
naxi_rdmatrix_4@mto1@s
vaxi_rdmatrix_4Mto1S_hgs_high
R17
!i10b 1
!s100 A1TeoZP[`hB2R?E49dcF43
I12]idm75dldW_@LnnF=^61
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v
R22
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v|
!s101 -O0
!i113 1
R6
naxi_rdmatrix_4@mto1@s_hgs_high
vaxi_rdmatrix_4Mto1S_hgs_low
R17
!i10b 1
!s100 2Ff>cYN<R=:IzI0n45NM<2
IE0jZcK5Jz;H]SGC3`zX>L1
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v
R22
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v|
!s101 -O0
!i113 1
R6
naxi_rdmatrix_4@mto1@s_hgs_low
vaxi_slave_stage
R19
!i10b 1
!s100 deG<MTS0BQ_oP7c9jf0N`2
I`=VAkWlh5Z_c]f;WeU6OV2
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v
R11
R4
r1
!s85 0
31
Z23 !s108 1455700337.000000
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v|
!s101 -O0
!i113 1
R6
vaxi_WA_ARBITER
R17
!i10b 1
!s100 Kh9bGBQGC7moVJA1kh4>T0
I^Zmk^WH@G^]A>2FDc`Yo]3
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v
R20
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v|
!s101 -O0
!i113 1
R6
naxi_@w@a_@a@r@b@i@t@e@r
vaxi_wa_channel
R17
!i10b 1
!s100 5NH8=aTDgh<3?:VXfA:Hf0
Ia31k0]j8G0e^B22>T`O=V1
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v|
!s101 -O0
!i113 1
R6
vaxi_wd_channel
R17
!i10b 1
!s100 OOnZEW0ejEVTD_5A092lA3
I6[]TcD6[K1UVUm[E?R``?3
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v|
!s101 -O0
!i113 1
R6
vaxi_wresp_channel
R7
!i10b 1
!s100 <_n9Q[b4nZ[nDJ]nn0NFF1
IAEY4oG4HAg4`gWBAzm5bJ2
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v
R21
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v|
!s101 -O0
!i113 1
R6
vaxi_wrmatrix_4Mto1S
R17
!i10b 1
!s100 WV2nm3bNL0<WgSbg_17272
IcPU1M3HFn]EPOaf_O3Gd=3
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v|
!s101 -O0
!i113 1
R6
naxi_wrmatrix_4@mto1@s
vaxi_wrmatrix_4Mto1S_hgs_high
R17
!i10b 1
!s100 GG:nICjB]@Q]eSoLM<EmX1
IFXlVZh^BY;_WQ3F3ZVN7V0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v|
!s101 -O0
!i113 1
R6
naxi_wrmatrix_4@mto1@s_hgs_high
vaxi_wrmatrix_4Mto1S_hgs_low
R17
!i10b 1
!s100 KiLzn4aYfn1aO1P38>[Tl1
I@Li5ANiViQ2_Z<ZcHiJ<z0
R2
R3
R8
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v
R21
R4
r1
!s85 0
31
R18
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v|
!s101 -O0
!i113 1
R6
naxi_wrmatrix_4@mto1@s_hgs_low
vCMD_Decoder
R1
!i10b 1
!s100 DaHl6@iMjnN@o86?e8dN>3
I8KEI9kQLlV0?`G]QaWoPU2
R2
R3
w1398159676
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/CMD_Decoder.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/CMD_Decoder.v
Z24 L0 21
R4
r1
!s85 0
31
R5
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/CMD_Decoder.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/CMD_Decoder.v|
!s101 -O0
!i113 1
R6
n@c@m@d_@decoder
vCMD_Decoder_tb
I7`nBl0=>an9kbUkAl;k9S2
R13
Z25 dD:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/simulation
w1397212584
8D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/CMD_Decoder_tb.v
FD:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/CMD_Decoder_tb.v
R9
R16
r1
31
R6
Z26 !s92 +incdir+D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus -work presynth -O0
n@c@m@d_@decoder_tb
!s110 1397213536
!i10b 1
!s100 6o1ILD7UDbzgSe;h?SDXe2
!s85 0
!s108 1397213536.345000
!s107 D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/CMD_Decoder_tb.v|
!s90 -reportprogress|300|+incdir+D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus|-work|presynth|D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/CMD_Decoder_tb.v|
!s101 -O0
vCOM_Interface
Z27 !s110 1455700338
!i10b 1
!s100 gjTW:]Hl0Y5c<klSjX8c13
IN79n0Kl3IA0K^Hi48Ni161
R2
R3
w1455699846
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COM_Interface.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COM_Interface.v
L0 9
R4
r1
!s85 0
31
Z28 !s108 1455700338.000000
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COM_Interface.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COM_Interface.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface
vCOM_Interface_COREUART_0_Clock_gen
R27
!i10b 1
!s100 lPRiZ@eocJPBcjLOC_CH?3
IFWG1nAi@j3C4gFIG`5QzZ1
R2
R3
Z29 w1455699840
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v
R9
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Clock_gen.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_@clock_gen
vCOM_Interface_COREUART_0_COREUART
R27
!i10b 1
!s100 Q^CdJ4Z6Y@RSiDi8A27j?2
I@H_:8h:ef]3ZCD1DjH0<J2
R2
R3
R29
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v
Z30 L0 14
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/CoreUART.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_@c@o@r@e@u@a@r@t
vCOM_Interface_COREUART_0_fifo_256x8
R27
!i10b 1
!s100 fKXF1k?Mg=CZAMGhhGZM33
I72:2eJn7CeOZiMXma>lFn1
R2
R3
R29
Z31 8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_smartfusion2.v
Z32 FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_smartfusion2.v
R30
R4
r1
!s85 0
31
R28
Z33 !s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_smartfusion2.v|
Z34 !s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/fifo_256x8_smartfusion2.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_fifo_256x8
vCOM_Interface_COREUART_0_fifo_ctrl_128
R27
!i10b 1
!s100 WM:BO`I:LV8Wi6@V79dYc3
IWWA5jd8DhHTfUiUFR;FA`1
R2
R3
R29
R31
R32
L0 155
R4
r1
!s85 0
31
R28
R33
R34
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_fifo_ctrl_128
vCOM_Interface_COREUART_0_ram128x8_pa4
R27
!i10b 1
!s100 MofXQVQg88gfic3Hljh0J2
IePI`:VNf`nm8695[TenXM2
R2
R3
R29
R31
R32
L0 649
R4
r1
!s85 0
31
R28
R33
R34
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_ram128x8_pa4
vCOM_Interface_COREUART_0_Rx_async
R27
!i10b 1
!s100 jd:>z1J8@Q?dA2:<_7Ek;3
IS3Td4oZ`nfNHegn1F_45Z2
R2
R3
R29
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v
R30
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Rx_async.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_@rx_async
vCOM_Interface_COREUART_0_Tx_async
R27
!i10b 1
!s100 nBYkU;ne@Q7IiSA89Of0I2
IHFHd]73^P:<lNU?XROJKA1
R2
R3
R29
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v
R30
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/COREUART_0/rtl/vlog/core_obfuscated/Tx_async.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@c@o@r@e@u@a@r@t_0_@tx_async
vCOM_Interface_tb
IKI34Io=>dP;a>E@5:eFid0
R13
R25
w1397021725
8D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/COM_Interface_tb.v
FD:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/COM_Interface_tb.v
R24
R16
r1
31
R6
n@c@o@m_@interface_tb
R26
!s110 1397023084
!i10b 1
!s100 0HR=W6@cFRUHSP@W=o0?M2
!s85 0
!s108 1397023084.025000
!s107 D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/COM_Interface_tb.v|
!s90 -reportprogress|300|+incdir+D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus|-work|presynth|D:/Learning/DDR/Design/IGL2/LOW_POWER/1/Libero_Project/MDDR_TA/stimulus/COM_Interface_tb.v|
!s101 -O0
vCOM_Interface_TPSRAM_0_TPSRAM
R27
!i10b 1
!s100 95IQPPNion<DUj<;5_UHO0
II9BmI2>e<XD?G`]S0hXZ21
R2
R3
w1455699845
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v
L0 5
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/COM_Interface/TPSRAM_0/COM_Interface_TPSRAM_0_TPSRAM.v|
!s101 -O0
!i113 1
R6
n@c@o@m_@interface_@t@p@s@r@a@m_0_@t@p@s@r@a@m
vControl_Logic
R27
!i10b 1
!s100 4DD7<<1KKQ^;Zn<3UgnPB3
I0PVQS19_mPJn^=B49oEkg1
R2
R3
w1416909601
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/Control_Logic.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/Control_Logic.v
R24
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/Control_Logic.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/hdl/Control_Logic.v|
!s101 -O0
!i113 1
R6
n@control_@logic
vCoreConfigMaster
R1
!i10b 1
!s100 AGzI9_G[?n<k?TR_5]EgG1
IGUnF[me<4hWF2;flzh;bh1
R2
R3
w1455697784
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v
L0 24
R4
r1
!s85 0
31
R5
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vlog/core/coreconfigmaster.v|
!s101 -O0
!i113 1
R6
n@core@config@master
vCoreConfigP
R7
!i10b 1
!s100 NC@o4lVhJKc>5][eOzz[e1
I_YZGc_C2;oba49WO^Ied@3
R2
R3
Z35 w1455697818
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v
L0 22
R4
r1
!s85 0
31
R5
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v|
!s101 -O0
!i113 1
R6
n@core@config@p
vCoreResetP
R7
!i10b 1
!s100 GNO^jQOff>hR9=b6B2heR1
IYOU5FD;3>oTKSK7A@goT32
R2
R3
R35
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v
Z36 L0 23
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v|
!s101 -O0
!i113 1
R6
n@core@reset@p
vcoreresetp_pcie_hotreset
R7
!i10b 1
!s100 Io@TN_8VJ[8aKmHaHh9@j1
IDL3Z8[=^J;:@gCh98_ZCG3
R2
R3
R35
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v
L0 31
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v|
!s101 -O0
!i113 1
R6
vdram
Z37 !s110 1395847974
I:nd8T01=zXMgNg>fnM?9e2
R13
Z38 dD:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/simulation
Z39 w1395840729
FD:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/dram.v
Z40 8D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/testbench.v
Z41 FD:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/testbench.v
FD:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/dram_parameters.vh
L0 83
R16
r1
31
Z42 !s108 1395847974.453000
Z43 !s107 D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/dram_parameters.vh|D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/dram.v|D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/testbench.v|
Z44 !s90 -reportprogress|300|+incdir+D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus|-work|presynth|D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus/testbench.v|
R6
Z45 !s92 +incdir+D:/Learning/DDR/Design/IGL2/v0.4/MDDR_TA/stimulus -work presynth -O0
!i10b 1
!s100 =>NEoaZ;_5N5ORf::a_m83
!s85 0
!s101 -O0
vLPDDR_VIP_Simulation
R27
!i10b 1
!s100 9^MMDeXU:^lTXf9j`lLQj0
I`LhzkOTDU@z@;5P8EX<3H3
R2
R3
w1455700163
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation/LPDDR_VIP_Simulation.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation/LPDDR_VIP_Simulation.v
L0 9
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation/LPDDR_VIP_Simulation.v|
!s90 -reportprogress|300|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation/LPDDR_VIP_Simulation.v|
!s101 -O0
!i113 1
R6
Z46 !s92 +incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1 +incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data +incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation -work presynth -O0
n@l@p@d@d@r_@v@i@p_@simulation
vmaster_stage
R12
I@4Ba<_nFkGm:C]T[B5i;;3
R13
R14
R15
8D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/master_stage.v
FD:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/master_stage.v
R20
R16
r1
31
R6
!i10b 1
!s100 C@jlz8O=MOS1f`:Lnk6nU2
!s85 0
!s108 1401871511.802000
!s107 D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/master_stage.v|
!s90 -reportprogress|300|-work|presynth|D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/master_stage.v|
!s101 -O0
vMDDR_TA
R27
!i10b 1
!s100 ]Y]BR=]>MmeWojo?5W;VL3
IC8fA^E0BzWOfBNQ=DG^KT0
R2
R3
Z47 w1455699795
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v
L0 9
R4
r1
!s85 0
31
R23
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a
vMDDR_TA_CCC_0_FCCC
R7
!i10b 1
!s100 QzDR]HHR4oz9I4:m8DV7R0
Igl^boFdMoe8fOUaH426;;2
R2
R3
w1455699793
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v
L0 5
R4
r1
!s85 0
31
R10
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a_@c@c@c_0_@f@c@c@c
vMDDR_TA_COREAXI_0_COREAXI
R19
!i10b 1
!s100 ^BojClXz`3TJh@P3R5J[h1
IVOV;ILRBEDlk5SH51af@m0
R2
R3
w1455699794
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v
R11
R4
r1
!s85 0
31
R23
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a_@c@o@r@e@a@x@i_0_@c@o@r@e@a@x@i
vMDDR_TA_FABOSC_0_OSC
R19
!i10b 1
!s100 aeJ4iUfU<R88592T4YReU0
Io4z0f`9KZWPUV2XldGoPd0
R2
R3
R47
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v
L0 5
R4
r1
!s85 0
31
R23
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a_@f@a@b@o@s@c_0_@o@s@c
vMDDR_TA_HPMS
R19
!i10b 1
!s100 =X9FXY=JmCOgmZSf^mGLf3
IDWMJNl?zM09mT9Je=a?CJ1
R2
R3
w1455699789
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v
L0 9
R4
r1
!s85 0
31
R23
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_HPMS/MDDR_TA_HPMS.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a_@h@p@m@s
vMDDR_TA_top
R27
!i10b 1
!s100 S>LQ16;>@;R@9UM]hHT`23
IGo1Ck1oT@:JH8[cEX82oY1
R2
R3
w1455699819
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v
L0 9
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v|
!s90 -reportprogress|300|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v|
!s101 -O0
!i113 1
R6
n@m@d@d@r_@t@a_top
vmobile_ddr
IMa7m?@8:aaa?XP`Vb>Yo]1
R13
R0
w1395740477
FD:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/mobile_ddr.v
8D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/testbench.v
FD:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/testbench.v
FD:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/512Mb_mobile_ddr_parameters.vh
L0 94
R16
r1
31
R6
!s92 +incdir+D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus -work presynth -O0
!s110 1395740499
!s108 1395740499.504000
!s107 D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/512Mb_mobile_ddr_parameters.vh|D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/mobile_ddr.v|D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/testbench.v|
!s90 -reportprogress|300|+incdir+D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus|-work|presynth|D:/Learning/DDR/Design/IGL2/v0.1/MDDR_TA/stimulus/testbench.v|
!i10b 1
!s100 @4EiC5?EkU]MnEA_f2[722
!s85 0
!s101 -O0
vRESET_GEN
R27
!i10b 1
!s100 ^eT^?3Tbjk^[^3?FTW9WM1
IGiQ@a0`0DDV@?C0QRZYF51
R2
R3
w1455698303
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v
L0 3
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v|
!s90 -reportprogress|300|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1/RESET_GEN.v|
!s101 -O0
!i113 1
R6
R46
n@r@e@s@e@t_@g@e@n
vSimDRAM
R27
!i10b 1
!s100 7GBN0=8AldX<=2znK<WkL2
I9BkD1JKJI4QN]l7mnNH8H1
R2
R3
w1455699585
8F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data/SimDRAM.v
FF:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data/SimDRAM.v
L0 1
R4
r1
!s85 0
31
R28
!s107 F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data/SimDRAM.v|
!s90 -reportprogress|300|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/RESET_GEN/1.0.1|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data|+incdir+F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/work/LPDDR_VIP_Simulation|-work|presynth|F:/M2S_M2GL_AC428_DF/Libero_Project/MDDR_TA/component/Actel/Simulation/SimDRAM/1.0.102/data/SimDRAM.v|
!s101 -O0
!i113 1
R6
R46
n@sim@d@r@a@m
vslave_stage
R12
IFEdcK>]zLUZ2g6V]GY_001
R13
R14
R15
8D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/slave_stage.v
FD:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/slave_stage.v
R20
R16
r1
31
R6
!i10b 1
!s100 QKz?FZTIcA[VS]@l8KV5a0
!s85 0
!s108 1401871511.932000
!s107 D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/slave_stage.v|
!s90 -reportprogress|300|-work|presynth|D:/Learning/DDR/Design/IGL2/LOW_POWER/FOR_RELEASE/v2/IGL2_LPDDR_POWER_DF/Libero_Project/MDDR_TA/component/Actel/DirectCore/COREAXI/2.1.101/rtl/vlog/core/slave_stage.v|
!s101 -O0
vtestbench
R37
I??FOWmSPd19KAmB^2e_1i3
R13
R38
R39
R40
R41
R36
R16
r1
31
R42
R43
R44
R6
R45
!i10b 1
!s100 EoGROC=WnflY@Um8dllKG3
!s85 0
!s101 -O0
