@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\hdl\axi_if.v":553:0:553:5|Removing sequential instance AXI_IF_0.ARBURST_1[0],  because it is equivalent to instance AXI_IF_0.ARSIZE_1[0]
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\hdl\axi_if.v":265:0:265:5|Removing sequential instance AXI_IF_0.AWBURST_1[0],  because it is equivalent to instance AXI_IF_0.AWSIZE_1[0]
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance MDDR_TA_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT530 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including MDDR_TA_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreconfigmaster\2.1.102\rtl\vlog\core\coreconfigmaster.v":723:4:723:9|Found inferred clock MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock which controls 575 sequential elements including MDDR_TA_0.ConfigMaster_0.state[28:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including MDDR_TA_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\m2s_m2gl_ac428_df\libero_project\mddr_ta\hdl\ahb_if.v":70:0:70:5|Found inferred clock MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock which controls 725 sequential elements including AHB_IF_0.HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
