//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Feb 17 14:34:17 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ps/1fs

// LPDDR_VIP_Simulation
module LPDDR_VIP_Simulation(
    // Outputs
    TX
);

//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output TX;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [15:0] MDDR_TA_top_0_MDDR_ADDR;
wire   [2:0]  MDDR_TA_top_0_MDDR_BA;
wire          MDDR_TA_top_0_MDDR_CAS_N;
wire          MDDR_TA_top_0_MDDR_CKE;
wire          MDDR_TA_top_0_MDDR_CLK;
wire          MDDR_TA_top_0_MDDR_CLK_N;
wire          MDDR_TA_top_0_MDDR_CS_N;
wire          MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT;
wire          MDDR_TA_top_0_MDDR_RAS_N;
wire          MDDR_TA_top_0_MDDR_WE_N;
wire   [1:0]  net_0;
wire   [15:0] net_1;
wire   [1:0]  net_2;
wire          RESET_GEN_0_RESET;
wire          TX_net_0;
wire          TX_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
wire   [1:0]  DRAM_DM_RDQS_const_net_0;
wire   [1:0]  DRAM_DQS_N_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net                  = 1'b0;
assign DRAM_DM_RDQS_const_net_0 = 2'h0;
assign DRAM_DQS_N_const_net_0   = 2'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TX_net_1 = TX_net_0;
assign TX       = TX_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MDDR_TA_top
MDDR_TA_top MDDR_TA_top_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN  ( MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .DEVRST_N              ( RESET_GEN_0_RESET ),
        .RX                    ( GND_net ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT ( MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .MDDR_CAS_N            ( MDDR_TA_top_0_MDDR_CAS_N ),
        .MDDR_CLK              ( MDDR_TA_top_0_MDDR_CLK ),
        .MDDR_CLK_N            ( MDDR_TA_top_0_MDDR_CLK_N ),
        .MDDR_CKE              ( MDDR_TA_top_0_MDDR_CKE ),
        .MDDR_CS_N             ( MDDR_TA_top_0_MDDR_CS_N ),
        .MDDR_ODT              (  ),
        .MDDR_RAS_N            ( MDDR_TA_top_0_MDDR_RAS_N ),
        .MDDR_RESET_N          (  ),
        .MDDR_WE_N             ( MDDR_TA_top_0_MDDR_WE_N ),
        .TX                    ( TX_net_0 ),
        .MDDR_ADDR             ( MDDR_TA_top_0_MDDR_ADDR ),
        .MDDR_BA               ( MDDR_TA_top_0_MDDR_BA ),
        // Inouts
        .MDDR_DM_RDQS          ( net_2 ),
        .MDDR_DQ               ( net_1 ),
        .MDDR_DQS              ( net_0 ) 
        );

//--------RESET_GEN   -   Actel:Simulation:RESET_GEN:1.0.1
RESET_GEN #( 
        .DELAY       ( 1000 ),
        .LOGIC_LEVEL ( 0 ) )
RESET_GEN_0(
        // Outputs
        .RESET ( RESET_GEN_0_RESET ) 
        );

//--------SimDRAM   -   Actel:Simulation:SimDRAM:1.0.102
SimDRAM #( 
        .AL                 ( 0 ),
        .BL_BITS            ( 8 ),
        .CL                 ( 3 ),
        .CWL                ( 5 ),
        .DQ_BITS            ( 16 ),
        .MEMORY             ( 2 ),
        .PARTIAL_REFRESH_EN ( 0 ),
        .RZQ                ( 240 ),
        .TRFC               ( 25 ),
        .WR                 ( 8 ) )
SimDRAM_0(
        // Inputs
        .DRAM_CAS_N   ( MDDR_TA_top_0_MDDR_CAS_N ),
        .DRAM_CKE     ( MDDR_TA_top_0_MDDR_CKE ),
        .DRAM_CLK     ( MDDR_TA_top_0_MDDR_CLK ),
        .DRAM_CLK_N   ( MDDR_TA_top_0_MDDR_CLK_N ),
        .DRAM_CS_N    ( MDDR_TA_top_0_MDDR_CS_N ),
        .DRAM_ODT     ( GND_net ), // tied to 1'b0 from definition
        .DRAM_RAS_N   ( MDDR_TA_top_0_MDDR_RAS_N ),
        .DRAM_RESET_N ( GND_net ), // tied to 1'b0 from definition
        .DRAM_WE_N    ( MDDR_TA_top_0_MDDR_WE_N ),
        .DRAM_ADDR    ( MDDR_TA_top_0_MDDR_ADDR ),
        .DRAM_BA      ( MDDR_TA_top_0_MDDR_BA ),
        .DRAM_DM      ( net_2 ),
        // Outputs
        .DRAM_RDQS_N  (  ),
        // Inouts
        .DRAM_DM_RDQS ( DRAM_DM_RDQS_const_net_0 ), // tied to 2'h0 from definition
        .DRAM_DQS     ( net_0 ),
        .DRAM_DQS_N   ( DRAM_DQS_N_const_net_0 ), // tied to 2'h0 from definition
        .DRAM_DQ      ( net_1 ) 
        );



wire 		MDDR_CLK;
wire 		MDDR_CKE;
wire 		MDDR_CS_N;
wire [15:0] MDDR_ADDR;
wire [2:0]  MDDR_BA;
		
wire [7:0]  TX_DATA;
wire [1:0]  MDDR_DM_RDQS;
wire [15:0] MDDR_DQ;
wire [1:0]  MDDR_DQS;
wire [2:0]  COMMAND;
reg txdata;

reg BRCLK;
parameter BRCLK_PERIOD  = 8680500;  /* COREUART BAUD RATE 115200 Hz */

assign MDDR_DM_RDQS = net_2;
assign MDDR_DQ      = net_1;
assign MDDR_DQS     = net_0;
assign MDDR_CLK     = MDDR_TA_top_0_MDDR_CLK;
assign MDDR_CKE     = MDDR_TA_top_0_MDDR_CKE;
assign MDDR_CS_N    = MDDR_TA_top_0_MDDR_CS_N;
assign MDDR_ADDR    = MDDR_TA_top_0_MDDR_ADDR;
assign MDDR_BA      = MDDR_TA_top_0_MDDR_BA;

assign COMMAND = {MDDR_TA_top_0_MDDR_RAS_N,MDDR_TA_top_0_MDDR_CAS_N,MDDR_TA_top_0_MDDR_WE_N};
assign TX_DATA = LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_IN;

initial
begin

    BRCLK     = 1'b0;
    @(posedge LPDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
    repeat(3000)
      begin
         #(BRCLK_PERIOD / 2.0) BRCLK <= !BRCLK;
      end

end


initial
begin
    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
    $display ("Loading LSRAM from lsram.mem file");
    $display ("");
    $readmemh("lsram_512x64.mem",LPDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.Rdata_mem);
    $display (" Completed Loading LSRAM"); 
    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");

    @(posedge LPDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.RESETn);

    force LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_OUT  = 8'b01_1110_00;  /* Handshaking Command 'x'         */
	@(posedge txdata )                                                                              /* Waiting for acknowledgement 'a' */
	repeat(1) @(posedge BRCLK);
	force LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_OUT  = 8'b00_0000_01;  /* Write command                   */
    repeat(10) @(posedge BRCLK);
	
	force LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_OUT  = 8'b00_1000_00;  /* DEEP POWER DOWN Entry           */
    repeat(10) @(posedge BRCLK);
	
	force LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_OUT  = 8'b00_0101_10;  /* DEEP POWER DOWN Exit and Read   */
	repeat(10) @(posedge BRCLK);
	
	force LPDDR_VIP_Simulation.MDDR_TA_top_0.COM_Interface_0.COREUART_0.DATA_OUT  = 8'b00_0000_00;  /* NO OPERATION                    */
	
end

always @(posedge LPDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK)
begin
 if(TX_DATA == 8'b01100001) 
   begin
     txdata  <= 1'b1;
   end
 else
   begin
     txdata  <= 1'b0;
   end
end

endmodule




