Project Settings
Project Name | MDDR_TA_top_syn | Implementation Name | synthesis_1
Top Module | MDDR_TA_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
Compile Input | Complete | 86 | 1160 | 0 | - | 0m:08s | - | 3/27/2014 12:20:11 PM
Pre-mapping | Complete | 52 | 22 | 0 | 0m:01s | 0m:03s | 156MB | 3/27/2014 12:20:16 PM
Map & Optimize | Complete | 416 | 3007 | 0 | 0m:14s | 0m:17s | 190MB | 3/27/2014 12:20:34 PM
Area Summary
Carry Cells | 317 | Sequential Cells | 956
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 51
Global Clock Buffers | 8 | Block Rams (RAM1K18) (v_ram) | 3
LUTs (total_luts) | 1624 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock | 400.0 MHz | 123.4 MHz | -5.603
MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock | 400.0 MHz | 107.4 MHz | -6.815
MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 400.0 MHz | 400.2 MHz | 0.001
MDDR_TA_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 400.0 MHz | 161.8 MHz | -3.682
System | 400.0 MHz | 293.1 MHz | -0.912
Optimizations Summary
Combined Clock Conversion | 3 / 1 |  |