Project Settings
Project Name Mult32x32_multipleMACC_syn Implementation Name synthesis
Top Module work.Mult32x32_multipleMACC Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 0 0 - 0m:00s - 2/16/2016
2:12:56 PM
(premap)Complete 3 1 0 0m:00s 0m:00s 134MB 2/16/2016
2:12:58 PM
(fpga_mapper)Complete 11 1 0 0m:13s 0m:13s 192MB 2/16/2016
2:13:11 PM
Multi-srs Generator Complete0m:01s2/16/2016
2:12:57 PM

Area Summary
Sequential Cells 145 DSP Blocks (MACC) (dsp_used) 4
I/O Cells 130 Global Clock Buffers 2
LUTs (total_luts) 0

Timing Summary
Clock NameReq FreqEst FreqSlack
Mult32x32_multipleMACC|clk100.0 MHz368.2 MHz7.284

Optimizations Summary
Combined Clock Conversion 1 / 0