@W: MT530 :"e:\libero_11p7_updates\downloaded\dspan_gl2_df\igloo2\wide multiplier\mult32x32_multipliemacc\hdl\mult32x32_multiplemacc.vhd":68:4:68:5|Found inferred clock Mult32x32_multipleMACC|clk which controls 256 sequential elements including Mul_result[63:0]. This clock has no specified timing constraint which may adversely impact design performance. 
