Project Settings
Project Name Mult32x32_SingleMACC_syn Implementation Name synthesis
Top Module work.Mult32x32_SingleMACC Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 13 2 0 - 0m:01s - 2/16/2016
12:07:53 PM
(premap)Complete 3 1 0 0m:00s 0m:00s 135MB 2/16/2016
12:07:54 PM
(fpga_mapper)Complete 10 2 0 0m:01s 0m:01s 137MB 2/16/2016
12:07:56 PM
Multi-srs Generator Complete0m:00s2/16/2016
12:07:54 PM

Area Summary
Sequential Cells 105 DSP Blocks (MACC) (dsp_used) 1
I/O Cells 132 Global Clock Buffers 2
LUTs (total_luts) 47

Timing Summary
Clock NameReq FreqEst FreqSlack
Mult32x32_SingleMACC|clk100.0 MHz368.4 MHz7.286

Optimizations Summary
Combined Clock Conversion 1 / 0