#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-KUMARJ #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : Mult32x32_SingleMACC.vhd(24) | Top entity is set to Mult32x32_SingleMACC. File C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd changed - recompiling File E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\hdl\acc_0.vhd changed - recompiling File E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\hdl\Mult32x32_SingleMACC.vhd changed - recompiling File C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\signed.vhd changed - recompiling VHDL syntax check successful! Compiler output is up to date. No re-compile necessary @N:CD630 : Mult32x32_SingleMACC.vhd(24) | Synthesizing work.mult32x32_singlemacc.mult32x32_gl2_arch @N:CD231 : Mult32x32_SingleMACC.vhd(67) | Using onehot encoding for type state (idle="100000000") @W:CD638 : Mult32x32_SingleMACC.vhd(83) | Signal cdin is undriven @W:CD638 : Mult32x32_SingleMACC.vhd(85) | Signal co is undriven @N:CD630 : acc_0.vhd(17) | Synthesizing work.acc_0.rtl @N:CD630 : acc_0_acc_0_0_HARD_MULT_ACC.vhd(8) | Synthesizing work.acc_0_acc_0_0_hard_mult_acc.def_arch @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(702) | Synthesizing smartfusion2.macc.syn_black_box Post processing for smartfusion2.macc.syn_black_box Post processing for work.acc_0_acc_0_0_hard_mult_acc.def_arch Post processing for work.acc_0.rtl Post processing for work.mult32x32_singlemacc.mult32x32_gl2_arch @N:CL201 : Mult32x32_SingleMACC.vhd(98) | Trying to extract state machine for register Curr_State Extracted state machine for register Curr_State State machine has 9 reachable states with original encodings of: 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:52 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:53 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:53 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201403MSP1\bin64\syn_nfilter.exe changed - recompiling File D:\Projects\Updates\AC398\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\synthesis\synwork\Mult32x32_SingleMACC_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:54 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @L: E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC_scck.rpt Printing clock summary report in "E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) syn_allowed_resources : blockrams=69 set on top level netlist Mult32x32_SingleMACC Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------- Mult32x32_SingleMACC|clk 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ========================================================================================= @W:MT530 : acc_0_acc_0_0_hard_mult_acc.vhd(111) | Found inferred clock Mult32x32_SingleMACC|clk which controls 111 sequential elements including U1.acc_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\synthesis\Mult32x32_SingleMACC.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:54 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 134MB) Encoding state machine Curr_State[0:8] (view:work.Mult32x32_SingleMACC(mult32x32_gl2_arch)) original code -> new code 000000001 -> 0000 000000010 -> 0001 000000100 -> 0010 000001000 -> 0011 000010000 -> 0100 000100000 -> 0101 001000000 -> 0110 010000000 -> 0111 100000000 -> 1000 @W:BN132 : mult32x32_singlemacc.vhd(181) | Removing instance mul_result_valid, because it is equivalent to instance Curr_State[3] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 7.16ns 48 / 105 @N:FP130 : | Promoting Net clk_c on CLKINT I_897 @N:FP130 : | Promoting Net reset_n_c on CLKINT I_898 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 107 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 107 Curr_State[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 137MB) Writing Analyst data base E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Wide Multiplier\Mult32x32\synthesis\synwork\Mult32x32_SingleMACC_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 137MB) @W:MT420 : | Found inferred clock Mult32x32_SingleMACC|clk with period 10.00ns. Please declare a user-defined clock on object "p:clk" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Tue Feb 16 12:07:56 2016 # Top view: Mult32x32_SingleMACC Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 7.286 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------- Mult32x32_SingleMACC|clk 100.0 MHz 368.4 MHz 10.000 2.714 7.286 inferred Inferred_clkgroup_0 =============================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------ Mult32x32_SingleMACC|clk Mult32x32_SingleMACC|clk | 10.000 7.286 | No paths - | No paths - | No paths - ========================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Mult32x32_SingleMACC|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- Curr_State[0] Mult32x32_SingleMACC|clk SLE Q Curr_State[0] 0.094 7.286 Curr_State[1] Mult32x32_SingleMACC|clk SLE Q Curr_State[1] 0.094 7.517 Curr_State[2] Mult32x32_SingleMACC|clk SLE Q Curr_State[2] 0.094 7.589 Curr_State[3] Mult32x32_SingleMACC|clk SLE Q Curr_State[3] 0.094 7.712 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[0] P[0] 0.192 8.606 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[1] P[1] 0.192 8.606 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[2] P[2] 0.192 8.606 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[3] P[3] 0.192 8.606 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[4] P[4] 0.192 8.606 U1.acc_0_0.U0 Mult32x32_SingleMACC|clk MACC P[5] P[5] 0.192 8.606 ==================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- A0[0] Mult32x32_SingleMACC|clk SLE D A0_4[0] 9.778 7.286 A0[1] Mult32x32_SingleMACC|clk SLE D A0_4[1] 9.778 7.286 A0[2] Mult32x32_SingleMACC|clk SLE D A0_4[2] 9.778 7.286 A0[3] Mult32x32_SingleMACC|clk SLE D A0_4[3] 9.778 7.286 A0[4] Mult32x32_SingleMACC|clk SLE D A0_4[4] 9.778 7.286 A0[5] Mult32x32_SingleMACC|clk SLE D A0_4[5] 9.778 7.286 A0[6] Mult32x32_SingleMACC|clk SLE D A0_4[6] 9.778 7.286 A0[7] Mult32x32_SingleMACC|clk SLE D A0_4[7] 9.778 7.286 A0[8] Mult32x32_SingleMACC|clk SLE D A0_4[8] 9.778 7.286 A0[9] Mult32x32_SingleMACC|clk SLE D A0_4[9] 9.778 7.286 ========================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.492 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 7.286 Number of logic level(s): 2 Starting point: Curr_State[0] / Q Ending point: A0[0] / D The start point is clocked by Mult32x32_SingleMACC|clk [rising] on pin CLK The end point is clocked by Mult32x32_SingleMACC|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- Curr_State[0] SLE Q Out 0.094 0.094 - Curr_State[0] Net - - 1.011 - 28 Curr_State_ns_3_0_.A0_4_sn_m2 CFG3 C In - 1.105 - Curr_State_ns_3_0_.A0_4_sn_m2 CFG3 Y Out 0.196 1.302 - A0_4_sn_N_3 Net - - 0.924 - 34 Curr_State_ns_3_0_.A0_4[0] CFG4 B In - 2.225 - Curr_State_ns_3_0_.A0_4[0] CFG4 Y Out 0.129 2.354 - A0_4[0] Net - - 0.138 - 1 A0[0] SLE D In - 2.492 - ============================================================================================ Total path delay (propagation time + setup) of 2.714 is 0.642(23.6%) logic and 2.073(76.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 137MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 136MB peak: 137MB) --------------------------------------- Resource Usage Report for Mult32x32_SingleMACC Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses CFG2 3 uses CFG3 7 uses CFG4 37 uses Sequential Cells: SLE 105 uses DSP Blocks: 1 MACC: 1 Mult I/O ports: 132 I/O primitives: 132 INBUF 67 uses OUTBUF 65 uses Global Clock Buffers: 2 Total LUTs: 47 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 36; LUTs = 36; Total number of SLEs after P&R: 105 + 0 + 0 + 36 = 141; Total number of LUTs after P&R: 47 + 0 + 0 + 36 = 83; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 52MB peak: 137MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 16 12:07:56 2016 ###########################################################]