@W: MT530 :"e:\libero_11p7_updates\downloaded\dspan_gl2_df\igloo2\wide multiplier\mult32x32\hdl\acc_0_acc_0_0_hard_mult_acc.vhd":111:4:111:5|Found inferred clock Mult32x32_SingleMACC|clk which controls 111 sequential elements including U1.acc_0_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
