| Project Settings |
|---|
| Project Name | FIR_6tap_syn | Implementation Name | synthesis |
| Top Module | work.FIR_6tap | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
11 |
0 |
0 |
- |
0m:01s |
- |
2/17/2016
4:36:18 PM |
| (premap) | Complete |
3 |
1 |
0 |
0m:00s |
0m:00s |
137MB |
2/17/2016
4:36:20 PM |
| (fpga_mapper) | Complete |
10 |
1 |
0 |
0m:01s |
0m:01s |
136MB |
2/17/2016
4:36:21 PM |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 2/17/2016
4:36:19 PM |
| Area Summary |
|---|
| |
| Sequential Cells | 72 |
DSP Blocks (MACC)
(dsp_used) | 3 |
| I/O Cells | 46 |
Global Clock Buffers | 2 |
| LUTs
(total_luts) | 0 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| FIR_6tap|clk | 100.0 MHz | 368.2 MHz | 7.284 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|