#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-KUMARJ #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : FIR_6_TAP.vhd(26) | Top entity is set to FIR_6tap. Options changed - recompiling VHDL syntax check successful! Options changed - recompiling @N:CD630 : FIR_6_TAP.vhd(26) | Synthesizing work.fir_6tap.def_arch @N:CD630 : Dotmul_add.vhd(17) | Synthesizing work.dotmul_add.rtl @N:CD630 : Dotmul_add_Dotmul_add_0_HARD_MULT_ADDSUB.vhd(8) | Synthesizing work.dotmul_add_dotmul_add_0_hard_mult_addsub.def_arch @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(702) | Synthesizing smartfusion2.macc.syn_black_box Post processing for smartfusion2.macc.syn_black_box Post processing for work.dotmul_add_dotmul_add_0_hard_mult_addsub.def_arch Post processing for work.dotmul_add.rtl Post processing for work.fir_6tap.def_arch At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:18 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using 9x9 Multiplier\FIR_6_TAP\synthesis\synwork\FIR_6tap_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:19 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: FIR_6tap_scck.rpt Printing clock summary report in "E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\synthesis\FIR_6tap_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) syn_allowed_resources : blockrams=69 set on top level netlist FIR_6tap Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------- FIR_6tap|clk 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ============================================================================= @W:MT530 : dotmul_add_dotmul_add_0_hard_mult_addsub.vhd(119) | Found inferred clock FIR_6tap|clk which controls 72 sequential elements including U0.Dotmul_add_0.U0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\synthesis\FIR_6tap.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 137MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:20 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 7.28ns 1 / 72 @N:FP130 : | Promoting Net clk_c on CLKINT I_1 @N:FP130 : | Promoting Net reset_n_c on CLKINT I_2 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 78 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 78 X6_reg[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 135MB) Writing Analyst data base E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\synthesis\synwork\FIR_6tap_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) @W:MT420 : | Found inferred clock FIR_6tap|clk with period 10.00ns. Please declare a user-defined clock on object "p:clk" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Feb 17 16:36:21 2016 # Top view: FIR_6tap Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 7.284 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------- FIR_6tap|clk 100.0 MHz 368.2 MHz 10.000 2.716 7.284 inferred Inferred_clkgroup_0 ===================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------ FIR_6tap|clk FIR_6tap|clk | 10.000 7.284 | No paths - | No paths - | No paths - ================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FIR_6tap|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[0] CDOUT1[0] 0.274 7.284 U0.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[0] CDOUT0[0] 0.274 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[1] CDOUT1[1] 0.274 7.284 U0.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[1] CDOUT0[1] 0.274 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[2] CDOUT1[2] 0.274 7.284 U0.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[2] CDOUT0[2] 0.274 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[3] CDOUT1[3] 0.274 7.284 U0.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[3] CDOUT0[3] 0.274 7.284 U0.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[4] CDOUT0[4] 0.274 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDOUT[4] CDOUT1[4] 0.274 7.284 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[0] CDOUT0[0] 8.529 7.284 U2.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[0] CDOUT1[0] 8.529 7.284 U2.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[1] CDOUT1[1] 8.529 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[1] CDOUT0[1] 8.529 7.284 U2.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[2] CDOUT1[2] 8.529 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[2] CDOUT0[2] 8.529 7.284 U2.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[3] CDOUT1[3] 8.529 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[3] CDOUT0[3] 8.529 7.284 U2.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[4] CDOUT1[4] 8.529 7.284 U1.Dotmul_add_0.U0 FIR_6tap|clk MACC CDIN[4] CDOUT0[4] 8.529 7.284 ============================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.471 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.529 - Propagation time: 1.245 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 7.284 Number of logic level(s): 0 Starting point: U1.Dotmul_add_0.U0 / CDOUT[0] Ending point: U2.Dotmul_add_0.U0 / CDIN[0] The start point is clocked by FIR_6tap|clk [rising] on pin CLK[0] The end point is clocked by FIR_6tap|clk [rising] on pin CLK[1] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------- U1.Dotmul_add_0.U0 MACC CDOUT[0] Out 0.274 0.274 - CDOUT1[0] Net - - 0.971 - 1 U2.Dotmul_add_0.U0 MACC CDIN[0] In - 1.245 - ===================================================================================== Total path delay (propagation time + setup) of 2.716 is 1.745(64.2%) logic and 0.971(35.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB) --------------------------------------- Resource Usage Report for FIR_6tap Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses Sequential Cells: SLE 72 uses DSP Blocks: 3 MACC: 3 Mults I/O ports: 46 I/O primitives: 46 INBUF 11 uses OUTBUF 35 uses Global Clock Buffers: 2 Total LUTs: 0 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 108; LUTs = 108; Total number of SLEs after P&R: 72 + 0 + 0 + 108 = 180; Total number of LUTs after P&R: 0 + 0 + 0 + 108 = 108; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 51MB peak: 136MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Feb 17 16:36:21 2016 ###########################################################]