@W: MT530 :"e:\libero_11p7_updates\downloaded\dspan_gl2_df\igloo2\using_9x9_multiplier\fir_6_tap\hdl\dotmul_add_dotmul_add_0_hard_mult_addsub.vhd":119:4:119:5|Found inferred clock FIR_6tap|clk which controls 72 sequential elements including U0.Dotmul_add_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
