@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\hdl\FIR_6_TAP.vhd":26:7:26:14|Top entity is set to FIR_6tap.
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\hdl\FIR_6_TAP.vhd":26:7:26:14|Synthesizing work.fir_6tap.def_arch 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\hdl\Dotmul_add.vhd":17:7:17:16|Synthesizing work.dotmul_add.rtl 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Using_9x9_Multiplier\FIR_6_TAP\hdl\Dotmul_add_Dotmul_add_0_HARD_MULT_ADDSUB.vhd":8:7:8:46|Synthesizing work.dotmul_add_dotmul_add_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":702:10:702:13|Synthesizing smartfusion2.macc.syn_black_box 
@N|Running in 64-bit mode

