Project Settings
Project Name Alphablending_syn Implementation Name synthesis
Top Module work.Alphablending Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 11 1 0 - 0m:00s - 2/16/2016
12:03:26 PM
(premap)Complete 3 1 0 0m:00s 0m:00s 136MB 2/16/2016
12:03:28 PM
(fpga_mapper)Complete 10 1 0 0m:00s 0m:00s 136MB 2/16/2016
12:03:29 PM
Multi-srs Generator Complete0m:00s2/16/2016
12:03:27 PM

Area Summary
Carry Cells 30 Sequential Cells 27
DSP Blocks (MACC) (dsp_used) 3 I/O Cells 69
Global Clock Buffers 2 LUTs (total_luts) 30

Timing Summary
Clock NameReq FreqEst FreqSlack
Alphablending|clk100.0 MHz369.8 MHz7.296

Optimizations Summary
Combined Clock Conversion 1 / 0