@W: MT530 :"e:\libero_11p7_updates\downloaded\dspan_gl2_df\igloo2\using 9x9 multiplier\alphablending\hdl\dotmultadd_dotmultadd_0_hard_mult_addsub.vhd":110:4:110:5|Found inferred clock Alphablending|clk which controls 27 sequential elements including U0.Dotmultadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 
