@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CD720 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd":24:7:24:28|Top entity is set to Extended_adder_3_input.
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\Extended_adder_3_input.vhd":24:7:24:28|Synthesizing work.extended_adder_3_input.extended_adder_3_input_arch 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\dotp_multadd.vhd":17:7:17:18|Synthesizing work.dotp_multadd.rtl 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\dotp_multadd_dotp_multadd_0_HARD_MULT_ADDSUB.vhd":8:7:8:50|Synthesizing work.dotp_multadd_dotp_multadd_0_hard_mult_addsub.def_arch 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box 
@N: CD630 :"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd":702:10:702:13|Synthesizing smartfusion2.macc.syn_black_box 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\dotp_multadd1.vhd":17:7:17:19|Synthesizing work.dotp_multadd1.rtl 
@N: CD630 :"E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_3_input\hdl\dotp_multadd1_dotp_multadd1_0_HARD_MULT_ADDSUB.vhd":8:7:8:52|Synthesizing work.dotp_multadd1_dotp_multadd1_0_hard_mult_addsub.def_arch 
@N|Running in 64-bit mode

