| Project Settings |
|---|
| Project Name | Extended_adder_2_input_syn | Implementation Name | synthesis |
| Top Module | work.Extended_adder_2_input | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
12 |
4 |
0 |
- |
0m:00s |
- |
2/17/2016
4:11:09 PM |
| (premap) | Complete |
3 |
1 |
0 |
0m:00s |
0m:00s |
136MB |
2/17/2016
4:11:11 PM |
| (fpga_mapper) | Complete |
10 |
1 |
0 |
0m:00s |
0m:00s |
137MB |
2/17/2016
4:11:12 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/17/2016
4:11:10 PM |
| Area Summary |
|---|
| |
| Carry Cells | 8 |
Sequential Cells | 52 |
| DSP Blocks (MACC)
(dsp_used) | 1 |
I/O Cells | 142 |
| Global Clock Buffers | 2 |
LUTs
(total_luts) | 8 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Extended_adder_2_input|clk | 100.0 MHz | 341.6 MHz | 7.072 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|