Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03M-SP1-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Linked File: Extended_adder_2_input_scck.rpt
Printing clock  summary report in "E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_2_input\synthesis\Extended_adder_2_input_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)

syn_allowed_resources : blockrams=69  set on top level netlist Extended_adder_2_input

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)



@S |Clock Summary
*****************

Start                          Requested     Requested     Clock        Clock              
Clock                          Frequency     Period        Type         Group              
-------------------------------------------------------------------------------------------
Extended_adder_2_input|clk     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
===========================================================================================

@W:MT530 : dotp_multadd_dotp_multadd_0_hard_mult_addsub.vhd(113) | Found inferred clock Extended_adder_2_input|clk which controls 52 sequential elements including U0.dotp_multadd_0.U0. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file E:\Libero_11p7_updates\downloaded\DSPAN_GL2_DF\IGLOO2\Extended_Adder\Extended_adder_2_input\synthesis\Extended_adder_2_input.sap. 
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 136MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Feb 17 11:27:30 2016

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